Datasheet

UNISONIC TECHNOLOGIES CO., LTD
LXXLD15
Preliminary
CMOS IC
0.8V REFERENCE ULTRA
LOW DROPOUT LINEAR
REGULATOR

DESCRIPTION
The UTC LXXLD15 is a typical LDO with the feature of very
low dropout voltage as low as 0.2V at output current 1.5A.
For normal operation, two supply voltages are necessary.
One called control voltage from other equipment can shutdown
the output voltage and it should pull and hold the voltage of EN
pin less than 0.3V. Another one is the main supply voltage
whose purpose is for main power conversion to keep the power
dissipation low and to make the dropout voltage lower.
Internally, in the UTC LXXLD15, there’re many functions
which can be seen in the block figure to prevent the IC from
being damaged. Internal Power-On-Reset (POR) circuit can
control the two supply voltages to prevent fault operations of the
circuit. And the thermal shutdown circuit is able to protect the
device from over thermal operation and a current limit function
will keep the device work safely under current over-load.
The UTC LXXLD15 can be used as an ideal to provide well
supply voltage in the applications, such as front-side-bus
termination on motherboard, NB applications, front side bus VTT
(1.2V/1.5A) and note book PC applications.

FEATURES
* Low Dropout VD=0.2V (typ.) @ IOUT=1.5A
* Low ESR Output Capacitor
* VREF=0.8V
* ±1.5% over Line, Load and Temperature Output Accuracy
* Fast Transient Response
* Output Voltage Adjustable through External Resistors
* POR (Power-On-Reset) controlling VCNTL and VIN

HSOP-8
* With internal Soft-Start
* Internal Current Limit Protection
* Internal Under Voltage Protection
* Hysteretic Thermal Shutdown
* With Power-OK Output (with a Delay Time)
* For Standby or Suspend Mode: Shutdown
ORDERING INFORMATION
Ordering Number
LXXLD15G-SH2-R
Note: XX: Output Voltage, refer to Marking Information.
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Copyright © 2014 Unisonic Technologies Co., Ltd
Package
HSOP-8
Packing
Tape Reel
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Preliminary
CMOS IC
MARKING INFORMATION
PACKAGE
VOLTAGE CODE
HSOP-8
AD: ADJ
MARKING
PIN CONFIGURATION
GND
1
8
EN
FB
2
7
POK
VIN
VOUT
3
6
VCNTL
VOUT
4
5
VIN
PIN DESCRIPTION
PIN NO.
1
PIN NAME
GND
2
FB
3
4
VOUT
5
VIN
6
VCNTL
7
POK
8
EN
DESCRIPTION
Ground pin.
There’s an external resistor divider connected to this pin which is necessary to give the
feedback voltage to the regulator. The external circuit is combined as the follow:
between VOUT and FB is R1(connected with a bypass capacitor which can improve the
load transient response),and between FB and ground is R2.The value of R2 and R1 are
recommended between 100Ω~10kΩ.So the output voltage is equals:
R1
VOUT=0.8·(1+
)(V)
R2
The output voltage pin of the regulator. There should be set an output capacitor to
compensate for closed-loop and also to improve transient responses. It’s necessary to
connect Pin 3 and Pin 4 together by wide tracks.
This pin is the main supply input.
It’s necessary to connect the Exposed Pad and VIN together for lower dropout voltage.
Monitoring this pin’s voltage can reset Power-On.
Power input pin of the control circuitry. Connecting this pin to a +5V (recommended)
supply voltage provides the bias for the control circuitry. The voltage at this pin is
monitored for Power-On Reset purpose.
Output pin for Power-OK signal output.
Being an open drain output, through senescing FB voltage, this pin can show the users
the output voltage’s states. That’s this pin will be low under any of these two situations:
the rising FB voltage is not above the VPOK threshold; the falling FB voltage is below the
VPNOK threshold. That indicates the output voltage is not ready for users.
Input Enable control pin. The output voltage can be shut down when this pin is below
0.3V. This pin’s voltage can be set higher than VCNTL voltage by an internal 10μA
current source, and then the regulator will begin working normally.
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Preliminary
CMOS IC
BLOCK DIAGRAM
EN
VCNTL
Power On
Reset
FB
FB
UV
+
Soft-Start and
Control Logic
VIN
0.4V
-
Thermal
Limit
EAMP
+
VREF
0.8V
VOUT
Current Limit
+
-
POK
Dealy
POK
90%
VREF
GND
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Preliminary
CMOS IC
ABSOLUTE MAXIMUM RATING
PARAMETER
SYMBOL
RATINGS
UNIT
Supply Voltage (VCNTL to GND)
VCNTL
-0.3 ~ +7
V
Supply Voltage (VIN to GND)
VIN
-0.3 ~ +3.9
V
EN and FB to GND
VI/O
-0.3 ~ VCNTL+0.3
V
POK to GND
VPOK
-0.3 ~ +7
V
Power Dissipation
PD
2.8
W
Lead Soldering Temperature, 10 Seconds
TSDR
260
°С
Junction Temperature
TJ
150
°С
Storage Temperature
TSTG
-65 ~ +150
°С
Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.

RECOMMENDED OPERATING CONDITIONS
PARAMETER
Control
Input
VCNTL=3.3±5%
Output Voltage
VCNTL=5.0±5%
Output Current
Junction Temperature
Supply Voltage
Supply Voltage

SYMBOL
VCNTL
VIN
VOUT
IOUT
TJ
RATINGS
3.1 ~ 6
1.1 ~ 3.5
0.8 ~ 1.2
0.8 ~ VIN-0.2
0 ~ 1.5
-40 ~ +125
UNIT
V
V
V
V
A
°С
THERMAL CHARACTERISTICS
PARAMETER
SYMBOL
RATINGS
UNIT
Junction to Ambient in Free Air (Note 1)
θJA
44
°C/W
Junction to Case (Note 2)
θJC
19
°C/W
Notes: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
The exposed pad of HSOP-8 is soldered directly on the PCB.
2. The Thermal Pad Temperature is measured on the PCB copper area connected to the thermal pad of
package.
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Preliminary
CMOS IC
ELECTRICAL CHARACTERISTICS
(Refer to the typical application circuit. These specifications apply over, VCNTL = 5V, VIN = 1.5V, VOUT = 1.2V and
TA = -40 ~ 85°C, unless otherwise specified. Typical values refer to TA = 25°C).
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNIT
VCNTL Nominal Supply Current
ICNTL
EN=VCNTL, VFB is well regulated
0.4 1
2 mA
VCNTL Shutdown Current
ISD
EN=GND
180 380 µA
VCNTL
VCNTL Rising
2.7 2.9 3.1 V
POR Threshold
VTHR
VIN
VIN Rising
0.8 0.9 1.0 V
VCNTL
0.4
V
POR Hysteresis
VHYS
VIN
0.5
V
Reference Voltage
VREF
FB=VOUT
0.8
V
Output Voltage Accuracy
IOUT=0A ~ 1.5A, TJ= -40 ~ 125°С
-1.5
+1.5 %
∆VOUT
Line Regulation
VCNTL=3.3 ~ 5.5V
-0.13
0.13 %/V
∆VIN × VOUT
∆VOUT
IOUT=0A ~ 1.5A
Load Regulation
0.06 0.15 %
VOUT
0.12 0.18 V
VCNTL=5V, IOUT=1.5A, VOUT=1.2V
TJ=25°С
VOUT=2.5V
0.17 0.23 V
Dropout Voltage
VD
0.25 V
VCNTL=5V, IOUT=1.5A, VOUT=1.2V
TJ=-40 ~ +125°С
VOUT=2.5V
0.3 V
VCNTL=5V, TJ=25°С
2.1 2.8 3.5 A
Current Limit
ILIM
VCNTL=5V, IOUT=1.5A, TJ=-40 ~ +125°С 1.8
A
Over Temperature Shutdown
OTS
TJ Rising
150
°С
Over Temperature Hysteresis
OTH
50
°С
Under-Voltage Threshold
VFB Falling
0.4
V
EN Logic High Threshold Voltage
VEN Rising
0.3 0.4 0.5 V
EN Hysteresis
30
mV
EN Pin Pull-Up Current
EN=GND
10
μA
Soft-Start Interval
TSS
2
ms
POK Threshold Voltage for Power OK
VPOK
VFB Rising
90% 92% 94% VREF
POK Threshold Voltage for Power Not
VPNOK
VFB Falling
79% 81% 83% VREF
OK
POK Low Voltage
POK sinks 5mA
0.25 0.4 V
POK Delay Time
TDELAY
1
3 10 ms
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Preliminary
CMOS IC
APPLICATION INFORMATION
1. Power Sequencing
When there’s no main voltage applied at VIN, it is suggested not to apply a voltage to VOUT for a long time.
Because the internal parasitic diode (between VOUT to VIN) will conduct and dissipate power, there’s no protection.
2. Output Capacitor
A proper output capacitor to maintain stability and improve transient response over temperature and current is
necessary. Proper ESR (equivalent series resistance) and capacitance of the output capacitor should be selected
properly for stability of the normal operation and good load transient response.
Many kinds of capacitors can be used as an output capacitor, such as ultra-low-ESR capacitors (like ceramic chip
capacitors), low-ESR bulk capacitors (like solid Tantalum, POSCap, and Aluminum electrolytic capacitors). And also
the value of the output capacitors’ can be increased without limit.
In the applications with large stepping load current, the low-ESR bulk capacitors are normally recommended.
Decoupling ceramic capacitors are recommended to be placed at the load and ground pins very closely and also
the impedance of the layout must be minimized.
3. Input Capacitor
In order to prevent the input rail from dropping, the proper input capacitor to supply current surge during stepping
load transients is required. Because the limited slew rate of the surge currents, more parasitic inductance needs
more input capacitance.
Ultra-low-ESR capacitors (>100mF, ESR<300mW) is recommended for the input capacitor.
4. Feedback Network
The following figure shows the feedback network between VOUT GND and FB pins. Working with the internal error
amplifier, the feedback network can provide proper frequency response for the UTC LXXLD15.
VOUT
VOUT
R1
VERR
EAMP
FB
VFB
VREF
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R2
C1
ESR
COUT
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Preliminary
CMOS IC
TYPICAL APPLICATION CIRCUITS
1. Using an Output Capacitor with ESR≥18mΩ
2. Using an MLCC as the Output Capacitor
R3=1kΩ
VCNTL +5V
CCNTL=1µF
6
VCNTL
POK
VIN 5
VIN +1.5V
CIN=22µF
7 POK
UTC VOUT 3
LXXLD15
VOUT 4
VOUT
+1.2V/1.5A
R1=39kΩ
EN
8 EN
C1=56pF
COUT=22µF
FB 2
GND
1
Enable
R2=78kΩ
VOUT (V)
1.05
1.5
1.8
R1 (kΩ)
43
27
15
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R2 (kΩ)
137.6
30.86
12
C1 (pF)
47
82
150
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Preliminary
CMOS IC
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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