INTERSIL X9313WS-3

X9313
®
Digitally Controlled Potentiometer (XDCP™)
Data Sheet
Linear, 32 Taps, 3 Wire Interface, Terminal
Voltages ± VCC
The Intersil X9313 is a digitally controlled potentiometer
(XDCP). The device consists of a resistor array, wiper
switches, a control section, and nonvolatile memory. The
wiper position is controlled by a 3-wire interface.
The potentiometer is implemented by a resistor array
composed of 31 resistive elements and a wiper switching
network. Between each element and at either end are tap
points accessible to the wiper terminal. The position of the
wiper element is controlled by the CS, U/D, and INC inputs.
The position of the wiper can be stored in nonvolatile
memory and then be recalled upon a subsequent power-up
operation.
The device can be used as a three-terminal potentiometer or
as a two-terminal variable resistor in a wide variety of
applications including:
April 18, 2007
FN8177.5
Features
• Solid-state potentiometer
• 3-wire serial interface
• 32 wiper tap points
- Wiper position stored in nonvolatile memory and
recalled on power-up
• 31 resistive elements
- Temperature compensated
- End to end resistance range ±20%
- Terminal voltages, -VCC to +VCC
• Low power CMOS
- VCC = 3V or 5V
- Active current, 3mA max.
- Standby current, 500µA max.
• Control
• High reliability
- Endurance, 100,000 data changes per bit
- Register data retention, 100 years
• Parameter adjustments
• RTOTAL values = 1kΩ, 10kΩ, 50kΩ
• Signal processing
• Packages
- 8 Ld SOIC, 8 Ld MSOP and 8 Ld PDIP
• Pb-free plus anneal available (RoHS compliant)
Block Diagram
DECODER
U/D
INC
CS
VCC (SUPPLY VOLTAGE)
CONTROL
AND
MEMORY
29
5-BIT
NONVOLATILE
MEMORY
RW/VW
DEVICE SELECT
(CS)
RH/VH
31
30
RH/VH
UP/DOWN
(U/D)
INCREMENT
(INC)
5-BIT
UP/DOWN
COUNTER
RL/VL
28
ONE OF
THIRTY-TWO
OUTPUTS
ACTIVE
AT A
TIME
TRANSFER
GATES
RESISTOR
ARRAY
2
VSS (GROUND)
VCC
VSS
GENERAL
STORE AND
RECALL
CONTROL
CIRCUITRY
1
0
RL/VL
RW/VW
DETAILED
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9313
Ordering Information
PART NUMBER
X9313UMI
PART
MARKING
13UI
VCC RANGE
(V)
RTOTAL
(kΩ)
TEMPERATURE
RANGE
(°C)
4.5 to 5.5
50
-40 to +85
-40 to +85
PACKAGE
PKG.
DWG. #
8 Ld MSOP
M8.118
X9313UMIZ (Note)
DDB
8 Ld MSOP (Pb-free)
M8.118
X9313UP
X9313UP
0 to +70
8 Ld PDIP
MDP0031
X9313US*
X9313U
0 to +70
8 Ld SOIC
MDP0027
X9313USZ* (Note)
X9313U Z
0 to +70
8 Ld SOIC (Pb-free)
M8.15
X9313USI
X9313U I
-40 to +85
8 Ld SOIC
MDP0027
X9313USIZ (Note)
X9313U ZI
-40 to +85
8 Ld SOIC (Pb-free)
M8.15
X9313WMZ (Note)
DDF
0 to +70
8 Ld MSOP (Pb-free)
M8.118
X9313WMI*
13WI
-40 to +85
8 Ld MSOP
M8.118
X9313WMIZ* (Note)
DDE
-40 to +85
X9313WP
X9313WP
X9313WPZ-3
X9313WP ZD
X9313WPI
10
8 Ld MSOP (Pb-free)
M8.118
8 Ld PDIP
MDP0031
-40 to +85
8 Ld PDIP*** (Pb-free)
MDP0031
X9313WP I
-40 to +85
8 Ld PDIP
MDP0031
X9313WPIZ
X9313WP ZI
-40 to +85
8 Ld PDIP*** (Pb-free)
MDP0031
X9313WS*, **
X9313WS
0 to +70
8 Ld SOIC
MDP0027
X9313WSZ*, ** (Note)
X9313W Z
0 to +70
8 Ld SOIC (Pb-free)
M8.15
X9313WSI*
X9313WS I
-40 to +85
8 Ld SOIC
MDP0027
X9313WSIZ* (Note)
X9313WS ZI
-40 to +85
8 Ld SOIC (Pb-free)
M8.15
X9313ZM
313Z
0 to +70
8 Ld MSOP
M8.118
X9313ZMZ (Note)
DDJ
0 to +70
8 Ld MSOP (Pb-free)
M8.118
X9313ZMI*, **
13ZI
-40 to +85
8 Ld MSOP
M8.118
X9313ZMIZ*, ** (Note)
DDH
-40 to +85
8 Ld MSOP (Pb-free)
M8.118
X9313ZP
X9313ZP
0 to +70
8 Ld PDIP
MDP0031
X9313ZPI
X9313ZP I
-40 to +85
8 Ld PDIP
MDP0031
X9313ZPIZ (Note)
X9313ZP ZI
-40 to +85
8 Ld PDIP*** (Pb-free)
MDP0031
X9313ZS*, **
X9313ZS
0 to +70
8 Ld SOIC
MDP0027
X9313ZSZ*, ** (Note)
X9313 Z
0 to +70
8 Ld SOIC (Pb-free)
M8.15
X9313ZSI*
X9313ZS I
-40 to +85
8 Ld SOIC
MDP0027
X9313ZSIZ* (Note)
X9313ZS ZI
-40 to +85
8 Ld SOIC (Pb-free)
M8.15
X9313UM-3T1
13UD
X9313UMZ-3T1 (Note)
0 to +70
1
0 to +70
8 Ld MSOP Tape and Reel M8.118
DDD
0 to +70
8 Ld MSOP Tape and Reel M8.118
(Pb-free)
X9313UMI-3*
13UE
-40 to +85
8 Ld MSOP
M8.118
X9313UMIZ-3* (Note)
13UEZ
-40 to +85
8 Ld MSOP (Pb-free)
M8.118
X9313US-3*, **
X9313U D
0 to +70
8 Ld SOIC
MDP0027
X9313USZ-3*, ** (Note)
X9313U ZD
0 to +70
8 Ld SOIC (Pb-free)
M8.15
X9313WM-3*
13WD
0 to +70
8 Ld MSOP
M8.118
X9313WMZ-3* (Note)
DDG
0 to +70
8 Ld MSOP (Pb-free)
M8.118
X9313WMI-3*
13WE
-40 to +85
8 Ld MSOP
M8.118
2
3 to 5.5
50
10
FN8177.5
April 18, 2007
X9313
Ordering Information (Continued)
PART NUMBER
PART
MARKING
X9313WMIZ-3* (Note)
13WEZ
X9313WS-3*
X9313W D
X9313WSZ-3* (Note)
X9313W ZD
X9313ZM-3*
13ZD
X9313ZMZ-3* (Note)
VCC RANGE
(V)
RTOTAL
(kΩ)
TEMPERATURE
RANGE
(°C)
PKG.
DWG. #
PACKAGE
-40 to +85
8 Ld MSOP (Pb-free)
M8.118
0 to +70
8 Ld SOIC
MDP0027
0 to +70
8 Ld SOIC (Pb-free)
M8.15
0 to +70
8 Ld MSOP
M8.118
DDK
0 to +70
8 Ld MSOP (Pb-free)
M8.118
X9313ZMI-3*
13ZE
-40 to +85
8 Ld MSOP
M8.118
X9313ZMIZ-3* (Note)
13ZEZ
-40 to +85
8 Ld MSOP (Pb-free)
M8.118
X9313ZP-3
X9313ZP D
0 to +70
8 Ld PDIP
MDP0031
X9313ZPZ-3 (Note)
X9313ZP ZD
0 to +70
8 Ld PDIP (Pb-free)***
MDP0031
3 to 5.5
1
X9313ZS-3*
X9313Z D
0 to +70
8 Ld SOIC
MDP0027
X9313ZSZ-3* (Note)
X9313Z ZD
0 to +70
8 Ld SOIC (Pb-free)
M8.15
X9313ZSI-3*
X9313Z E
-40 to +85
8 Ld SOIC
MDP0027
X9313ZSIZ-3* (Note)
X9313Z ZE
-40 to +85
8 Ld SOIC (Pb-free)
M8.15
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
*Add "T1" suffix for tape and reel.
**Add "T2" suffix for tape and reel.
***Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
Pin Descriptions
Chip Select (CS)
RH/VH and RL/VL
The high (RH/VH) and low (RL/VL) terminals of the X9313
are equivalent to the fixed terminals of a mechanical
potentiometer. The terminology of RL/VL and RH/VH
references the relative position of the terminal in relation to
wiper movement direction selected by the U/D input and not
the voltage potential on the terminal.
The device is selected when the CS input is LOW. The current
counter value is stored in nonvolatile memory when CS is
returned HIGH while the INC input is also HIGH. After the
store operation is complete the X9313 will be placed in the low
power standby mode until the device is selected once again.
Pinouts
X9313
8 LD PDIP, 8 LD SOIC
TOP VIEW
RW/VW
RW/VW is the wiper terminal and is equivalent to the
movable terminal of a mechanical potentiometer. The
position of the wiper within the array is determined by the
control inputs. The wiper terminal series resistance is
typically 40Ω at VCC = 5V.
INC
1
8
VCC
U/D
2
7
CS
X9313
RH/VH
3
6
RL/VL
VSS
4
5
RW/VW
Up/Down (U/D)
The U/D input controls the direction of the wiper movement
and whether the counter is incremented or decremented.
X9313
8 LD MSOP
TOP VIEW
Increment (INC)
The INC input is negative-edge triggered. Toggling INC will
move the wiper and either increment or decrement the
counter in the direction indicated by the logic level on the
U/D input.
RH/VH
VSS
RW/VW
RL/VL
3
8
U/D
7
INC
3
6
VCC
4
5
CS
1
2
X9313
FN8177.5
April 18, 2007
X9313
TABLE 1. PIN NAMES
SYMBOL
DESCRIPTION
RH/VH
High terminal
RW/VW
Wiper terminal
RL/VL
Low terminal
VSS
Ground
VCC
Supply voltage
U/D
Up/Down control input
INC
Increment control input
CS
Chip Select control input
Principles of Operation
There are three sections of the X9313: the input control,
counter and decode section; the nonvolatile memory; and
the resistor array. The input control section operates just like
an up/down counter. The output of this counter is decoded to
turn on a single electronic switch connecting a point on the
resistor array to the wiper output. Under the proper
conditions the contents of the counter can be stored in
nonvolatile memory and retained for future use. The resistor
array is comprised of 31 individual resistors connected in
series. At either end of the array and between each resistor
is an electronic switch that transfers the potential at that
point to the wiper.
The wiper, when at either fixed terminal, acts like its
mechanical equivalent and does not move beyond the last
position. That is, the counter does not wrap around when
clocked to either extreme.
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions. If
the wiper is moved several positions, multiple taps are
connected to the wiper for tIW (INC to VW change). The
RTOTAL value for the device can temporarily be reduced by
a significant amount if the wiper is moved several positions.
When the device is powered-down, the last wiper position
stored will be maintained in the nonvolatile memory. When
power is restored, the contents of the memory are recalled
and the wiper is set to the value last stored.
Instructions and Programming
The INC, U/D and CS inputs control the movement of the
wiper along the resistor array. With CS set LOW the device
is selected and enabled to respond to the U/D and INC
inputs. HIGH to LOW transitions on INC will increment or
decrement (depending on the state of the U/D input) a seven
bit counter. The output of this counter is decoded to select
one of thirty-two wiper positions along the resistive array.
The system may select the X9313, move the wiper and
deselect the device without having to store the latest wiper
position in nonvolatile memory. After the wiper movement is
performed as described above and once the new position is
reached, the system must keep INC LOW while taking CS
HIGH. The new wiper position will be maintained until
changed by the system or until a power-up/down cycle
recalled the previously stored data.
This procedure allows the system to always power-up to a
preset value stored in nonvolatile memory; then during
system operation minor adjustments could be made. The
adjustments might be based on user preference, system
parameter changes due to temperature drift, etc.
The state of U/D may be changed while CS remains LOW.
This allows the host system to enable the device and then
move the wiper up and down until the proper trim is attained.
TABLE 2. MODE SELECTION
CS
INC
U/D
MODE
L
H
Wiper up
L
L
Wiper down
H
X
Store wiper position
X
X
Standby current
L
X
No store, return to standby
L
H
Wiper up (not recommended)
L
L
Wiper down (not recommended)
H
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
The value of the counter is stored in nonvolatile memory
whenever CS transitions HIGH while the INC input is also
HIGH.
4
FN8177.5
April 18, 2007
X9313
Absolute Maximum Ratings
Recommended Operating Conditions
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on CS, INC, U/D, and
VCC with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V
Voltage on VH, VL, VW
with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6V to +7V
ΔV = |VH - VL|:
X9313Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4V
X9313W, X9313U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10V
Lead Temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . . +300°C
IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±8.8mA
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . 2.0kV
Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . . .200V
Temperature:
Commercial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage (VCC):
X9313 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ±10%
X9313-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 5.5V
Max Wiper current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±4.4mA
Power rating:
RTOTAL ≥ 10kΩ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10mW
RTOTAL 1kΩ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16mW
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications
CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional
operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Potentiometer CharacteristicsOver recommended operating conditions unless otherwise stated.
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS/NOTES
MIN
TYP
End-to-end resistance tolerance
MAX
UNIT
±20
%
VVH
VH terminal voltage
-VCC
+VCC
V
VVL
VL terminal voltage
-VCC
+VCC
V
RW
Wiper resistance
100
Ω
IW
Wiper current
±4.4
mA
IW = (VH - VL)/RTOTAL, VCC = 5V
Noise (Note 5)
Ref: 1kHz
Resolution
CH/CL/CW
(Note 5)
Absolute linearity (Note 1)
RW(n)(actual) - RW(n)(expected)
Relative linearity (Note 2)
RW(n+1) - (RW(n)+MI)
40
-120
dBV
3
%
±1
MI
(Note 3)
±0.2
MI
(Note 3)
RTOTAL temperature coefficient (Note 5)
±300
ppm/°C
Ratiometric temperature coefficient
(Note 5)
±20
ppm/°C
10/10/25
pF
Potentiometer capacitances
See Circuit #3
NOTES:
1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = (VW(n)(actual) - VW(n)(expected)) = ±1 MI maximum.
2. Relative linearity is a measure of the error in step size between taps = RW(n+1) - (RW(n) + MI) = ±0.2 MI.
3. 1 MI = minimum increment = RTOT/31.
5
FN8177.5
April 18, 2007
X9313
DC Operating Characteristics Over recommended operating conditions unless otherwise stated.
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS/NOTES
ICC
VCC active current
CS = VIL, U/D = VIL or VIH and
INC = 0.42/2.4V @ max tCYC
ISB
Standby supply current
CS = VCC - 0.3V, U/D and INC = VSS or
VCC - 0.3V
ILI
CS, INC, U/D input leakage current
VIN = VSS to VCC
VIH
CS, INC, U/D input HIGH current
VIL
CS, INC, U/D input LOW current
CIN
(Note 5)
CS, INC, U/D input capacitance
MIN
TYP
(Note 4)
MAX
UNIT
1
3
mA
200
500
µA
±10
µA
2
V
+0.8
VCC = 5V, VIN = VSS, TA = +25°C,
f = 1MHz
V
10
pF
Endurance and Data Retention
PARAMETER
MIN
UNIT
Minimum endurance
100,000
Data changes per bit
per register
Data retention
100
Years
VH/RH
VH/RH
RTOTAL
TEST POINT
RH
CW
CH
VS
TEST POINT
VW/RW
VL/RL
VL/RL
FIGURE 1. TEST CIRCUIT #1
6
VW/RW
VW
FORCE
CURRENT
FIGURE 2. TEST CIRCUIT #2
CL
RL
10pF
25pF
10pF
RW
FIGURE 3. CIRCUIT #3 SPICE MACRO
MODEL
FN8177.5
April 18, 2007
X9313
AC Operating Characteristics Over recommended operating conditions unless otherwise stated.
LIMITS
SYMBOL
PARAMETER
TYP
(Note 4)
MIN
MAX
UNIT
tCI
CS to INC setup
100
ns
tID
INC HIGH to U/D change
100
ns
tDI
U/D to INC setup
2.9
µs
tIL
INC LOW period
1
µs
tIH
INC HIGH period
1
µs
tIC
INC inactive to CS inactive
1
µs
tCPH
CS deselect time (STORE)
20
ms
tCPH
CS deselect time (NO STORE)
100
ns
INC to VW change
tIW
tCYC
5
INC cycle time
tR, tF (Note 5)
tPU (Note 5)
2
µs
INC input rise and fall time
500
Power-up to wiper stable
tR VCC (Note 5)
tWR (Note 5)
µs
10
VCC power-up rate
µs
0.2
50
Store cycle
µs
V/ms
10
ms
NOTES:
4. Typical values are for TA = +25°C and nominal supply voltage.
5. This parameter is not 100% tested.
Power-Up and Power-Down Requirements
1ms after VCC reaches its final value. The VCC ramp spec is
always in effect. In order to prevent unwanted tap position
changes, or an inadvertent store, bring the CS and INC high
before or concurrently with the VCC pin on power-up.
The recommended power-up sequence is to apply VCC/VSS
first, then the potentiometer voltages. During power-up, the
data sheet parameters for the DCP do not fully apply until
CS
tCYC
tCI
tIL
tIH
tCPH
tIC
90%
INC
90%
10%
tID
tDI
tF
tR
U/D
tIW
MI
(SEE NOTE)
VW
NOTE: MI IN THE AC TIMING DIAGRAM REFERS TO THE MINIMUM INCREMENTAL CHANGE IN THE VW OUTPUT DUE TO A CHANGE IN THE WIPER
POSITION.
FIGURE 4. AC TIMING DIAGRAM
7
FN8177.5
April 18, 2007
X9313
Applications Information
computer-based digital controls, and (3) the retentivity of
nonvolatile memory used for the storage of multiple
potentiometer settings or data.
Electronic digitally controlled potentiometers (XDCP) provide
three powerful application advantages; (1) the variability and
reliability of a solid-state potentiometer, (2) the flexibility of
Basic Configurations of Electronic Potentiometers
VR
VR
VH
VW/RW
VL
I
THREE-TERMINAL POTENTIOMETER;
VARIABLE VOLTAGE DIVIDER
TWO-TERMINAL VARIABLE RESISTOR;
VARIABLE CURRENT
Basic Circuits
BUFFERED REFERENCE VOLTAGE
CASCADING TECHNIQUES
R1
+V
NONINVERTING AMPLIFIER
+5V
+V
VS
+V
LM308A
+
+5V
OP-07
+
VREF
VO
–
VW
–
X
VW/RW
VOUT
-5V
R2
+V
-5V
R1
VW
VOUT = VW/RW
(a)
(b)
VO = (1 + R2/R1)VS
VOLTAGE REGULATOR
R1
VIN
VO (REG)
317
COMPARATOR WITH HYSTERESIS
OFFSET VOLTAGE ADJUSTMENT
R2
VS
VS
LT311A
–
+
100kΩ
R1
–
VO
+
10kΩ
+12V
10kΩ
}
10kΩ
R2
}
TL072
Iadj
VO (REG) = 1.25V (1 + R2/R1) + IADJ R2
VO
R1
R2
VUL = [R1/(R1 + R2)] VO(max)
VLL = [R1/(R1 + R2)] VO(min)
-12V
(FOR ADDITIONAL CIRCUITS SEE AN115)
8
FN8177.5
April 18, 2007
X9313
Mini Small Outline Plastic Packages (MSOP)
N
M8.118 (JEDEC MO-187AA)
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1
INCHES
E
-B-
INDEX
AREA
1 2
0.20 (0.008)
A B C
TOP VIEW
4X θ
0.25
(0.010)
R1
R
GAUGE
PLANE
A
SEATING
PLANE -C-
A2
A1
b
-He
D
0.10 (0.004)
4X θ
L1
SEATING
PLANE
C
0.20 (0.008)
C
a
CL
E1
C D
MAX
MIN
MAX
NOTES
0.037
0.043
0.94
1.10
-
A1
0.002
0.006
0.05
0.15
-
A2
0.030
0.037
0.75
0.95
-
b
0.010
0.014
0.25
0.36
9
c
0.004
0.008
0.09
0.20
-
D
0.116
0.120
2.95
3.05
3
E1
0.116
0.120
2.95
3.05
4
0.026 BSC
-B-
0.65 BSC
-
E
0.187
0.199
4.75
5.05
-
L
0.016
0.028
0.40
0.70
6
0.037 REF
N
C
0.20 (0.008)
MIN
A
L1
-A-
SIDE VIEW
SYMBOL
e
L
MILLIMETERS
0.95 REF
8
R
0.003
R1
0
α
-
8
-
0.07
0.003
-
5o
15o
0o
6o
7
-
-
0.07
-
-
5o
15o
-
0o
6o
Rev. 2 01/03
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. - H - Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (0.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Datums -A -H- .
and - B - to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only.
9
FN8177.5
April 18, 2007
X9313
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
H
0.25(0.010) M
B M
INCHES
E
SYMBOL
-B-
1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
MIN
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
e
α
B S
0.050 BSC
-
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
α
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
1.27 BSC
H
N
NOTES:
MILLIMETERS
8
0°
8
8°
0°
7
8°
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
10
FN8177.5
April 18, 2007
X9313
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M C A B
e
H
C
A2
GAUGE
PLANE
SEATING
PLANE
A1
0.004 C
0.010 M C A B
L
b
0.010
4° ±4°
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SYMBOL
SO-14
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
TOLERANCE
NOTES
A
0.068
0.068
0.068
0.104
0.104
0.104
0.104
MAX
-
A1
0.006
0.006
0.006
0.007
0.007
0.007
0.007
±0.003
-
A2
0.057
0.057
0.057
0.092
0.092
0.092
0.092
±0.002
-
b
0.017
0.017
0.017
0.017
0.017
0.017
0.017
±0.003
-
c
0.009
0.009
0.009
0.011
0.011
0.011
0.011
±0.001
-
D
0.193
0.341
0.390
0.406
0.504
0.606
0.704
±0.004
1, 3
E
0.236
0.236
0.236
0.406
0.406
0.406
0.406
±0.008
-
E1
0.154
0.154
0.154
0.295
0.295
0.295
0.295
±0.004
2, 3
e
0.050
0.050
0.050
0.050
0.050
0.050
0.050
Basic
-
L
0.025
0.025
0.025
0.030
0.030
0.030
0.030
±0.009
-
L1
0.041
0.041
0.041
0.056
0.056
0.056
0.056
Basic
-
h
0.013
0.013
0.013
0.020
0.020
0.020
0.020
Reference
-
16
20
24
28
Reference
-
N
SO-8
SO16
(0.150”)
8
14
16
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
11
FN8177.5
April 18, 2007
X9313
Plastic Dual-In-Line Packages (PDIP)
E
D
A2
SEATING
PLANE
L
N
A
PIN #1
INDEX
E1
c
e
b
A1
NOTE 5
1
eA
eB
2
N/2
b2
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE
INCHES
SYMBOL
PDIP8
PDIP14
PDIP16
PDIP18
PDIP20
TOLERANCE
A
0.210
0.210
0.210
0.210
0.210
MAX
A1
0.015
0.015
0.015
0.015
0.015
MIN
A2
0.130
0.130
0.130
0.130
0.130
±0.005
b
0.018
0.018
0.018
0.018
0.018
±0.002
b2
0.060
0.060
0.060
0.060
0.060
+0.010/-0.015
c
0.010
0.010
0.010
0.010
0.010
+0.004/-0.002
D
0.375
0.750
0.750
0.890
1.020
±0.010
E
0.310
0.310
0.310
0.310
0.310
+0.015/-0.010
E1
0.250
0.250
0.250
0.250
0.250
±0.005
e
0.100
0.100
0.100
0.100
0.100
Basic
eA
0.300
0.300
0.300
0.300
0.300
Basic
eB
0.345
0.345
0.345
0.345
0.345
±0.025
L
0.125
0.125
0.125
0.125
0.125
±0.010
N
8
14
16
18
20
Reference
NOTES
1
2
Rev. C 2/07
NOTES:
1. Plastic or metal protrusions of 0.010” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.
4. Dimension eB is measured with the lead tips unconstrained.
5. 8 and 16 lead packages have half end-leads as shown.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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12
FN8177.5
April 18, 2007