HA-5020 ® Data Sheet June 5, 2006 100MHz Current Feedback Video Amplifier With Disable FN2845.11 Features • Wide Unity Gain Bandwidth . . . . . . . . . . . . . . . . . 100MHz The HA-5020 is a wide bandwidth, high slew rate amplifier optimized for video applications and gains between 1 and 10. Manufactured on Intersil’s Reduced Feature Complementary Bipolar DI process, this amplifier uses current mode feedback to maintain higher bandwidth at a given gain than conventional voltage feedback amplifiers. Since it is a closed loop device, the HA-5020 offers better gain accuracy and lower distortion than open loop buffers. The HA-5020 features low differential gain and phase and will drive two double terminated 75Ω coax cables to video levels with low distortion. Adding a gain flatness performance of 0.1dB makes this amplifier ideal for demanding video applications. The bandwidth and slew rate of the HA-5020 are relatively independent of closed loop gain. The 100MHz unity gain bandwidth only decreases to 60MHz at a gain of 10. The HA-5020 used in place of a conventional op amp will yield a significant improvement in the speed power product. To further reduce power, HA-5020 has a disable function which significantly reduces supply current, while forcing the output to a true high impedance state. This allows the outputs of multiple amplifiers to be wire-OR’d into multiplexer configurations. The device also includes output short circuit protection and output offset voltage adjustment. For multi channel versions of the HA-5020 see the HA5022 dual with disable, HA5023 dual, HA5013 triple and HA5024 quad with disable op amp data sheets. • Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800V/µs • Output Current . . . . . . . . . . . . . . . . . . . . . . . ±30mA (Min) • Drives 3.5V into 75Ω • Differential Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.03% • Differential Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.03° • Low Input Voltage Noise . . . . . . . . . . . . . . . . . 4.5nV/√Hz • Low Supply Current . . . . . . . . . . . . . . . . . . . . 10mA (Max) • Wide Supply Range . . . . . . . . . . . . . . . . . . . ±5V to ±15V • Output Enable/Disable • High Performance Replacement for EL2020 • Pb-Free Plus Anneal Available (RoHS Compliant) Applications • Unity Gain Video/Wideband Buffer • Video Gain Block • Video Distribution Amp/Coax Cable Driver • Flash A/D Driver • Waveform Generator Output Driver • Current to Voltage Converter; D/A Output Buffer • Radar Systems • Imaging Systems Pinout HA-5020 (PDIP, SOIC) TOP VIEW BAL 1 IN- 2 IN+ 3 V- 4 - + 1 8 DISABLE 7 V+ 6 OUT 5 BAL CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2002, 2005-2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HA-5020 Ordering Information PART NUMBER PART MARKING TEMP. RANGE (°C) PACKAGE PKG. DWG. # HA3-5020-5 HA3-5020-5 0 to 75 8 Ld PDIP E8.3 HA3-5020-5Z (Note) HA3-5020-5Z 0 to 75 8 Ld PDIP (Pb-free) E8.3 HA9P5020-5 50205 0 to 75 8 Ld SOIC M8.15 HA9P5020-5Z (Note) 50205Z 0 to 75 8 Ld SOIC (Pb-free) M8.15 HA9P5020-5X96 50205 0 to 75 8 Ld SOIC Tape and Reel M8.15 HA9P5020-5ZX96 (Note) 50205Z 0 to 75 8 Ld SOIC Tape and Reel (Pb-free) M8.15 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2 FN2845.11 June 5, 2006 HA-5020 Absolute Maximum Ratings (Note 1) Thermal Information Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . 36V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VSUPPLY Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10V Output Current . . . . . . . . . . . . . . . . . . . . . . . Short Circuit Protected Thermal Resistance (Typical, Note 2) θJA (°C/W) θJC (°C/W) PDIP Package . . . . . . . . . . . . . . . . . . . 120 N/A SOIC Package . . . . . . . . . . . . . . . . . . . 165 N/A Maximum Junction Temperature (Plastic Packages, Note 1) . . . 150°C Maximum Storage Temperature Range . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C (SOIC - Lead Tips Only) Operating Conditions Temperature Range HA-5020-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Maximum power dissipation, including output load, must be designed to maintain junction temperature below 150°C for plastic packages. 1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications VSUPPLY = ±15V, RF = 1kΩ, AV = +1, RL = 400Ω, CL ≤ 10pF, Unless Otherwise Specified TEMP. (°C) MIN TYP MAX UNITS Input Offset Voltage (Notes 3, 14) 25 - 2 8 mV Full - - 10 mV Average Input Offset Voltage Drift Full - 10 - µV/°C 25 60 - - dB Full 50 - - dB 25 64 - - dB Full 60 - - dB PARAMETER TEST CONDITIONS INPUT CHARACTERISTICS VIO Common Mode Rejection Ratio (Note 14) VIO Power Supply Rejection Ratio (Note 14) VCM = ±10V ±4.5V ≤ VS ≤ ±18V Non-Inverting Input (+IN) Current (Note 14) VCM = ±10V +IN Common Mode Rejection ±4.5V ≤ VS ≤ ±18V +IN Power Supply Rejection Inverting Input (-IN) Current (Note 14) VCM = ±10V -IN Common Mode Rejection ±4.5V ≤ VS ≤ ±18V -IN Power Supply Rejection 25 - 3 8 µA Full - - 20 µA 25 - - 0.1 µA/V Full - - 0.5 µA/V 25 - - 0.06 µA/V Full - - 0.2 µA/V 25 - 12 20 µA Full - 25 50 µA 25 - - 0.4 µA/V Full - - 0.5 µA/V 25 - - 0.2 µA/V Full - - 0.5 µA/V 25 3500 - - V/mA Full 1000 - - V/mA 25 70 - - dB TRANSFER CHARACTERISTICS Transimpedance (Notes 9, 14) Open Loop DC Voltage Gain (Note 9) RL = 400Ω, VOUT = ±10V Open Loop DC Voltage Gain RL = 100Ω, VOUT = ±2.5V 3 Full 65 - - dB 25 60 - - dB Full 55 - - dB FN2845.11 June 5, 2006 HA-5020 Electrical Specifications VSUPPLY = ±15V, RF = 1kΩ, AV = +1, RL = 400Ω, CL ≤ 10pF, Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS TEMP. (°C) MIN TYP MAX UNITS 25 to 85 ±12 ±12.7 - V OUTPUT CHARACTERISTICS RL = 150Ω Output Voltage Swing (Note 14) Output Current (Guaranteed by Output Voltage Test) -40 to 0 ±11 ±11.8 - V 25 ±30 ±31.7 - mA Full ±27.5 - - mA Full - 7.5 10 mA Full - 5 7.5 mA POWER SUPPLY CHARACTERISTICS Quiescent Supply Current (Note 14) Supply Current, Disabled (Note 14) DISABLE = 0V Disable Pin Input Current DISABLE = 0V Full - 1.0 1.5 mA Minimum Pin 8 Current to Disable (Note 4) Full 350 - - µA Maximum Pin 8 Current to Enable (Note 5) Full - - 20 µA 25 600 800 - V/µs Full 500 700 - V/µs 25 9.6 12.7 - MHz Full 8.0 11.1 - MHz Rise Time (Note 8) 25 - 5 - ns Fall Time (Note 8) 25 - 5 - ns AC CHARACTERISTICS (AV = +1) Slew Rate (Note 6) Full Power Bandwidth (Note 7) (Guaranteed by Slew Rate Test) Propagation Delay (Notes 8, 14) 25 - 6 - ns -3dB Bandwidth (Note 14) VOUT = 100mV 25 - 100 - MHz Settling Time to 1% 10V Output Step 25 - 45 - ns Settling Time to 0.25% 10V Output Step 25 - 100 - ns 25 900 1100 - V/µs AC CHARACTERISTICS (AV = +10, RF = 383Ω) Slew Rate (Notes 6, 9) Full 700 - - V/µs 25 14.3 17.5 - MHz Full 11.1 - - MHz Rise Time (Note 8) 25 - 8 - ns Fall Time (Note 8) 25 - 8 - ns Full Power Bandwidth (Note 7) (Guaranteed by Slew Rate Test) Propagation Delay (Notes 8, 14) 25 - 9 - ns -3dB Bandwidth VOUT = 100mV 25 - 60 - MHz Settling Time to 1% 10V Output Step 25 - 55 - ns Settling Time to 0.1% 10V Output Step 25 - 90 - ns INTERSIL VALUE ADDED SPECIFICATIONS Input Noise Voltage (Note 14) f = 1kHz 25 - 4.5 - nV/√Hz +Input Noise Current (Note 14) f = 1kHz 25 - 2.5 - pA/√Hz -Input Noise Current (Note 14) f = 1kHz 25 - 25 - pA/√Hz Input Common Mode Range Full ±10 ±12 - V -IBIAS Adjust Range (Note 3) Full ±25 ±40 - µA Overshoot (Note 14) 25 - 7 - % 4 FN2845.11 June 5, 2006 HA-5020 Electrical Specifications VSUPPLY = ±15V, RF = 1kΩ, AV = +1, RL = 400Ω, CL ≤ 10pF, Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS TEMP. (°C) MIN TYP MAX UNITS Output Current, Short Circuit (Note 14) VIN = ±10V, VOUT = 0V Full ±50 ±65 - mA Output Current, Disabled (Note 14) DISABLE = 0V, VOUT = ±10V Full - - 1 µA Output Disable Time (Notes 10, 14) 25 - 10 - µs Output Enable Time (Notes 11, 14) 25 - 200 - ns Supply Voltage Range 25 ±5 - ±15 V DISABLE = 0V 25 - 6 - pF Differential Gain (Notes 13, 14) RL = 150Ω 25 - 0.03 - % Differential Phase (Notes 13, 14) RL = 150Ω 25 - 0.03 - ° Gain Flatness To 5MHz 25 - 0.1 - dB Output Capacitance, Disabled (Note 12) VIDEO CHARACTERISTICS Electrical Specifications V+ = +5V, V- = -5V, RF = 1kΩ, AV = +1, RL = 400Ω, CL ≤10pF, Unless Otherwise Specified. Parameters are not tested. The limits are guaranteed based on lab characterizations, and reflect lot-to-lot variation. TEMP. (°C) MIN TYP MAX UNITS Input Offset Voltage (Notes 3, 14) 25 - 2 8 mV Full - - 10 mV Average Input Offset Voltage Drift Full - 10 - µV/°C VIO Common Mode Rejection Ratio (Notes 14, 15) 25 50 - - dB Full 35 - - dB PARAMETER TEST CONDITIONS INPUT CHARACTERISTICS VIO Power Supply Rejection Ratio (Note 14) ±3.5V ≤ VS ≤ ±6.5V Non-Inverting Input (+IN) Current (Note 14) +IN Common Mode Rejection (Note 15) ±3.5V ≤ VS ≤ ±6.5V +IN Power Supply Rejection Inverting Input (-IN) Current (Note 14) -IN Common Mode Rejection (Note 15) ±3.5V ≤ VS ≤ ±6.5V -IN Power Supply Rejection 25 55 - - dB Full 50 - - dB 25 - 3 8 µA Full - - 20 µA 25 - - 0.1 µA/V Full - - 0.5 µA/V 25 - - 0.06 µA/V Full - - 0.2 µA/V 25 - 12 20 µA Full - 25 50 µA 25 - - 0.4 µA/V Full - - 0.5 µA/V 25 - - 0.2 µA/V Full - - 0.5 µA/V 25 1000 - - V/mA Full 850 - - V/mA 25 65 - - dB Full 60 - - dB TRANSFER CHARACTERISTICS Transimpedance (Notes 9, 14) RL = 400Ω, VOUT = ±2.5V Open Loop DC Voltage Gain 5 FN2845.11 June 5, 2006 HA-5020 Electrical Specifications V+ = +5V, V- = -5V, RF = 1kΩ, AV = +1, RL = 400Ω, CL ≤10pF, Unless Otherwise Specified. Parameters are not tested. The limits are guaranteed based on lab characterizations, and reflect lot-to-lot variation. (Continued) PARAMETER Open Loop DC Voltage Gain TEST CONDITIONS RL = 100Ω, VOUT = ±2.5V TEMP. (°C) MIN TYP MAX UNITS 25 50 - - dB Full 45 - - dB 25 to 85 ±2.5 ±3.0 - V -40 to 0 ±2.5 ±3.0 - V 25 ±16.6 ±20 - mA Full ±16.6 ±20 - mA Full - 7.5 10 mA OUTPUT CHARACTERISTICS Output Voltage Swing (Note 14) Output Current (Guaranteed by Output Voltage Test) RL = 100Ω POWER SUPPLY CHARACTERISTICS Quiescent Supply Current (Note 14) Supply Current, Disabled (Note 14) DISABLE = 0V Full - 5 7.5 mA Disable Pin Input Current DISABLE = 0V Full - 1.0 1.5 mA Minimum Pin 8 Current to Disable (Note 16) Full 350 - - µA Maximum Pin 8 Current to Enable (Note 5) Full - - 20 µA Slew Rate (Note 17) 25 215 400 - V/µs Full Power Bandwidth (Note 18) 25 22 28 - MHz Rise Time (Note 8) 25 - 6 - ns AC CHARACTERISTICS (AV = +1) Fall Time (Note 8) 25 - 6 - ns Propagation Delay (Note 8) 25 - 6 - ns Overshoot 25 - 4.5 - % 25 - 125 - MHz -3dB Bandwidth (Note 14) VOUT = 100mV Settling Time to 1% 2V Output Step 25 - 50 - ns Settling Time to 0.25% 2V Output Step 25 - 75 - ns Slew Rate (Note 17) 25 - 475 - V/µs Full Power Bandwidth (Note 18) 25 - 26 - MHz Rise Time (Note 8) 25 - 6 - ns Fall Time (Note 8) 25 - 6 - ns Propagation Delay (Note 8) 25 - 6 - ns AC CHARACTERISTICS (AV = +2, RF = 681Ω) Overshoot 25 - 12 - % -3dB Bandwidth (Note 14) VOUT = 100mV 25 - 95 - MHz Settling Time to 1% 2V Output Step 25 - 50 - ns Settling Time to 0.25% 2V Output Step 25 - 100 - ns Slew Rate (Note 17) 25 350 475 - V/µs Full Power Bandwidth (Note 18) 25 28 38 - MHz Rise Time (Note 8) 25 - 8 - ns AC CHARACTERISTICS (AV = +10, RF = 383Ω) Fall Time (Note 8) 25 - 9 - ns Propagation Delay (Note 8) 25 - 9 - ns Overshoot 25 - 1.8 - % 6 FN2845.11 June 5, 2006 HA-5020 Electrical Specifications V+ = +5V, V- = -5V, RF = 1kΩ, AV = +1, RL = 400Ω, CL ≤10pF, Unless Otherwise Specified. Parameters are not tested. The limits are guaranteed based on lab characterizations, and reflect lot-to-lot variation. (Continued) PARAMETER TEST CONDITIONS TEMP. (°C) MIN TYP MAX UNITS -3dB Bandwidth (Note 14) VOUT = 100mV 25 - 65 - MHz Settling Time to 1% 2V Output Step 25 - 75 - ns Settling Time to 0.25% 2V Output Step 25 - 130 - ns Input Noise Voltage (Note 14) f = 1kHz 25 - 4.5 - nV/√Hz +Input Noise Current (Note 14) f = 1kHz 25 - 2.5 - pA/√Hz -Input Noise Current (Note 14) f = 1kHz 25 - 25 - pA/√Hz INTERSIL VALUE ADDED SPECIFICATIONS Full ±2.5V − - V Output Current, Short Circuit VIN = ±2.5V, VOUT = 0V Full ±40 ±60 - mA Output Current, Disabled (Note 14) DISABLE = 0V, VOUT = ±2.5V, VIN = 0V Full - - 2 µA Output Disable Time (Notes 14, 20) 25 - 40 - µs Output Enable Time (Notes 14, 21) 25 - 40 - ns Supply Voltage Range 25 ±5 - ±15 V DISABLE = 0V 25 - 6 - pF Differential Gain (Notes 13, 14) RL = 150Ω 25 - 0.03 - % Differential Phase (Notes 13, 14) RL = 150Ω 25 - 0.03 - ° Gain Flatness To 5MHz 25 - 0.1 - dB Input Common Mode Range Output Capacitance, Disabled (Note 19) VIDEO CHARACTERISTICS NOTES: 2. Suggested VOS Adjust Circuit: The inverting input current (-IBIAS) can be adjusted with an external 10kΩ pot between pins 1 and 5, wiper connected to V+. Since -IBIAS flows through the feedback resistor (RF), the result is an adjustment in offset voltage. The amount of offset voltage adjustment is determined by the value of RF (∆VOS = ∆-IBIAS*RF). 3. RL = 100Ω, VIN = 10V. This is the minimum current which must be pulled out of the Disable pin in order to disable the output. The output is considered disabled when -10mV ≤ VOUT ≤ +10mV. 4. VIN = 0V. This is the maximum current that can be pulled out of the Disable pin with the HA-5020 remaining enabled. The HA-5020 is considered disabled when the supply current has decreased by at least 0.5mA. 5. VOUT switches from -10V to +10V, or from +10V to -10V. Specification is from the 25% to 75% points. 6. Slew Rate FPBW = --------------------------- ; V PEAK = 10V. 2πV PEAK RL = 100Ω, VOUT = 1V. Measured from 10% to 90% points for rise/fall times; from 50% points of input and output for propagation delay. This parameter is not tested. The limits are guaranteed based on lab characterization, and reflect lot-to-lot variation. VIN = +10V, Disable = +15V to 0V. Measured from the 50% point of Disable to VOUT = 0V. VIN = +10V, Disable = 0V to +15V. Measured from the 50% point of Disable to VOUT = 10V. VIN = 0V, Force VOUT from 0V to ±10V, tR = tF = 50ns. Measured with a VM700A video tester using a NTC-7 composite VITS. See “Typical Performance Curves” for more information. VCM = ±2.5V. At -40°C product is tested at VCM = ±2.25V because short test duration does not allow self heating. RL = 100Ω. VIN = 2.5V. This is the minimum current which must be pulled out of the Disable pin in order to disable the output. The output is considered disabled when -10mV ≤ VOUT ≤ +10mV. 16. VOUT switches from -2V to +2V, or from +2V to -2V. Specification is from the 25% to 75% points. Slew Rate 17. FPBW = --------------------------- ; V PEAK = 2V . 2πV PEAK 7. 8. 9. 10. 11. 12. 13. 14. 15. 18. VIN = 0V, Force VOUT from 0V to ±2.5V, tR = tF = 50ns. 19. VIN = +2V, Disable = +5V to 0V. Measured from the 50% point of Disable to VOUT = 0V. 20. VIN = +2V, Disable = 0V to +5V. Measured from the 50% point of Disable to VOUT = 2V. 7 FN2845.11 June 5, 2006 HA-5020 Test Circuits and Waveforms + - DUT 50Ω HP4195 NETWORK ANALYZER 50Ω FIGURE 1. TEST CIRCUIT FOR TRANSIMPEDANCE MEASUREMENTS VIN VIN + + DUT 50Ω DUT RL 400Ω VOUT - 50Ω RL 100Ω VOUT - RI 681Ω RF , 681Ω RF , 1kΩ FIGURE 2. SMALL SIGNAL PULSE RESPONSE CIRCUIT FIGURE 3. LARGE SIGNAL PULSE RESPONSE CIRCUIT VIN VIN VOUT VOUT Vertical Scale: VIN = 100mV/Div., VOUT = 100mV/Div. Horizontal Scale: 20ns/Div. FIGURE 4. SMALL SIGNAL RESPONSE 8 Vertical Scale: VIN = 1V/Div., VOUT = 1V/Div. Horizontal Scale: 50ns/Div. FIGURE 5. LARGE SIGNAL RESPONSE FN2845.11 June 5, 2006 V- V+ 9 D1 R1 60K QN3 R4 800 QN2 R3 6K QN1 QP1 R2 800 R33 800 QN4 QP2 R5 2.5K DIS R7 15K R6 15K QP3 R8 1.25K D2 QP4 QN7 QN6 QN5 R9 820 QP7 QN9 QP6 QN8 QP5 R10 820 R13 1K R12 280 +IN R11 1K QN11 QN10 QP8 R14 280 QP10 QP9 QN14 R16 400 QP13 QN13 QP12 QN12 QP11 R15 400 QP14 QN16 R24 140 R21 140 R20 140 R23 400 R25 140 QN15 C2 1.4pF C1 1.4pF QP15 R18 280 R22 280 -IN R17 280 R19 400 R26 200 QN18 R25 20 QN17 QP16 R27 200 QN20 QP17 R28 20 R26 200 QN19 QP18 R33 2K QP20 QP19 R30 7 5 R31 R29 9.5 R32 5 QN21 O HA-5020 Schematic Diagram FN2845.11 June 5, 2006 HA-5020 Application Information Driving Capacitive Loads Optimum Feedback Resistor The plots of inverting and non-inverting frequency response illustrate the performance of the HA-5020 in various closed loop gain configurations. Although the bandwidth dependency on closed loop gain isn’t as severe as that of a voltage feedback amplifier, there can be an appreciable decrease in bandwidth at higher gains. This decrease may be minimized by taking advantage of the current feedback amplifier’s unique relationship between bandwidth and RF . All current feedback amplifiers require a feedback resistor, even for unity gain applications, and RF, in conjunction with the internal compensation capacitor, sets the dominant pole of the frequency response. Thus, the amplifier’s bandwidth is inversely proportional to RF. The HA-5020 design is optimized for a 1000Ω RF at a gain of +1. Decreasing RF in a unity gain application decreases stability, resulting in excessive peaking and overshoot. At higher gains the amplifier is more stable, so RF can be decreased in a trade-off of stability for bandwidth. The table below lists recommended RF values for various gains, and the expected bandwidth. GAIN (ACL) RF (Ω) BANDWIDTH (MHz) -1 750 100 +1 1000 125 +2 681 95 +5 1000 52 +10 383 65 -10 750 22 PC Board Layout The frequency response of this amplifier depends greatly on the amount of care taken in designing the PC board. The use of low inductance components such as chip resistors and chip capacitors is strongly recommended. If leaded components are used the leads must be kept short especially for the power supply decoupling components and those components connected to the inverting input. Attention must be given to decoupling the power supplies. A large value (10µF) tantalum or electrolytic capacitor in parallel with a small value (0.1µF) chip capacitor works well in most cases. A ground plane is strongly recommended to control noise. Care must also be taken to minimize the capacitance to ground seen by the amplifier’s inverting input (-IN). The larger this capacitance, the worse the gain peaking, resulting in pulse overshoot and possible instability. It is recommended that the ground plane be removed under traces connected to -IN, and that connections to -IN be kept as short as possible to minimize the capacitance from this node to ground. 10 Capacitive loads will degrade the amplifier’s phase margin resulting in frequency response peaking and possible oscillations. In most cases the oscillation can be avoided by placing an isolation resistor (R) in series with the output as shown in Figure 6. VIN R + RT - VOUT CL RF RI FIGURE 6. PLACEMENT OF THE OUTPUT ISOLATION RESISTOR, R The selection criteria for the isolation resistor is highly dependent on the load, but 27Ω has been determined to be a good starting value. Enable/Disable Function When enabled the amplifier functions as a normal current feedback amplifier with all of the data in the electrical specifications table being valid and applicable. When disabled the amplifier output assumes a true high impedance state and the supply current is reduced significantly. The circuit shown in Figure 7 is a simplified schematic of the enable/disable function. The large value resistors in series with the DISABLE pin makes it appear as a current source to the driver. When the driver pulls this pin low current flows out of the pin and into the driver. This current, which may be as large as 350µA when external circuit and process variables are at their extremes, is required to insure that point “A” achieves the proper potential to disable the output. The driver must have the compliance and capability of sinking all of this current. +VCC R6 15K D1 ENABLE/ DISABLE INPUT R7 15K R10 R33 QP18 R8 A QP3 FIGURE 7. SIMPLIFIED SCHEMATIC OF ENABLE/DISABLE FUNCTION When VCC is +5V the DISABLE pin may be driven with a dedicated TTL gate. The maximum low level output voltage of the TTL gate, 0.4V, has enough compliance to insure that the amplifier will always be disabled even though D1 will not turn on, and the TTL gate will sink enough current to keep point “A” at its proper voltage. When VCC is greater than +5V the DISABLE pin should be driven with an open collector device that has a breakdown rating greater than VCC . FN2845.11 June 5, 2006 HA-5020 Referring to Figure 7, it can be seen that R6 will act as a pull-up resistor to +VCC if the DISABLE pin is left open. In those cases where the enable/disable function is not required on all circuits some circuits can be permanently enabled by letting the DISABLE pin float. If a driver is used to set the enable/disable level, be sure that the driver does not sink more than 20µA when the DISABLE pin is at a high level. TTL gates, especially CMOS versions, do not violate this criteria so it is permissible to control the enable/disable function with TTL. such as an A/D converter. The first problem is the low source impedance which tends to make amplifiers oscillate and causes gain errors. The second problem is the multiplexer which supplies no gain, introduces all kinds of distortion and limits the frequency response. Using op amps which have an enable/disable function, such as the HA-5020, eliminates the multiplexer problems because the external mux chip is not needed, and the HA-5020 can drive low impedance (large capacitance) loads if a series isolation resistor is used. Typical Applications Referring to Figure 9, both inputs are terminated in their characteristic impedance; 75Ω is typical for video applications. Since the drivers usually are terminated in their characteristic impedance the input gain is 0.5, thus the amplifiers, U2, are configured in a gain of +2 to set the circuit gain equal to one. Resistors R2 and R3 determine the amplifier gain, and if a different gain is desired R2 should be changed according to the equation G = (1 + R3/R2). R3 sets the frequency response of the amplifier so you should refer to the manufacturers data sheet before changing its value. R5, C1 and D1 are an asymmetrical charge/discharge time circuit which configures U1 as a break before make switch to prevent both amplifiers from being active simultaneously. If this design is extended to more channels the drive logic must be designed to be break before make. R4 is enclosed in the feedback loop of the amplifier so that the large open loop amplifier gain of U2 will present the load with a small closed loop output impedance while keeping the amplifier stable for all values of load capacitance. Two Channel Video Multiplexer Referring to the amplifier U1A in Figure 8, R1 terminates the cable in its characteristic impedance of 75Ω, and R4 back terminates the cable in its characteristic impedance. The amplifier is set up in a gain configuration of +2 to yield an overall network gain of +1 when driving a double terminated cable. The value of R3 can be changed if a different network gain is desired. R5 holds the disable pin at ground thus inhibiting the amplifier until the switch, S1, is thrown to position 1. At position 1 the switch pulls the disable pin up to the plus supply rail thereby enabling the amplifier. Since all of the actual signal switching takes place within the amplifier, it’s differential gain and phase parameters, which are 0.03% and 0.03° respectively, determine the circuit’s performance. The other circuit, U1B, operates in a similar manner. When the plus supply rail is 5V the disable pin can be driven by a dedicated TTL gate as discussed earlier. If a multiplexer IC or its equivalent is used to select channels its logic must be break before make. When these conditions are satisfied the HA-5020 is often used as a remote video multiplexer, and the multiplexer may be extended by adding more amplifier ICs. The circuit shown in Figure 9 was tested for the full range of capacitor values with no oscillations being observed; thus, problem one has been solved. The frequency and gain characteristics of the circuit are now those of the amplifier and independent of any multiplexing action; thus, problem two has been solved. The multiplexer transition time is approximately 15µs with the component values shown. Low Impedance Multiplexer Two common problems surface when you try to multiplex multiple high speed signals into a low impedance source VIDEO INPUT #1 U1A + R4 75 R1 75 +5V IN VIDEO OUTPUT TO 75Ω LOAD - 0.1µF R3 681 R2 681 1 U1B R9 75 R11 100 3 ALL OFF R6 75 R8 681 10µF R5 2000 2 VIDEO INPUT #2 +5V + R7 681 R10 2000 -5V IN +5V S1 -5V 10µF 0.1µF NOTES: + 21. U1 is HA-5020. 22. All resistors in Ω. 23. S1 is break before make. 24. Use ground plane. FIGURE 8. TWO CHANNEL HIGH IMPEDANCE MULTIPLEXER 11 FN2845.11 June 5, 2006 HA-5020 R3A INPUT B R1A 75 R2A 681 U2A 681 R4A 27 - + INPUT A D1A 1N4148 R1B 75 -5V 0.01µF R5A R3B 681 U1C 2000 CHANNEL SWITCH R2B 681 U2B C1A 0.047µF OUTPUT +5V R5B U1A INHIBIT 27 0.01µF U1D U1B R4B - + 2000 R6 100K NOTES: C1B 0.047µF 25. U2: HA-5020. 26. U1: CD4011. D1B 1N4148 FIGURE 8. LOW IMPEDANCE MULTIPLEXER Typical Performance Curves VSUPPLY = ±15V, AV = +1, RF = 1kΩ, RL = 400Ω, TA = 25°C, unless otherwise specified 100 100 2.5 10 10 INPUT NOISE VOLTAGE OFFSET VOLTAGE (mV) -INPUT NOISE CURRENT INPUT NOISE CURRENT (pA/√Hz) INPUT NOISE VOLTAGE (nV/√Hz) AV = +10 2.0 VSUPPLY = ±15V 1.5 1.0 VSUPPLY = ±4.5V 0.5 VSUPPLY = ±10V +INPUT NOISE CURRENT 1 10 100 1k 1 100k 10k 0.0 -60 -40 -20 0 FREQUENCY (Hz) 0 2.0 -0.5 1.8 VSUPPLY = ±15V VSUPPLY = ±10V -1.5 VSUPPLY = ±4.5V -2.0 -2.5 -60 -40 -20 0 20 40 60 80 TEMPERATURE (°C) 60 80 100 120 140 VSUPPLY = ±15V 1.6 VSUPPLY = ±10V 1.4 1.2 100 120 FIGURE 11. +INPUT BIAS CURRENT vs TEMPERATURE (AVERAGE OF 30 UNITS FROM 3 LOTS) 12 40 FIGURE 10. INPUT OFFSET VOLTAGE vs TEMPERATURE (ABSOLUTE VALUE AVERAGE OF 30 UNITS FROM 3 LOTS) BIAS CURRENT (µA) BIAS CURRENT (µA) FIGURE 9. INPUT NOISE vs FREQUENCY (AVERAGE OF 18 UNITS FROM 3 LOTS) -1.0 20 TEMPERATURE (°C) 140 1.0 -60 VSUPPLY = ±4.5V -40 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 140 FIGURE 12. -INPUT BIAS CURRENT vs TEMPERATURE (ABSOLUTE VALUE AVERAGE OF 30 UNITS FROM 3 LOTS) FN2845.11 June 5, 2006 HA-5020 Typical Performance Curves VSUPPLY = ±15V, AV = +1, RF = 1kΩ, RL = 400Ω, TA = 25°C, unless otherwise specified (Continued) 8 6 125°C VSUPPLY = ±15V SUPPLY CURRENT (mA) OPEN LOOP GAIN (MΩ) 5 VSUPPLY = ±10V 4 VSUPPLY = ±4.5V 3 2 7 25°C -55°C 6 5 4 1 -60 -40 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 140 FIGURE 13. TRANSIMPEDANCE vs TEMPERATURE (AVERAGE OF 30 UNITS FROM 3 LOTS) 3 5 7 9 11 SUPPLY VOLTAGE (±V) 13 15 FIGURE 14. SUPPLY CURRENT vs SUPPLY VOLTAGE (AVERAGE OF 30 UNITS FROM 3 LOTS) 7 9 DISABLE = 0V 5 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 8 -55°C 6 25°C 4 125°C 3 2 1 VSUPPLY = ±10V VSUPPLY = ±15V 6 5 4 3 2 1 0 0 5 3 7 9 11 SUPPLY VOLTAGE (±V) 13 1 15 5 7 9 11 13 15 FIGURE 16. SUPPLY CURRENT vs DISABLE INPUT VOLTAGE 0 1.0 -20 OUTPUT LEAKAGE CURRENT (µA) DISABLE = 0V VIN = 5VP-P RF = 750Ω -10 -30 -40 -50 -60 -70 -80 3 DISABLE INPUT VOLTAGE (V) FIGURE 15. DISABLE SUPPLY CURRENT vs SUPPLY VOLTAGE (AVERAGE OF 30 UNITS FROM 3 LOTS) FEEDTHROUGH (dB) VSUPPLY = ±4.5V 7 0 2M 4M 6M 8M 10M 12M 14M 16M 18M 20M FREQUENCY (Hz) FIGURE 17. DISABLE MODE FEEDTHROUGH vs FREQUENCY 13 0.5 VOUT = +10V 0 VOUT = -10V -0.5 -1.0 -60 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) FIGURE 18. DISABLED OUTPUT LEAKAGE vs TEMPERATURE (AVERAGE OF 30 UNITS FROM 3 LOTS) FN2845.11 June 5, 2006 HA-5020 VSUPPLY = ±15V, AV = +1, RF = 1kΩ, RL = 400Ω, TA = 25°C, unless otherwise specified (Continued) 20 3 1.8 18 2 VOUT = 0.2VP-P 1.6 16 1 CL = 10pF 1.4 14 1.2 12 1.0 10 ENABLE TIME 0.8 8 0.6 6 0.4 4 DISABLE TIME 0.2 0.0 -10 -8 -6 -4 -2 0 2 4 6 8 NORMALIZED GAIN (dB) 2.0 DISABLE TIME (µs) ENABLE TIME (µs) Typical Performance Curves 0 -2 AV = +2 -3 -4 -5 2 -6 0 -7 10 AV = +1 -1 AV = +6 AV = +10 0 24M 48M OUTPUT VOLTAGE (V) 72M 96M 120M FREQUENCY (Hz) FIGURE 19. ENABLE/DISABLE TIME vs OUTPUT VOLTAGE (AVERAGE OF 9 UNITS FROM 3 LOTS) FIGURE 20. NON-INVERTING GAIN vs FREQUENCY 0 CL = 10pF RF = 750Ω -1 +180 AV = -1 -2 -3 AV = -2 -4 -5 -6 AV = -6 AV = -10 0 96M -45 -180 120M -135 AV = +6 -180 AV = +10 0 24M 48M 72M 96M 120M FREQUENCY (Hz) FIGURE 21. INVERTING FREQUENCY RESPONSE 110 FIGURE 22. PHASE vs FREQUENCY 105 5 20 CL = 10pF -3dB BANDWIDTH VOUT = 0.2VP-P 4 90 3 GAIN PEAKING 80 2 70 1 -3dB BANDWIDTH (MHz) 100 GAIN PEAKING (dB) -3dB BANDWIDTH (MHz) -90 AV = +2 FREQUENCY (Hz) CL = 10pF VOUT = 0.2VP-P 0 AV = +1 -135 -225 72M +45 AV = -10 -90 -270 48M +90 AV = -6 -45 -7 24M AV = -2 +45 -8 0 +135 AV = -1 INVERTING PHASE (°) VOUT = 0.2VP-P 100 15 -3dB BANDWIDTH 95 10 90 5 GAIN PEAKING (dB) 1 NON-INVERTING PHASE (°) NORMALIZED GAIN (dB) 2 GAIN PEAKING 60 0 200 400 600 LOAD RESISTANCE (Ω) 800 0 1000 FIGURE 23. BANDWIDTH AND GAIN PEAKING vs LOAD RESISTANCE 14 85 700 900 1.1k 1.3k 0 1.5k FEEDBACK RESISTOR (Ω) FIGURE 24. BANDWIDTH AND GAIN PEAKING vs FEEDBACK RESISTANCE FN2845.11 June 5, 2006 HA-5020 Typical Performance Curves VSUPPLY = ±15V, AV = +1, RF = 1kΩ, RL = 400Ω, TA = 25°C, unless otherwise specified (Continued) 80 20 100 CL = 10pF, AV = +2 -3dB BANDWIDTH 10 90 5 85 -3dB BANDWIDTH (MHz) 15 GAIN PEAKING (dB) -3dB BANDWIDTH (MHz) VOUT = 0.2VP-P 95 GAIN PEAKING 80 400 GAIN PEAKING = 0dB 50 40 30 10 200 0 1.2k 600 800 1.0k FEEDBACK RESISTOR (Ω) 60 20 400 600 800 1000 FEEDBACK RESISTOR (Ω) FIGURE 25. BANDWIDTH AND GAIN PEAKING vs FEEDBACK RESISTANCE FIGURE 26. BANDWIDTH vs FEEDBACK RESISTANCE 75 0 -10 70 REJECTION RATIO (dB) REJECTION RATIO (dB) CL = 10pF, AV = +10 VOUT = 0.2VP-P 70 PSRR 65 60 CMRR AV = +10 -20 -30 -40 -50 CMRR -60 +PSRR -70 -PSRR -80 55 -60 -40 -20 0 20 40 60 80 100 120 -90 10k 140 TEMPERATURE (°C) FIGURE 27. REJECTION RATIOS vs TEMPERATURE (AVERAGE OF 30 UNITS FROM 3 LOTS) 3.0 VSUPPLY = ±10V 2.5 2.0 VSUPPLY = ±4.5V 1.5 -60 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) FIGURE 29. OUTPUT SWING OVERHEAD vs TEMPERATURE (AVERAGE OF 30 UNITS FROM 3 LOTS) 15 10M 30 (±VSUPPLY) - (±VOUT ) VSUPPLY = ±15V 1M FREQUENCY (Hz) FIGURE 28. REJECTION RATIOS vs FREQUENCY OUTPUT VOLTAGE SWING (VP-P) OUTPUT SWING OVERHEAD (±V) 3.5 100k VSUPPLY = ±15V 25 20 VSUPPLY = ±10V 15 10 VSUPPLY = ±4.5V 5 0 10 100 1k LOAD RESISTANCE (Ω) 10k FIGURE 30. OUTPUT VOLTAGE SWING vs LOAD RESISTANCE FN2845.11 June 5, 2006 HA-5020 Typical Performance Curves VSUPPLY = ±15V, AV = +1, RF = 1kΩ, RL = 400Ω, TA = 25°C, unless otherwise specified (Continued) 7.0 90 PROPAGATION DELAY (ns) SHORT CIRCUIT CURRENT (mA) 100 80 -ISC 70 +ISC 60 6.5 RLOAD = 100Ω VOUT = 1VP-P 6.0 5.5 50 40 -60 -40 -20 0 20 40 60 80 100 120 5.0 -60 140 -40 -20 TEMPERATURE (°C) 40 60 80 100 140 120 FIGURE 32. PROPAGATION DELAY vs TEMPERATURE (AVERAGE OF 18 UNITS FROM 3 LOTS) 15 11.0 VOUT = 100mVP-P , CL = 10pF AV = +10 (RF = 383Ω) 10.0 VSUPPLY = ±5V OVERSHOOT (%) PROPAGATION DELAY (ns) 20 TEMPERATURE (°C) FIGURE 31. SHORT CIRCUIT CURRENT LIMIT vs TEMPERATURE 9.0 8.0 AV = +2 7.0 6.0 AV = +2 10 AV = +1 VSUPPLY = ±15V 5 AV = +1 AV = +1 RLOAD = 100Ω VOUT = 1VP-P AV = +2 0 5.0 3 5 7 9 11 13 200 0 15 SUPPLY VOLTAGE (±V) 400 600 800 1000 LOAD RESISTANCE (Ω) FIGURE 33. PROPAGATION DELAY vs SUPPLY VOLTAGE (AVERAGE OF 18 UNITS FROM 3 LOTS) FIGURE 34. SMALL SIGNAL OVERSHOOT vs LOAD RESISTANCE 0.07 -50 FREQUENCY = 3.58MHz VO = 2VP-P CL = 30pF 0.06 DIFFERENTIAL GAIN (%) 3RD ORDER IMD -60 DISTORTION (dBc) 0 HD2 (GEN) -70 3RD ORDER IMD (GENERATOR) -80 HD3 HD2 -90 0.05 RLOAD = 75Ω 0.04 0.03 RLOAD = 150Ω 0.02 HD3 (GEN) 1M FREQUENCY (Hz) FIGURE 35. DISTORTION vs FREQUENCY 16 10M 0.01 RLOAD = 1K 3 5 7 9 11 13 15 SUPPLY VOLTAGE (±V) FIGURE 36. DIFFERENTIAL GAIN vs SUPPLY VOLTAGE (AVERAGE OF 18 UNITS FROM 3 LOTS) FN2845.11 June 5, 2006 HA-5020 Typical Performance Curves 0.07 VSUPPLY = ±15V, AV = +1, RF = 1kΩ, RL = 400Ω, TA = 25°C, unless otherwise specified (Continued) 1200 FREQUENCY = 3.58MHz VOUT = 20VP-P SLEW RATE (V/µs) RLOAD = 75Ω 0.05 0.04 RLOAD = 150Ω 0.03 RLOAD = 1K 3 5 7 9 11 SUPPLY VOLTAGE (±V) 13 -SLEW RATE 800 600 -60 15 Typical Performance Curves -20 0 20 40 60 80 100 120 140 FIGURE 38. SLEW RATE vs TEMPERATURE (AVERAGE OF 30 UNITS FROM 3 LOTS) VSUPPLY = ±5V, AV = +1, RF = 1kΩ, RL = 400Ω, TA = 25°C, Unless Otherwise Specified 5 5 4 4 AV + 2 NORMALIZED GAIN (dB) 3 2 1 0 AV + 1 -1 AV + 10 -2 -3 3 2 AV = -1 1 0 AV = -2 -1 -2 -3 -4 -5 -40 TEMPERATURE (°C) FIGURE 37. DIFFERENTIAL PHASE vs SUPPLY VOLTAGE (AVERAGE OF 18 UNITS FROM 3 LOTS) NORMALIZED GAIN (dB) +SLEW RATE 0.02 0.01 AV = -10 -4 2M 10M FREQUENCY (Hz) 100M -5 200M 2M 5 AV + 1 3 AV - 1 2 180 135 90 AV + 10 1 45 AV - 10 0 0 -1 -45 -2 -90 -3 -135 -4 -180 -5 2M 10M FREQUENCY (Hz) 100M FIGURE 41. PHASE RESPONSE AS A FUNCTION OF FREQUENCY 17 200M INVERTING PHASE (°) 4 10M FREQUENCY (Hz) 100M 200M FIGURE 40. INVERTING FREQUENCY RESPONSE -3dB BANDWIDTH (MHz) FIGURE 39. NON-INVERTING FREQUENCY RESPONSE NON-INVERTING PHASE (°) 1000 140 VOUT = 0.2VP-P CL = 10pF AV = +1 130 -3dB BANDWIDTH 120 10 5 GAIN PEAKING 500 700 900 1100 1300 0 1500 GAIN PEAKING (dB) DIFFERENTIAL PHASE (°) 0.06 FEEDBACK RESISTOR (Ω) FIGURE 42. BANDWIDTH AND GAIN PEAKING vs FEEDBACK RESISTANCE FN2845.11 June 5, 2006 HA-5020 130 95 -3dB BANDWIDTH 90 10 5 GAIN PEAKING 350 500 650 800 0 1100 950 -3dB BANDWIDTH (MHz) VOUT = 0.2VP-P CL = 10pF AV = +2 120 -3dB BANDWIDTH 110 6 100 4 90 80 0 200 400 FEEDBACK RESISTOR (Ω) 600 2 0 1000 800 LOAD RESISTOR (Ω) FIGURE 43. BANDWIDTH AND GAIN PEAKING vs FEEDBACK RESISTANCE FIGURE 44. BANDWIDTH AND GAIN PEAKING vs LOAD RESISTANCE 80 VOUT = 0.2VP-P CL = 10pF AV = +10 60 40 20 AV = +1 0 -10 REJECTION RATIO (dB) -3dB BANDWIDTH (MHz) VOUT = 0.2VP-P CL = 10pF AV = +1 GAIN PEAKING GAIN PEAKING (dB) 100 VSUPPLY = ±5V, AV = +1, RF = 1kΩ, RL = 400Ω, TA = 25°C, Unless Otherwise Specified (Continued) GAIN PEAKING (dB) -3dB BANDWIDTH (MHz) Typical Performance Curves -20 -30 -40 CMRR -50 -60 NEGATIVE PSRR -70 -80 POSITIVE PSRR 0 200 350 500 650 FEEDBACK RESISTOR (Ω) 800 950 0.001M FIGURE 45. BANDWIDTH vs FEEDBACK RESISTANCE 0.1M 1M FREQUENCY (Hz) 10M 30M FIGURE 46. REJECTION RATIOS vs FREQUENCY 500 RL = 100Ω VOUT = 1.0VP-P AV = +1 VOUT = 2VP-P 450 + SLEW RATE 400 7.5 SLEW RATE (V/µs) PROPAGATION DELAY (ns) 8.0 0.01M 7.0 350 - SLEW RATE 300 250 200 6.5 150 100 6.0 -50 -25 0 25 50 75 100 125 TEMPERATURE (°C) FIGURE 47. PROPAGATION DELAY vs TEMPERATURE 18 -50 -25 0 25 50 75 100 125 TEMPERATURE (°C) FIGURE 48. SLEW RATE vs TEMPERATURE FN2845.11 June 5, 2006 HA-5020 Typical Performance Curves VSUPPLY = ±5V, AV = +1, RF = 1kΩ, RL = 400Ω, TA = 25°C, Unless Otherwise Specified (Continued) 0.8 0.8 VOUT = 0.2VP-P CL = 10pF 0.2 0 AV = +2, RF = 681Ω -0.2 -0.4 AV = +5, RF = 1kΩ -0.6 AV = +1, RF = 1kΩ 0.4 0.2 -0.2 -0.4 -0.6 15M AV = -2 -1.2 -1.2 10M AV = -10 -1.0 AV = 10, RF = 383Ω 5M AV = -5 -0.8 -0.8 -1.0 AV = -1 0 20M 25M 5M 30M 10M 15M FREQUENCY (Hz) FIGURE 49. NON-INVERTING GAIN FLATNESS vs FREQUENCY 100 600 60 +INPUT NOISE CURRENT 400 40 +INPUT NOISE VOLTAGE 200 REJECTION RATIO (dB) 800 CURRENT NOISE (pA/√Hz) VOLTAGE NOISE (nV/√Hz) +PSRR 72 -INPUT NOISE CURRENT 70 68 -PSRR 66 64 62 CMRR 60 0 0.01k 0.1k 1k 58 -100 0 100k 10k -50 0 50 100 150 200 FIGURE 51. INPUT NOISE CHARACTERISTICS FIGURE 52. REJECTION RATIO vs TEMPERATURE 4.0 32 20 30 18 ENABLE ENABLE TIME (ns) OUTPUT SWING (V) 28 3.8 16 26 14 ENABLE 24 12 22 10 20 8 18 6 DISABLE 16 4 14 3.6 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 53. OUTPUT SWING vs TEMPERATURE 19 250 TEMPERATURE (°C) FREQUENCY (Hz) -60 30M 74 1000 20 25M FIGURE 50. INVERTING GAIN FLATNESS vs FREQUENCY AV = 10, RF = 383Ω 80 20M FREQUENCY (Hz) 140 DISABLE TIME (µs) 0.4 VOUT = 0.2VP-P CL = 10pF RF = 750Ω 0.6 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 0.6 2 DISABLE 12 -2.5 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 0 2.5 OUTPUT VOLTAGE (V) FIGURE 54. ENABLE/DISABLE TIME vs OUTPUT VOLTAGE FN2845.11 June 5, 2006 HA-5020 -20 -30 -40 -50 10 RL = 100Ω 1 0.1 0.01 180 0.001 135 90 45 -60 0 -70 -45 -80 1M FREQUENCY (Hz) 10M 20M 0.001M FIGURE 55. DISABLE FEEDTHROUGH vs FREQUENCY 0.01M 0.1M 1M FREQUENCY (Hz) 10M -135 100M FIGURE 56. TRANSIMPEDANCE vs FREQUENCY 10 RL = 400Ω 1 0.1 0.01 180 0.001 135 90 45 0 -45 PHASE ANGLE (°) 0.1M -90 TRANSIMPEDANCE (MΩ) FEEDTHROUGH (dB) -10 DISABLE = 0V VIN = 5VP-P RF = 750Ω TRANSIMPEDANCE (MΩ) 0 VSUPPLY = ±5V, AV = +1, RF = 1kΩ, RL = 400Ω, TA = 25°C, Unless Otherwise Specified (Continued) PHASE ANGLE (°) Typical Performance Curves -90 -135 0.001M 0.01M 0.1M 1M 10M 100M FREQUENCY (Hz) FIGURE 57. TRANSIMPEDENCE vs FREQUENCY 20 FN2845.11 June 5, 2006 HA-5020 Die Characteristics DIE DIMENSIONS: PASSIVATION: 1640µm x 1520µm x 483µm Type: Nitride over Silox Silox Thickness: 12kÅ ±2kÅ Nitride Thickness: 3.5kÅ ±1kÅ METALLIZATION: Type: Aluminum, 1% Copper Thickness: 16kÅ ±2kÅ TRANSISTOR COUNT: 62 SUBSTRATE POTENTIAL (Powered Up): PROCESS: V- High Frequency Bipolar Dielectric Isolation Metallization Mask Layout HA-5020 IN- 2 BAL DISABLE V+ 1 8 7 6 IN+ 3 21 4 5 V- BAL OUT FN2845.11 June 5, 2006 HA-5020 Dual-In-Line Plastic Packages (PDIP) E8.3 (JEDEC MS-001-BA ISSUE D) N 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AD E BASE PLANE -C- A2 SEATING PLANE A L D1 e B1 D1 A1 eC B 0.010 (0.25) M C A B S MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8, 10 eA C 0.008 0.014 0.204 C D 0.355 0.400 9.01 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. e 0.100 BSC 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eA 0.300 BSC 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. eB - L 0.115 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . N 8 0.355 10.16 5 2.54 BSC - 7.62 BSC 6 0.430 - 0.150 2.93 10.92 3.81 8 7 4 9 Rev. 0 12/93 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 22 FN2845.11 June 5, 2006 HA-5020 Small Outline Plastic Packages (SOIC) M8.15 (JEDEC MS-012-AA ISSUE C) N 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA H 0.25(0.010) M B M INCHES E SYMBOL -B1 2 3 L SEATING PLANE -A- A D h x 45° -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M MIN MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 e α B S 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 N α NOTES: MILLIMETERS 8 0° 1.27 8 8° 0° 6 7 8° 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. Rev. 1 6/05 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 23 FN2845.11 June 5, 2006