Datasheet

UNISONIC TECHNOLOGIES CO., LTD
UB264A
Preliminary
CMOS IC
LION BATTERY PROTECTION
IC FOR 2-SERIAL, 3-SERIAL,
OR 4-SERIAL-CELL PACK
(SECONDARY PROTECTION)
„
DESCRIPTION
The UTC UB264A Series is secondary protection IC for 2-, 3-, or
4-Cell lithium-ion rechargeable battery packs, and incorporates a
high-accuracy voltage detection circuit.
The UTC UB264A Series also includes a high accuracy delay
circuit for over voltage detection time without external capacitors.
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FEATURES
High-accuracy voltage detection circuit for each cell
Overcharge detection voltage n (n=1 to 4): 4.30V to 4.80V (in
50mV steps)
Overcharge hysteresis voltage n (n=1 to 4): -0.52V±0.21V,
−0.39V±0.16V, −0.26V±0.11V, −0.13V±0.06V, None
Delay times for overcharge detection can be set by an internal
circuit without external capacitors
Output control function via CTL pin
CMOS output active “H”
Wide operating voltage range 3.6V to 24V
Wide operating temperature range −40°C ~ +85°C
Low current consumption: 2.5μA typ. (+25°C) at 3.5V for each
cell
ORDERING INFORMATION
Note:
Ordering Number
Lead Free
Halogen Free
UB264AL-P08-R
UB264AG-P08-R
xx: SERIAL CODE, refer SERIAL CODE LIST.
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Copyright © 2012 Unisonic Technologies Co., Ltd
Package
Packing
TSSOP-8
Tape Reel
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UB264A
Preliminary
„
PIN CONFIGURATION
„
PIN DESCRIPTION
PIN NO.
1
2
3
4
5
6
7
8
„
CMOS IC
PIN NAME
DESCRIPTION
VDD
Positive power input pin
SENSE
Positive voltage connection pin of battery 1
Negative voltage connection pin of battery 1
VC1
Positive voltage connection pin of battery 2
Negative voltage connection pin of battery 2
VC2
Positive voltage connection pin of battery 3
Negative voltage connection pin of battery 3
VC3
Positive voltage connection pin of battery 4
Negative power input pin
VSS
Negative voltage connection pin of battery 4
CTL
CO output control pin
CO
FET gate connection pin for charge
SERIAL CODE LIST
MODEL
CODE
OVERCHARGE
DETECTION
VOLTAGE
[VCU](V)
OVERCHARGE
HYSTERSIS
VOLTAGE
[VHC](V)
OVERCHARGE
DETECTION
DELAY TIME
[tCU](S)
OVERCHARGE
RELEASE
DELAY TIME
[tCL](mS)
AA
4.45±0.050
-0.39±0.16
4.0±1.0
60.0±20.0
AB
4.35±0.050
-0.39±0.16
4.0±1.0
60.0±20.0
AC
4.50±0.050
-0.39±0.16
4.0±1.0
60.0±20.0
AD
4.35±0.050
-0.39±0.16
2.0±0.5
30.0±10.0
AE
4.30±0.050
-0.39±0.16
4.0±1.0
60.0±20.0
AF
4.45±0.050
-0.39±0.16
2.0±0.5
30.0±10.0
AG
4.30±0.050
-0.39±0.16
2.0±0.5
30.0±10.0
AH
4.40±0.050
-0.39±0.16
4.0±1.0
60.0±20.0
UB264A
UNISONIC TECHNOLOGIES CO., LTD
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OUTPUT
FORM
CMOS output
active “H”
CMOS output
active “H”
CMOS output
active “H”
CMOS output
active “H”
CMOS output
active “H”
CMOS output
active “H”
CMOS output
active “H”
CMOS output
active “H”
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Preliminary
CMOS IC
BLOCK DIAGRAM
SENSE
VC1
Overcharge
Detector 1
VC2
Overcharge
Detector 2
Oscillator
VDD
Divider
CO
Control
Logic
CTL
Overcharge
Detector 3
VC3
Overcharge
Detector 4
VSS
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Preliminary
CMOS IC
ABSOLUTE MAXIMUM RATING (TA=25°C, unless otherwise specified)
PARAMETER
SYMBOL
RATINGS
UNIT
Input Voltage Between VDD And VSS
VDS
VSS −0.3 ~ VSS+26
V
Input Pin Voltage
VIN
VSS −0.3 ~ VDD+0.3
V
CO Output Pin Voltage
VCO
VSS −0.3 ~ VDD+0.3
V
Power Dissipation (Note 2)
PD
650
mW
Operation Ambient Temperature
TOPR
−40 ~ +85
°C
Storage Temperature
TSTG
−40 ~ +125
°C
Notes: 1. Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
2. When mounted on printed circuit board.
„
ELECTRICAL CHARACTERISTICS (TA=25°C, unless otherwise specified)
PARAMETER
DETECTION VOLTAGE
Overcharge Detection
Voltage n (n=1, 2, 3, 4)
Overcharge Hysteresis
Voltage n (n=1, 2, 3, 4)
DELAY TIME
Overcharge Detection Delay
Time
SYMBOL
VCUn
4.30 ~ 4.80 V, adjustable
VHCn
VHCn=−0.52±0.21V, −0.39±0.16V,
−0.26 ±0.11V, −0.13 ±0.06V, None
tCU
Overcharge Release Delay
Time
tCL
Overcharge Timer Reset
Delay Time
tTR
Transition Time To Test
Mode (Note 1)
CTL Pin Response Time
INPUT VOLTAGE
Operating Voltage Between
VDD And VSS
TEST CONDITIONS
tTST
For AD, AF and AG products
For AD, AF and AG products
For AD, AF and AG products
For AD, AF and AG products
MIN
TYP
MAX
UNIT
VCUn−
0.050
VCUn
VCUn+
0.050
V
VHCn
3.0
1.5
40
20
10
5
40
20
4.0
2.0
60
30
15
7.5
60
30
tCTL
VDSOP
3.6
CTL Input “H” Voltage
VCTLH
VDD×
0.95
CTL Input “L” Voltage
VCTLL
INPUT CURRENT
Current Consumption During
IOPE
V1=V2=V3=V4=3.5V
Operation
Current Consumption During
IOPED V1=V2=V3=V4=2.3V
Overdischarge
SENSE Pin Current
ISENSE V1=V2=V3=V4=3.5V
VC1 Pin Current
IVC1
V1=V2=V3=V4=3.5V
VC2 Pin Current
IVC2
V1=V2=V3=V4=3.5V
VC3 Pin Current
IVC3
V1=V2=V3=V4=3.5 V
CTL Pin “H” Current
ICTLH
V1=V2=V3=V4=3.5 V, VCTL=VDD
CTL Pin “L” Current
ICTLL
V1=V2=V3=V4=3.5 V, VCTL=0 V
OUTPUT CURRENT
CO Pin Sink Current
ICOL
VCOP=VSS+0.5V
CO Pin Source Current
ICOH
VCOP=VDD−0.5V
Note: 1. Test conditions: V1=V2=V3=V4=3.5V, VDD ≥ VSENSE+8.5V.
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-0.5
-0.5
-0.5
1.0
-0.1
0.4
20
V
5.0
2.5
80
40
20
10
80
40
3.0
24
s
ms
ms
ms
ms
V
V
VDD×
0.4
V
2.5
10
μA
2.0
10
μA
1.5
0
0
0
1.5
6.0
0.5
0.5
0.5
2.0
μA
μA
μA
μA
μA
μA
mA
μA
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Preliminary
CMOS IC
OPERATING
1. Overcharge Detection
Under normal conditions, when the voltage of any one cell battery exceeds the overcharge detection voltage (VCU)
during charging, and after the state is retained for the overcharge detection delay time (tCU), CO will become “H”.
This state is called overcharge. Attaching FET to the CO pin provides charge control and a second protection.
Only the voltages of all the batteries decreases below the total of the overcharge detection voltage (VCU) and the
overcharge hysteresis voltage (VHC), and the state is retained for the overcharge release delay time (tCL) or longer,
CO will become “L”.
2. Overcharge Timer Reset
When an overcharge release noise that forces the voltage of the battery temporarily below the overcharge
detection voltage (VCU) is input during the overcharge detection delay time (tCU) from when VCU is exceeded to when
charging is stopped, tCU is continuously counted if the time the overcharge release noise persists is shorter than the
overcharge timer reset delay time (tTR). Under the same conditions, if the time the overcharge release noise persists
is tTR or longer, counting of tCU is reset once. After that, when VCU has been exceeded, counting tCU resumes.
3. CTL Pin
The CTL pin is used to control the output voltage of the CO pin. In the UTC UB264A Series, the CTL pin takes
precedence over the overcharge detection circuit.
Note:
Notes:
1.
2.
CTL PIN
CO PIN
“H”
Normal state (Note 1)
Open
“H”
“L”
“H”
“L”→ “H”
“H” →“L”
1. The state is controlled by the overcharge detection circuit.
The reverse voltage “H” to “L” or “L” to “H” of CTL pin is VDD pin voltage −2.8V (Typ.), does not have
the hysteresis.
Since the CTL pin implements high resistance of 8MΩ to 12MΩ for pull down, be careful of external
noise application. If an external noise is applied, CO may become “H”. Perform thorough evaluation
using the actual application.
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„
Preliminary
CMOS IC
OPERATING(Cont.)
4. Test Mode
In the UTC UB264A Series, the overcharge detection delay time (tCU) can be shortened by entering the test mode.
The test mode can be set by retaining the VDD pin voltage 8.5 V or more higher than the SENSE pin voltage for at
least 80ms (V1=V2=V3=V4=3.5V, Ta=25°C). The status is retained by the internal latch and the test mode is
retained even if the VDD pin voltage is decreased to the same voltage as that of the SENSE pin. When CO becomes
“H” when the delay time has elapsed after overcharge detection, the latch for retaining the test mode is reset and the
UTC UB264A Series exits from the test mode.
VDD pin voltage SENSE pin voltage
>8.5V
Pin voltage
VCUn
VHCn
Battery voltage
(n=1 to 4)
Test mode
tTST
CO Pin
tCU/64
Notes:
1.
2.
3.
4.
tCL
When the VDD pin voltage is decreased to lower than the UVLO voltage of 2 V (Typ.), the UTC
UB264A Series returns to the normal mode.
Set the test mode when no batteries are overcharged.
The overcharge release delay time (tCL) is not shortened in the test mode.
The overcharge timer reset delay time (tTR) is not shortened in the test mode.
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„
Preliminary
CMOS IC
TIMING CHARTS
1. Overcharge Detection Operation
VHCn
VCUn
Battery voltage
(n=1 to 4)
CTL Pin
tTR or
longer
CO Pin
tTR or shorter
tCU or shorter
tCU
tCL
2. Overcharge Timer Reset Operation
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Preliminary
CMOS IC
TYPICAL APPLICATION CIRCUIT
(1) 4-serial cell
SC Protector
RVDD
EB+
VDD
CVDD
SENSE
BAT1
BAT2
BAT3
R1
R2
R3
C1
VC1
C2
UTC
UB264A
VC2 Series
VC3
BAT4
R4
FET
C3
CO
DP
C4
VSS
CTL
External
input
RCTL
EB-
(2) 3-serial cell
SC Protector
RVDD
EB+
VDD
CVDD
SENSE
BAT1
BAT2
BAT3
R1
R2
R3
C1
VC1
C2
UTC
UB264A
VC2 Series
FET
C3
VC3
CO
DP
VSS
CTL
External
input
RCTL
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EB-
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Preliminary
CMOS IC
(3) 2-serial cell
SC Protector
RVDD
EB+
VDD
CVDD
SENSE
BAT1
BAT2
R1
R2
C1
VC1
C2
UTC
UB264A
VC2 Series
VC3
FET
CO
DP
VSS
CTL
External
input
RCTL
EB-
Constants for External Components
NO.
1
2
3
4
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
PART
R1 to R4
C1 to C4, CVDD
RVDD
RCTL
MIN
0.1
0.01
50
0
TYP
1
0.1
100
100
MAX
10
1
500
500
UNIT
kΩ
μF
Ω
Ω
the examples of connection shown above and the constants will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
Set the same constants to R1 to R4 and to C1 to C4 and CVDD.
Set RVDD, C1 to C4 and CVDD so that the condition (RVDD) × (C1 to C4, CVDD) ≥ 5 × 10−6 is satisfied.
T Set R1 to R4, C1 to C4, and CVDD so that the condition (R1 to R4) × (C1 to C4, CVDD) ≥ 1 × 10−4 is
satisfied.
In some application circuits, even if an overcharged battery is not included, the order of connecting
batteries may be restricted to prevent transient output of CO detection pulses when the batteries are
connected. Perform thorough evaluation with the actual application circuit.
Since “H” may be output at CO transiently when the battery is being connected, connect the positive
terminal of BAT1 last in order to prevent the three terminal protection fuse from cutoff.
Before the battery connection, short-circuit the battery side pins RVDD and R1.
In the UTC UB264A Series, normally input “H” to the external input, and input “L” when setting CO to
“H”.
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Preliminary
CMOS IC
TYPICAL APPLICATION CIRCUIT(Cont.)
(4) 4-serial cell (Overheat Protection via PTC)
Notes:
1.
2.
3.
4.
The above connection example will not guarantee successful operation. Perform thorough evaluation
using the actual application.
A pull-down resistor is included in the CTL pin. To perform overheat protection via the PTC in the UTC
UB264A Series, connect the PTC before connecting batteries.
When the power fluctuation is large, connect the power supply of the PTC to the VDD pin of the UTC
UB264A Series.
Since “H” may be output at CO transiently when the battery is being connected, connect the positive
terminal of BAT1 last in order to prevent the three terminal protection fuse from cutoff.
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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