SP600 Semiconductor July 1998 WN ITHDRA TE W T R A P OLE SS OBS NS PROCE S DE IG NO NEW Features File Number 2428.4 Half Bridge 500VDC Driver • Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . 500V The SP600 is a smart power high voltage integrated circuit (HVIC) optimized to drive MOS gated power devices in halfbridge topologies. It provides the necessary control and management for PWM motor drive, power supply, and UPS applications. • Ability to Interface and Drive Standard and Current Sensing N-Channel Power MOSFET/IGBT Devices • Creation and Management of a Floating Power Supply for Upper Rail Drive • Simultaneous Conduction Lockout • Overcurrent Protection Ordering Information • Single Low Current Bias Supply Operation PART • Latch Immune CMOS Logic PACKAGE -40oC to +85oC SP600 • Peak Drive in Excess of 0.5A Pinout TEMPERATURE 22 Lead Plastic DIP Functional Block Diagram VBS SP600 (PDIP) TOP VIEW 12 D1U VBIAS 3 VDD 4 VSS 5 VBIAS 10Ω RND 21 BOT 3 VDD 20 NC 19 D1U 4 18 G1U VDF 19 G1U IONT LEVEL SHIFT S IOFFT 18 G2U Q R 17 3.5Ω RBS TRIPU UV LOCK OUT 11 UPPER ITRIPSEL 2 22 TOP + - TRIPL 6 17 G2U CL1 7 16 CL2 G2L 8 15 TRIPU 16 G1L 9 14 PHASE PHASE D1L 10 13 VOUT TOP VDF 11 12 VBS 22 15 CL2 S ITRIPSEL Q 14 3.5Ω RO R 13 VOUT D1L 10 IONB S BOT CMOS TIMING AND CONTROL 21 FAULT IOFFB VOUT SENSE AND FILTER FAULT 750Ω RF 1 Q R Q 9 G2L 8 UV LOCK OUT TRIPL + - S 6 CL1 R FILTER G1L LOWER FAULT 1 7 ITRIPSEL S Q R ITRIPSEL 2 1 VSS 5 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. Copyright © Harris Corporation 1998 SP600 Absolute Maximum Ratings Full Temperature Range, All Voltage Referenced to VSS Unless Otherwise Noted. Note 1, Note 2. Thermal Information Low Voltage Power Supply, VBIAS (Note 1) . . . . . . . . . . . . . . 18VDC Floating Low Voltage Boot Strap . . . . . . . . . . . . . . . . . . . . . . 18VDC Power Supply to Phase, VBS Low Voltage Signal Pins Fault, ITRIPSEL , VDD, TRIPL , CL1, G2L . . . -0.5VDC to VDD +0.5 G1L, D1L, VDF, TOP, BOT CL2, TRIPU , G1U, G2U, D1U to Phase. . . . -0.5VDC to VBS +0.5 High Voltage Pins Phase, VPHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500VDC (VBS , VOUT , TRIPU , CL2, G2U and D1U: 0V-18V Higher Than Phase) Dynamic High Voltage Rating Phase, . . . . . . . . . . . . . 10,000V/µs DVPHASE/DT Thermal Resistance θJA Plastic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . 75oC/W Maximum Package Power Dissipation at TA = +85oC, PO Plastic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mW Operating Ambient Temperature Range, TA . . . . . . .-25oC to +85oC Storage Temperature Range, TS . . . . . . . . . . . . . . .-40oC to +150oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +265oC NOTES: 1. Care must be taken in the application of VBIAS as not to impose high peak dissipation demands on a relatively small metallized noise dropping resistor (RND). Prolonged high peak currents may result if +15VDC is applied abruptly and/or if the local bypass capacitor CDD is large. It is suggested that CDD be ≤ 10MFD. If it is desirable to switch the 15VDC source or if a CDD is larger, additional series impedance may be required. 2. Consult factory for additional package offerings. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications (VBIAS = 15V, Pulsed <300ms), Unless Otherwise Noted, All Parameters Referenced to VSS Except TRIPU , CL2, G1U, D1U, and VBS Referenced to PHASE. DF: VDF to VBS , CF: VBS to PHASE PARAMETER SYMBOL TEMP MIN TYP MAX UNITS IIN +25oC - 20 30 µA -40oC to +85oC - 30 33 µA +25oC - 1.7 2.05 mA -40oC to +85oC - 1.7 2.1 mA +25oC - 1.7 2.05 mA -40oC to +85oC - 1.7 2.1 mA +25oC - 875 1000 µA -40oC to +85oC - 900 1060 µA DC CHARACTERISTICS Input Current (5V < VTOP , VBOT , VTRIPSEL < 15V) IBIAS Quiescent Current (All Inputs Low) IBIAS Quiescent Current (VOUT ≥ VBIAS, and All Inputs Low) IBS Quiescent Current Bootstrap Supply TOP Threshold Level IBIAS IBIAS L H IBS VTOP BOTTOM Threshold Level VBOT Current TRIPSELECT Threshold Level Trip Lower and Upper Comparator Threshold Level - Normal (ITRIPSEL = VSS) Trip Lower and Upper Comparator Threshold Level - Boost (ITRIPSEL = VDD) % of Measured VTRIP L/U VTRIPSEL VTRIP L/U N VTRIP L/U B +25oC 7 8 9 V -40oC to +85oC 6.95 8 9.1 V +25oC 7 8 9 V -40oC to +85oC 6.9 8 9.1 V +25oC 7 8 9 V -40oC to +85oC 6.95 8 9.1 V +25oC 90 105 125 mV -40oC to +85oC 90 105 127 mV +25oC 110 130 150 % -40oC to +85oC 109 130 152 % N Under Voltage Lockout Thresholds (VDD and VBS) Phase Out of Status Voltage Threshold (PHASE) 2 VLOCK VOSVT +25oC 9 10 11.5 V -40oC to +85oC 9.7 10.5 11.8 V +25oC 5 7 9 V -40oC to +85oC 4.7 7 9.6 V SP600 Electrical Specifications (VBIAS = 15V, Pulsed <300ms), Unless Otherwise Noted, All Parameters Referenced to VSS Except TRIPU , CL2, G1U, D1U, and VBS Referenced to PHASE. DF: VDF to VBS , CF: VBS to PHASE (Continued) PARAMETER SYMBOL TEMP RF +25oC 500 760 1000 Ω -40oC to +85oC 450 760 1100 Ω +25oC 12 17 23 Ω -40oC to +85oC 7 17 29 Ω Faultbar Impedance at IFBAR = 1mA Upper/Lower Source Impedances (ISOURCE = 10mA) Upper/Lower Sink Impedances (ISINK = 10mA) RSO L/U Noise Clamping Zeners; CL2 and CL1 (IZ = 50mA) UNITS 8 12 16 Ω 5 12 20 Ω +25oC 2 3.5 5 Ω -40oC to +85oC 5.6 Ω 1.4 3.5 +25oC 6 10 14 Ω -40oC to +85oC 5.4 10 14.6 Ω ILK +25oC - 1 3 µA VD1U/L +25oC 0.40 0.90 1.40 V VCL2/1-LOW +25oC 6.35 6.61 6.85 V -40oC to +85oC 6.15 6.61 7.15 V +25oC 7.0 8.5 8.0 V +25oC 2 3.5 5 Ω -40oC to +85oC 1.4 3.5 5.6 Ω RND High Voltage Leakage (500V VBS, VOUT, PHASE, TRIPU, CL2, G1U, G2U, and D1U to VSS. All other Pins at VSS) Noise Clamping Zeners; CL2 and CL1 (IZ = 10mA) MAX -40oC to +85oC RBS Noise Dropping Resistor Impedance Miller Clamp Diodes; D1U and D1L (ID = 10mA) TYP +25oC RSI L/U Bootstrap Supply Current Limiting Impedance MIN VCL2/1HIGH VOUT Limiting Resistance RO NOTE: Maximum Steady State ÷ 15VDC Supply Current = IBIAS Switching Specifications ÷ IBS (All Referenced to VSS , Except: TRIPU , Cl2, G1U, G2U, and D1U Referenced to PHASE. DF : VDF to VBS , CF : VBS to PHASE) PARAMETER Refresh One Shot Timer Delay Time of Trip I/U Voltage (ITRIPSEL low) to G2U/G2L Low (50% Overdrive) SYMBOL TEMP tREF +25oC 200 350 500 µs -40oC to +85oC 180 350 540 µs +25oC 2 3 4 µs -40oC to +85oC 1.85 3 4.35 µs tOFF TN Delay Time of Trip I Voltage (ITRIPSEL low) to Faultbar Low tFN Delay Time of Phase Out of Status to Faultbar Low (TOP High) tOSVF Minimum Logic Input Pulse Width: TOP and BOTTOM Minimum G1U/G1L On Time tMINIW tON Minimum Pulsed Off Time, G2U/G2L Turn On Delay Time of G1U (BISTATE MODE) 3 L tOFF tON D MIN TYP MAX UNITS +25oC 2 3 4 µs -40oC to +85oC 1.85 3 4.35 µs +25oC 500 700 900 ns -40oC to +85oC 400 700 1050 ns +25oC 300 430 600 ns -40oC to +85oC 275 430 660 ns +25oC 1.6 2.3 3.1 µs -40oC to +85oC µs 1.5 2.4 3.4 +25oC 1.3 2.0 3.4 µs -40oC to +85oC 1.05 2.1 3.9 µs +25oC 2.5 3.2 4.5 µs -40oC to +85oC 2.1 3.3 5.2 µs SP600 Switching Specifications (All Referenced to VSS , Except: TRIPU , Cl2, G1U, G2U, and D1U Referenced to PHASE. DF : VDF to VBS , CF : VBS to PHASE) (Continued) PARAMETER SYMBOL Turn On Delay Time of G1L (BISTATE MODE) tON D Turn On Delay Time of G1U (THREE-STATE MODE) tON Turn On Delay Time of G1L (THREE-STATE MODE) tON D D Turn Off Delay Time of G2U and G2L Minimum Dead Time: G1U off to G1L on, or G1L off to G1U on (BISTATE MODE) Fault Reset Delay to Clear Faultbar Rise Time of Upper and Lower Driver (Load = 2000pF) Fall Time of Upper and Lower Driver (Load = 2000pF) tOFF D tD.T. tR.T. tR U/L tF U/L TEMP MIN TYP MAX UNITS +25oC 2.5 3.2 4.5 µs -40oC to +85oC 2.1 3.3 5.2 µs +25oC 0.75 1.0 1.5 µs -40oC to +85oC 0.60 1.1 1.75 µs +25oC 0.75 1.0 1.5 µs -40oC to +85oC 0.60 1.1 1.75 µs +25oC 0.75 1.0 1.45 µs -40oC to +85oC 0.60 1.1 1.75 µs +25oC 1.5 2.5 3.5 µs -40oC to +85oC µs 1.2 2.6 4 +25oC 3.4 4.5 6.6 µs -40oC to +85oC 3.15 4.8 7.4 µs +25oC 25 50 100 ns -40oC to +85oC 15 50 115 ns +25oC 25 50 100 ns -40oC to +85oC 15 50 115 ns Recommended Operating Conditions and Functional Pin Description PARAMETER FAULTBAR ITRIPSELECT VBIAS CONDITION Open Drain Fault Indicator Output Digital Input Command to Increase TRIPL and TRIPU Threshold by 30% 14.5V to 16.5V with 15V nominal, ≅ 1.5mA DC BIAS Current VDD CDD to VSS VSS COMMON TRIP I CL1 G2L and G1L (All Voltages Referenced to VSS, Unless Otherwise Noted. See Figure 1) 100mV Signal to Shut Off LOWER Drive and Trigger a Fault Output Lower Noise Clamp Zener Low Impedance Driver Designed to Drive Power MOS Transistors (LOWER) VDF Current Limiting Charging Resistor for Bootstrap Capacitor Power Supply VBS Bootstrap Supply, Normally a Diode Drop Below VDD Voltage with Respect to the Floating PHASE Reference VOUT Load Connection Node PHASE Floating Reference Point for High Side Control Circuitry: VBS, TRIPU, CL2, G1U, G2U and D1U TRIPU 100mV Signal, Referenced to PHASE, to Shut Off UPPER Drive CL2 G2U and G1U Upper Noise Clamp Zener Low Impedance Driver Designed to Drive Power MOS Transistors (UPPER) TOP Digital Input to Command the UPPER On BOT Digital Input to Command the LOWER On D1U Miller Clamp UPPER to VBS D1L Miller Clamp LOWER to VDD 4 SP600 Timing Diagram TOP TOP 1 0 BOT REFRESH ONE SHOT IONB 0 1 0 BOT IOFFT IONT IOFFB REFRESH ONE SHOT 0 1 IONB 0 IOFFT 0 1 IONT 0 1 IOFFB 0 VOUT 0 1 0 0 1 0 1 0 1 0 1 UPPER 0 0 1 LOWER 1 1 VALID BOTON 0 1 1 UPPER 1 0 1 1 VALID BOTON 1 LOWER 0 VDC VOUT COM THREE-STATE MODE SLOWER THAN REFRESH ONE SHOT TIMER 1 0 VDC COM BISTATE MODE SLOWER THAN REFRESH ONE SHOT TIMER NOTE: BOT switching not relevant. Typical Circuit Configuration TRUTH TABLE Applicable to Typical Circuit Configuration (Figure 1) INPUTS OUTPUTS TOP BOT TRIPL TRIPU PHASE VBIAS UPPER LOWER FAULT BAR 0 0 0 X X 1 0 0 1 1 1 0 0 1 1 1 0 1 1 1 0 1 1 1 0 0 0 1 1 0 X 0 1 0 0 0 X X 1 X X 1 0 0 0 0 1 0 X X 1 0 1 1 1 0 0 X X 1 0 0 1 X X X X X 0 0 0 0 NOTE: 0 = False, 1 = True, X = Don’t Care 5 SP600 25VDC ≤ VLINK ≤ 500VDC RCU RDU RPU 19 18 17 D1U G1U G2U TRIPU SYSTEM CONTROL 21 22 1 2 14 15 PHASE VOUT VBS BOT VDF TOP SP600 HVIC D1L FAULT G1L ITRIPSELECT G2L VBIAS VDD 3 15V IBIAS VSS 4 TRIPL 13 12 CF 11 DF VOUT IBS 10 LOAD 9 RCL 8 RDL 6 RPL 5 COM CDD FIGURE 1. TYPICAL CIRCUIT CONFIGURATION LEGEND Application Specific RCU Upper Gate Charging Resistor Application Specific RDU Upper Gate Discharge Resistor Application Specific RPU Upper Current Pilot Resistor Application Specific RCL Lower Gate Charging Resistor Application Specific RDL Lower Gate Discharging Resistor Application Specific RPL Lower Current Pilot Resistor 3µF at ≥ 15DC CDD Local LV Filter Capacitor 0.22µF Ceramic X7R at ≥ 15VDC CF Flying Capacitor for Bootstrap Supply Harris P/N A114M or Equiv PRV ≥ VLINK DF Flying Diode for Bootstrap Supply NOTE: Refer to ‘Additional Product Offerings’ for information concerning power output devices. 6 SP600 Functional Description The SP600 provides a flexible, digitally controlled power function which is intended to be used as PWM drivers of N-Channel MOSFETs and/or IGBTs for up to 240VAC line rectified totem-pole applications. The CMOS driveable inputs are filtered and captured by the control logic to determine the output state. The logic includes fixed timing to prohibit simultaneous conduction of the external power switches and, thru the VOUT sense detector, verifies the output voltage state is in agreement with the controlled inputs. The >11VDC floating power supply required to drive the upper rail external power device is created and managed by the HVIC through CF and DF. This capacitor is refreshed from the VDD supply each time VOUT goes low. If the upper channel is commanded on for a long period of time, the bootstrap capacitor CF is automatically refreshed by bringing VOUT low. This is accomplished by turning off the upper rail MOSFET/IGBT, momentarily turning on the lower rail output device, followed by returning control back to the upper switch. Otherwise, CF would gradually deplete its charge allowing the upper switch to come out of saturation. The upper and lower gate drivers allow for controlled charge and discharge rates as well as facilitate the use of nearly lossless current sensing power MOS devices. The over current trip level can be boosted 30% on a pulse by pulse basis by logic level ‘1’ applied to ITRIPSELECT. A FAULT output signal is generated when any of the following occurs: V bias is low Over current is detected V phase doesn’t agree with the input signal Reset of FAULT is provided by externally removing power or by holding both TOP and BOT inputs low for the required reset time (trtMAX). Each application can be individually optimized by the selection of external components tailored to ensure proper overall system operation including: Determining the ratings and sizing of MOSFETs and IGBTs, mixed or matched, as well as flyback diodes (FBD). The selection of separate gate charge (RC) and discharge (RD) impedance chosen per the load capacitance, frequency of operation, and DI/DT dependent recovery characteristics of the associated FBDs. RD should also be sized to prevent simultaneous bridge conduction by ensuring gate discharge in the allotted turn off pulse width (tOFF MIN). The selection of over current detection resistors (RP), compatible with current sense MOSFETs/IGBTs or shunt(s) may be used. For the floating bootstrap supply DF and CF must be determined. DF must support the worse case system bus voltage and handle the charging currents of CF. Proper selection should take into consideration TRR and TFR per the desired operating frequency. Proper selection of CF is a trade off between the minimum tON time of the lower rail to charge up the capacitor, the amount of charge transfer required by the load, and cost. Due to automatic refresh the capacitor is replenished every 350µs TYP (or even sooner if input commands the TOP to switch at a faster repetition rate). The local filter capacitor (CDD) should be sized sufficiently large enough to transfer the charge to CF without causing a significant droop in VDD. As a rule of thumb it should be at least 10 times larger than CF and be located adjacent to the VDD and VSS pins to minimize series resistance and inductance. Refer to Application Note AN8829 for more details about module operation and selection of external components. 7