ICL7660S Data Sheet April 1999 File Number Super Voltage Converter Features The ICL7660S Super Voltage Converter is a monolithic CMOS voltage conversion IC that guarantees significant performance advantages over other similar devices. It is a direct replacement for the industry standard ICL7660 offering an extended operating supply voltage range up to 12V, with lower supply current. No external diode is needed for the ICL7660S. In addition, a Frequency Boost pin has been incorporated to enable the user to achieve lower output impedance despite using smaller capacitors. All improvements are highlighted in the Electrical Specifications section. Critical parameters are guaranteed over the entire commercial, industrial and military temperature ranges. • Guaranteed Lower Max Supply Current for All Temperature Ranges The ICL7660S performs supply voltage conversion from positive to negative for an input range of 1.5V to 12V, resulting in complementary output voltages of -1.5V to -12V. Only 2 non-critical external capacitors are needed for the charge pump and charge reservoir functions. The ICL7660S can be connected to function as a voltage doubler and will generate up to 22.8V with a 12V input. It can also be used as a voltage multiplier or voltage divider. • Improved SCR Latchup Protection The chip contains a series DC power supply regulator, RC oscillator, voltage level translator, and four output power MOS switches. The oscillator, when unloaded, oscillates at a nominal frequency of 10kHz for an input supply voltage of 5.0V. This frequency can be lowered by the addition of an external capacitor to the “OSC” terminal, or the oscillator may be over-driven by an external clock. Applications The “LV” terminal may be tied to GND to bypass the internal series regulator and improve low voltage (LV) operation. At medium to high voltages (3.5V to 12V), the LV pin is left floating to prevent device latchup. • Wide Operating Voltage Range 1.5V to 12V • 100% Tested at 3V • No External Diode Over Full Temperature and Voltage Range • Boost Pin (Pin 1) for Higher Switching Frequency • Guaranteed Minimum Power Efficiency of 96% • Improved Minimum Open Circuit Voltage Conversion Efficiency of 99% • Simple Conversion of +5V Logic Supply to ±5V Supplies • Simple Voltage Multiplication VOUT = (-)nVIN • Easy to Use - Requires Only 2 External Non-Critical Passive Components • Improved Direct Replacement for Industry Standard ICL7660 and Other Second Source Devices • Simple Conversion of +5V to ±5V Supplies • Voltage Multiplication VOUT = ±nVIN • Negative Supplies for Data Acquisition Systems and Instrumentation • RS232 Power Supplies • Supply Splitter, VOUT = ±VS/2 Pinouts ICL7660S (PDIP, SOIC) TOP VIEW Ordering Information TEMP. RANGE (oC) PACKAGE ICL7660SCBA 0 to 70 8 Ld P SOIC (N) ICL7660SCPA 0 to 70 ICL7660SIBA BOOST 1 8 V+ CAP+ 2 7 OSC M8.15 GND 3 6 LV 8 Ld PDIP E8.3 CAP- 4 5 VOUT -40 to 85 8 Ld P SOIC (N) M8.15 ICL7660SIPA -40 to 85 8 Ld PDIP E8.3 ICL7660SMTV (Note) -55 to 125 8 Pin Metal Can T8.C PART NUMBER 3179.2 PKG. NO. ICL7660S (CAN) TOP VIEW V+ (AND CASE) 8 BOOST 1 7 OSC NOTE: Add /883B to part number if 883B processing is required. 6 LV CAP+ 2 GND 3 4 CAP- 3-36 5 VOUT CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 ICL7660S Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13.0V LV and OSC Input Voltage (Note 1) V+ < 5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V+ + 0.3V V+ > 5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . V+ -5.5V to V+ +0.3V Current into LV (Note 1) V+ > 3.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20µA Output Short Duration VSUPPLY ≤ 5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Continuous Storage Temperature Range . . . . . . . . . . . . . . . . . . -65oC to 150oC Thermal Resistance (Typical, Note 2) θJA (oC/W) θJC (oC/W) PDIP. . . . . . . . . . . . . . . . . . . . . . . . . . . 150 N/A Plastic SOIC. . . . . . . . . . . . . . . . . . . . . 170 N/A Metal Can. . . . . . . . . . . . . . . . . . . . . . . 155 70 Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range ICL7660SM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC ICL7660SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC ICL7660SC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Connecting any terminal to voltages greater than V+ or less than GND may cause destructive latchup. It is recommended that no inputs from sources operating from external supplies be applied prior to “power up” of ICL7660S. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER V+ = 5V, TA = 25oC, OSC = Free running, Test Circuit Figure 12, Unless Otherwise Specified SYMBOL Supply Current (Note 5) I+ TEST CONDITIONS RL = ∞ , 25oC 0oC < TA < +70oC -40oC < TA < 85oC -55oC < TA < 125oC MIN TYP MAX UNITS - 80 160 µA - - 180 µA - - 180 µA - - 200 µA Supply Voltage Range - High (Note 6) V+H RL = 10K, LV Open, TMIN < TA < TMAX 3.0 - 12 V Supply Voltage Range - Low V+L RL = 10K, LV to GND, TMIN < TA < TMAX 1.5 - 3.5 V IOUT = 20mA - 60 100 Ω IOUT = 20mA, 0oC < TA < 70oC IOUT = 20mA, -25oC < TA < 85oC IOUT = 20mA, -55oC < TA < 125oC - - 120 Ω - - 120 Ω - - 150 Ω IOUT = 3mA, V+ = 2V, LV = GND, 0oC < TA < 70oC - - 250 Ω IOUT = 3mA, V+ = 2V, LV = GND, -40oC < TA < 85oC - - 300 Ω IOUT = 3mA, V+ = 2V, LV = GND, -55oC < TA < 125oC - - 400 Ω COSC = 0, Pin 1 Open or GND 5 10 - kHz COSC = 0, Pin 1 = V+ - 35 - kHz RL = 5kΩ 96 98 - % TMIN < TA < TMAX RL = 5kΩ 95 97 - - RL = ∞ 99 99.9 - % Output Source Resistance ROUT Oscillator Frequency (Note 5) Power Efficiency fOSC PEFF Voltage Conversion Efficiency VOUTEFF 3-37 ICL7660S V+ = 5V, TA = 25oC, OSC = Free running, Test Circuit Figure 12, Unless Otherwise Specified (Continued) Electrical Specifications PARAMETER SYMBOL Oscillator Impedance ZOSC TEST CONDITIONS MIN TYP MAX UNITS V+ = 2V - 1 - MΩ V+ = 5V - 100 - kΩ NOTES: 3. Derate linearly above 50oC by 5.5mW/oC 4. In the test circuit, there is no external capacitor applied to pin 7. However, when the device is plugged into a test socket, there is usually a very small but finite stray capacitance present, of the order of 5pF. 5. The Intersil ICL7660S can operate without an external diode over the full temperature and voltage range. This device will function in existing designs which incorporate an external diode with no degradation in overall circuit performance. 6. All significant improvements over the industry standard ICL7660 are highlighted. Typical Performance Curves (Test Circuit Figure 12) 12 OUTPUT SOURCE RESISTANCE (Ω) 250 SUPPLY VOLTAGE (V) 10 8 SUPPLY VOLTAGE RANGE (NO DIODE REQUIRED) 6 4 2 0 TA = 125oC 200 TA = 25oC 150 TA = -55oC 100 50 0 -55 -25 0 25 50 100 125 0 TEMPERATURE (oC) FIGURE 1. OPERATING VOLTAGE AS A FUNCTION OF TEMPERATURE POWER CONVERSION EFFICIENCY (%) OUTPUT SOURCE RESISTANCE (Ω) 10 12 98 300 250 IOUT = 3mA, V+ = 2V IOUT = 20mA, V+ = 5V 150 IOUT = 20mA, V+ = 5V 100 50 IOUT = 20mA, V+ = 12V 0 -50 4 6 8 SUPPLY VOLTAGE (V) FIGURE 2. OUTPUT SOURCE RESISTANCE AS A FUNCTION OF SUPPLY VOLTAGE 350 200 2 -25 0 25 50 75 100 TEMPERATURE (oC) FIGURE 3. OUTPUT SOURCE RESISTANCE AS A FUNCTION OF TEMPERATURE 3-38 125 96 94 92 V+ = 5V TA = 25oC IOUT = 1mA 90 88 86 84 82 80 100 1k 10k OSC FREQUENCY FOSC (Hz) FIGURE 4. POWER CONVERSION EFFICIENCY AS A FUNCTION OF OSCILLATOR FREQUENCY 50k ICL7660S Typical Performance Curves (Test Circuit Figure 12) (Continued) 20 V+ = 5V TA = 25oC 9 OSCILLATOR FREQUENCY fOSC (kHz) 8 7 6 5 4 3 2 1 18 16 14 V+ = 10V 12 10 V+ = 5V 8 0 10 100 -55 1k -25 0 25 FIGURE 5. FREQUENCY OF OSCILLATION AS A FUNCTION OF EXTERNAL OSCILLATOR CAPACITANCE POWER CONVERSION EFFICIENCY (%) V+ = 5V TA = 25oC OUTPUT VOLTAGE (V) -1 -2 -3 -4 100 100 90 90 80 80 70 70 60 60 50 50 40 40 30 30 20 V+ = 5V 20 10 TA = 25oC 10 0 0 0 10 125 100 -5 20 30 LOAD CURRENT (mA) 0 40 10 20 30 40 50 60 LOAD CURRENT (mA) FIGURE 7. OUTPUT VOLTAGE AS A FUNCTION OF OUTPUT CURRENT FIGURE 8. SUPPLY CURRENT AND POWER CONVERSION EFFICIENCY AS A FUNCTION OF LOAD CURRENT 100 2 V+ = 2V TA = 25oC 90 1 POWER CONVERSION EFFICIENCY (%) OUTPUT VOLTAGE (V) 75 FIGURE 6. UNLOADED OSCILLATOR FREQUENCY AS A FUNCTION OF TEMPERATURE 1 0 50 TEMPERATURE (oC) COSC (pF) SUPPLY CURRENT (mA) 1 0 -1 80 16 70 14 60 12 50 10 40 8 30 6 V+ = 2V 20 4 TA = 25oC 10 2 0 -2 0 1 2 3 4 5 6 7 8 9 LOAD CURRENT (mA) FIGURE 9. OUTPUT VOLTAGE AS A FUNCTION OF OUTPUT CURRENT 3-39 SUPPLY CURRENT (mA) (NOTE 8) OSCILLATOR FREQUENCY fOSC (kHz) 10 0 0 1.5 3 4.5 6 7.5 LOAD CURRENT (mA) 9 FIGURE 10. SUPPLY CURRENT AND POWER CONVERSION EFFICIENCY AS A FUNCTION OF LOAD CURRENT ICL7660S Typical Performance Curves (Test Circuit Figure 12) (Continued) V+ = 5V TA = 25oC I = 10mA OUTPUT RESISTANCE (Ω) 400 C1 = C2 = 1µF C1 = C2 = 10µF 300 C1 = C2 = 100µF 200 100 0 100 1k 10k 100k OSCILLATOR FREQUENCY (Hz) FIGURE 11. OUTPUT SOURCE RESISTANCE AS A FUNCTION OF OSCILLATOR FREQUENCY NOTE: 7. These curves include in the supply current that current fed directly into the load RL from the V+ (See Figure 12). Thus, approximately half the supply current goes directly to the positive side of the load, and the other half, through the ICL7660S, to the negative side of the load. Ideally, VOUT ∼ 2VIN, IS ∼ 2IL, so VIN x IS ∼ VOUT x IL. Detailed Description The ICL7660S contains all the necessary circuitry to complete a negative voltage converter, with the exception of 2 external capacitors which may be inexpensive 10µF polarized electrolytic types. The mode of operation of the device may be best understood by considering Figure 13, which shows an idealized negative voltage converter. Capacitor C1 is charged to a voltage, V+, for the half cycle when switches S1 and S3 are closed. (Note: Switches S2 and S4 are open during this half cycle.) During the second half cycle of operation, switches S2 and S4 are closed, with S1 and S3 open, thereby shifting capacitor C1 to C2 such that the voltage on C2 is exactly V+, assuming ideal switches and no load on C2. The ICL7660S approaches this ideal situation more closely than existing non-mechanical circuits. V+ IS V+ 1 7 IL 3 6 RL 4 5 2 C1 + 10µF - (+5V) 8 ICL7660S -VOUT C2 10µF + must always remain reverse biased with respect to their sources, but not so much as to degrade their “ON” resistances. In addition, at circuit start up, and under output short circuit conditions (VOUT = V+), the output voltage must be sensed and the substrate bias adjusted accordingly. Failure to accomplish this would result in high power losses and probable device latchup. This problem is eliminated in the ICL7660S by a logic network which senses the output voltage (VOUT) together with the level translators, and switches the substrates of S3 and S4 to the correct level to maintain necessary reverse bias. The voltage regulator portion of the ICL7660S is an integral part of the anti-latchup circuitry, however its inherent voltage drop can degrade operation at low voltages. Therefore, to improve low voltage operation “LV” pin should be connected to GND, disabling the regulator. For supply voltages greater than 3.5V the LV terminal must be left open to insure latchup proof operation, and prevent device damage. Theoretical Power Efficiency Considerations In theory a voltage converter can approach 100% efficiency if certain conditions are met: 1. The drive circuitry consumes minimal power. NOTE: For large values of COSC (>1000pF) the values of C1 and C2 should be increased to 100µF. FIGURE 12. ICL7660S TEST CIRCUIT In the ICL7660S, the 4 switches of Figure 13 are MOS power switches; S1 is a P-Channel devices and S2, S3 and S4 are N-Channel devices. The main difficulty with this approach is that in integrating the switches, the substrates of S3 and S4 3-40 2. The output switches have extremely low ON resistance and virtually no offset. 3. The impedance of the pump and reservoir capacitors are negligible at the pump frequency. ICL7660S The ICL7660S approaches these conditions for negative voltage conversion if large values of C1 and C2 are used. ENERGY IS LOST ONLY IN THE TRANSFER OF CHARGE BETWEEN CAPACITORS IF A CHANGE IN VOLTAGE OCCURS. The energy lost is defined by: E = 1/2C1 (V12 - V22) where V1 and V2 are the voltages on C1 during the pump and transfer cycles. If the impedances of C1 and C2 are relatively high at the pump frequency (refer to Figure 13) compared to the value of RL, there will be substantial difference in the voltages V1 and V2. Therefore it is not only desirable to make C2 as large as possible to eliminate output voltage ripple, but also to employ a correspondingly large value for C1 in order to achieve maximum efficiency of operation. 8 S1 2 Typical Applications Simple Negative Voltage Converter The majority of applications will undoubtedly utilize the ICL7660S for generation of negative supply voltages. Figure 14 shows typical connections to provide a negative supply where a positive supply of +1.5V to +12V is available. Keep in mind that pin 6 (LV) is tied to the supply negative (GND) for supply voltage below 3.5V. V+ 1 10µF 8 2 + - ICL7660S 3 6 4 5 4 VOUT = -V+ V+ + 14B. FIGURE 14. SIMPLE NEGATIVE CONVERTER AND ITS OUTPUT EQUIVALENT C2 S4 5 VOUT = -VIN 7 FIGURE 13. IDEALIZED NEGATIVE VOLTAGE CONVERTER Do’s and Don’ts 1. Do not exceed maximum supply voltages. 2. Do not connect LV terminal to GND for supply voltage greater than 3.5V. 3. Do not short circuit the output to V+ supply for supply voltages above 5.5V for extended periods, however, transient conditions including start-up are okay. 4. When using polarized capacitors, the + terminal of C1 must be connected to pin 2 of the ICL7660S and the + terminal of C2 must be connected to GND. 5. If the voltage supply driving the ICL7660S has a large source impedance (25Ω - 30Ω), then a 2.2µF capacitor from pin 8 to ground may be required to limit rate of rise of input voltage to less than 2V/µs. 6. User should insure that the output (pin 5) does not go more positive than GND (pin 3). Device latch up will occur under these conditions. A 1N914 or similar diode placed in parallel with C2 will prevent the device from latching up under these conditions. (Anode pin 5, Cathode pin 3). 3-41 14A. 3 VOUT - 10µF + C1 S3 RO - S2 VIN 3 7 The output characteristics of the circuit in Figure 14 can be approximated by an ideal voltage source in series with a resistance as shown in Figure 14B. The voltage source has a value of -(V+). The output impedance (RO) is a function of the ON resistance of the internal MOS switches (shown in Figure 13), the switching frequency, the value of C1 and C2, and the ESR (equivalent series resistance) of C1 and C2. A good first order approximation for RO is: RO ≅ 2(RSW1 + RSW3 + ESRC1) + 2(RSW2 + RSW4 + ESRC1) + 1 fPUMP x C1 (fPUMP = + ESRC2 fOSC 2 , RSWX = MOSFET switch resistance) Combining the four RSWX terms as RSW, we see that: 1 RO ≅ 2 x RSW + fPUMP x C1 + 4 x ESRC1 + ESRC2Ω RSW, the total switch resistance, is a function of supply voltage and temperature (See the Output Source Resistance graphs), typically 23Ω at 25oC and 5V. Careful selection of C1 and C2 will reduce the remaining terms, minimizing the output impedance. High value capacitors will reduce the 1/(fPUMP x C1) component, and low ESR capacitors will lower the ESR term. Increasing the oscillator frequency will reduce the 1/(fPUMP x C1) term, but may have the side effect of a net increase in output impedance when C1 > 10µF and is not long ICL7660S enough to fully charge the capacitors every cycle. In a typical application where fOSC = 10kHz and C = C1 = C2 = 10µF: RO ≅ 2 x 23 + 1 (5 x 103 x 10 x 10-6) + 4 x ESRC1 + ESRC2 RO ≅ 46 + 20 + 5 x ESRCΩ Since the ESRs of the capacitors are reflected in the output impedance multiplied by a factor of 5, a high value could potentially swamp out a low 1/fPUMP x C1) term, rendering an increase in switching frequency or filter capacitance ineffective. Typical electrolytic capacitors may have ESRs as high as 10Ω. Output Ripple ESR also affects the ripple voltage seen at the output. The total ripple is determined by 2 voltages, A and B, as shown in Figure 15. Segment A is the voltage drop across the ESR of C2 at the instant it goes from being charged by C1 (current flowing into C2) to being discharged through the load (current flowing out of C2). The magnitude of this current change is 2 x IOUT, hence the total drop is 2 x IOUT x ESRC2V. Segment B is the voltage change across C2 during time t2, the half of the cycle when C2 supplies current the load. The drop at B is IOUT x t2/C2V. The peak-to-peak ripple voltage is the sum of these voltage drops: V 1 RIPPLE ≅ -------------------------------------------- + 2 ESRC 2 × I OUT 2 × f PUMP × C 2 Changing the ICL7660S Oscillator Frequency It may be desirable in some applications, due to noise or other considerations, to alter the oscillator frequency. This can be achieved simply by one of several methods described below. By connecting the Boost Pin (Pin 1) to V+, the oscillator charge and discharge current is increased and, hence, the oscillator frequency is increased by approximately 31/2 times. The result is a decrease in the output impedance and ripple. This is of major importance for surface mount applications where capacitor size and cost are critical. Smaller capacitors, e.g. 0.1µF, can be used in conjunction with the Boost Pin in order to achieve similar output currents compared to the device free running with C1 = C2 = 10µF or 100µF. (Refer to graph of Output Source Resistance as a Function of Oscillator Frequency). Increasing the oscillator frequency can also be achieved by overdriving the oscillator from an external clock, as shown in Figure 18. In order to prevent device latchup, a 1kΩ resistor must be used in series with the clock output. In a situation where the designer has generated the external clock frequency using TTL logic, the addition of a 10kΩ pullup resistor to V+ supply is required. Note that the pump frequency with external clocking, as with internal clocking, will be 1/2 of the clock frequency. Output transitions occur on the positive going edge of the clock. V+ Again, a low ESR capacitor will result in a higher performance output. 10µF Any number of ICL7660S voltage converters may be paralleled to reduce output resistance. The reservoir capacitor, C2, serves all devices while each device requires its own pump capacitor, C1. The resultant output resistance would be approximately: ROUT (of ICL7660S) n (number of devices) Cascading Devices The ICL7660S may be cascaded as shown to produce larger negative multiplication of the initial supply voltage. However, due to the finite efficiency of each device, the practical limit is 10 devices for light loads. The output voltage is defined by: VOUT = -n(VIN), where n is an integer representing the number of devices cascaded. The resulting output resistance would be approximately the weighted sum of the individual ICL7660S ROUT values. 3-42 8 1kΩ 2 + Paralleling Devices ROUT = 1 V+ - ICL7660S CMOS GATE 7 3 6 4 5 + VOUT 10µF FIGURE 15. EXTERNAL CLOCKING It is also possible to increase the conversion efficiency of the ICL7660S at low load levels by lowering the oscillator frequency. This reduces the switching losses, and is shown in Figure 19. However, lowering the oscillator frequency will cause an undesirable increase in the impedance of the pump (C1) and reservoir (C2) capacitors; this is overcome by increasing the values of C1 and C2 by the same factor that the frequency has been reduced. For example, the addition of a 100pF capacitor between pin 7 (OSC and V+ will lower the oscillator frequency to 1kHz from its nominal frequency of 10kHz (a multiple of 10), and thereby necessitate corresponding increase in the value of C1 and C2 (from 10µF to 100µF). ICL7660S V+ V+ 1 2 + C1 - 1 8 COSC 7 ICL7660S 3 6 4 5 2 C1 + + - VOUT = -VIN 8 ICL7660S 7 3 6 4 5 VOUT C2 - D1 D2 + C3 + VOUT = (2V+) (VFD1) - (VFD2) C2 + C - 4 FIGURE 16. LOWERING OSCILLATOR FREQUENCY Positive Voltage Doubling The ICL7660S may be employed to achieve positive voltage doubling using the circuit shown in Figure 20. In this application, the pump inverter switches of the ICL7660S are used to charge C1 to a voltage level of V+ -VF (where V+ is the supply voltage and VF is the forward voltage on C1 plus the supply voltage (V+) is applied through diode D2 to capacitor C2. The voltage thus created on C2 becomes (2V+) - (2VF) or twice the supply voltage minus the combined forward voltage drops of diodes D1 and D2. The source impedance of the output (VOUT) will depend on the output current, but for V+ = 5V and an output current of 10mA it will be approximately 60Ω. V+ 1 2 FIGURE 18. COMBINED NEGATIVE VOLTAGE CONVERTER AND POSITIVE DOUBLER Voltage Splitting The bidirectional characteristics can also be used to split a high supply in half, as shown in Figure 22. The combined load will be evenly shared between the two sides, and a high value resistor to the LV pin ensures start-up. Because the switches share the load in parallel, the output impedance is much lower than in the standard circuits, and higher currents can be drawn from the device. By using this circuit, and then the circuit of Figure 17, +15V can be converted (via +7.5, and -7.5 to a nominal -15V, although with rather high series output resistance (∼250Ω). 8 ICL7660S 3 6 4 5 V+ D1 7 + D2 VOUT = (2V+) - (2VF) + + - C1 - C2 RL1 50µF 1 VOUT = V+ - V2 50µF 2 + - RL2 NOTE: D1 and D2 can be any suitable diode. 8 ICL7660S 7 3 6 4 5 + 50µF V- FIGURE 17. POSITIVE VOLTAGE DOUBLER Combined Negative Voltage Conversion and Positive Supply Doubling Figure 21 combines the functions shown in Figure 14 and Figure 20 to provide negative voltage conversion and positive voltage doubling simultaneously. This approach would be, for example, suitable for generating +9V and -5V from an existing +5V supply. In this instance capacitors C1 and C3 perform the pump and reservoir functions respectively for the generation of the negative voltage, while capacitors C2 and C4 are pump and reservoir respectively for the doubled positive voltage. There is a penalty in this configuration which combines both functions, however, in that the source impedances of the generated supplies will be somewhat higher due to the finite impedance of the common charge pump driver at pin 2 of the device. 3-43 FIGURE 19. SPLITTING A SUPPLY IN HALF Regulated Negative Voltage Supply In Some cases, the output impedance of the ICL7660S can be a problem, particularly if the load current varies substantially. The circuit of Figure 23 can be used to overcome this by controlling the input voltage, via an ICL7611 low-power CMOS op amp, in such a way as to maintain a nearly constant output voltage. Direct feedback is inadvisable, since the ICL7660S’s output does not respond instantaneously to change in input, but only after the switching delay. The circuit shown supplies enough delay to accommodate the ICL7660S, while maintaining adequate feedback. An increase in pump and storage capacitors is desirable, and the values shown provides an output impedance of less than 5Ω to a load of 10mA. ICL7660S Further information on the operation and use of the ICL7660S may be found in AN051 “Principles and Applications of the ICL7660 CMOS Voltage Converter”. 50k +8V 56k +8V 100Ω 50k + 10µF 100k ICL7611 + 1 2 ICL8069 100µF + - 8 ICL7660S 7 3 6 4 5 800k VOUT - 250k VOLTAGE ADJUST + 100µF FIGURE 20. REGULATING THE OUTPUT VOLTAGE Other Applications +5V LOGIC SUPPLY 12 TTL DATA INPUT 11 16 1 4 3 RS232 DATA OUTPUT 15 1 10µF - -5V 8 7 IH5142 3 6 13 4 5 2 + +5V ICL7660S 10µF 14 + FIGURE 21. RS232 LEVELS FROM A SINGLE 5V SUPPLY All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 3-44 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029