Datasheet

UNISONIC TECHNOLOGIES CO., LTD
UB209B
Preliminary
CMOS IC
BATTERY PROTECTION IC
WITH CELL-BALANCE
FUNCTION

DESCRIPTION
The UTC UB209B Series is a protection IC for
lithium-ion/lithium polymer rechargeable batteries, including a
high precision voltage detection circuit and a delay circuit.
The UTC UB209B Series has a transmission function and two
types of cell-balance function so that users are also able to
configure a protection circuit with series multi-cell.

TSSOP-8
FEATURES
* Settable delay time by external capacitor for output pin
* High-accuracy voltage detection circuit
* Two types of cell-balance function: charge/discharge
* Control charging, discharging, cell-balance by CTLC, CTLD pins
* Low current consumption: 8.0µA max
* Wide range of operation temperature (-40°C~+85°C)

ORDERING INFORMATION
Ordering Number
Lead Free
Halogen Free
UB209BL-P08-R
UB209BG-P08-R
Note: xx: Output Voltage, refer to Marking Information.
UB209BG-xx-P08-R

Package
Packing
TSSOP-8
Tape Reel
(1)Packing Type
(1) R: Tape Reel
(2)Package Type
(2) P08: TSSOP-8
(3)Output Voltage Code
(3) xx: Refer to Marking Information
(4)Halogen Free
(4) Halogen Free, L: Lead Free
SERIAL CODE LIST
Overcharge Overcharge Cell-balance Cell-balance Overdischarge Overdischarge
Discharge
Detection
Release
Detection
Release
Detection
Release
Model Code
Cell-balance
Voltage
Voltage
Voltage
Voltage
Voltage
Voltage
Function
[VCU](V)
[VCL](V)
[VBU](V)
[VBL](V)
[VDL](V)
[VDU](V)
AA
4.100
4.000
4.050
4.000
2.50
2.70
Yes
AB
3.800
3.750
3.650
3.600
2.00
2.50
Yes
AC
3.900
3.500
3.550
3.550
2.50
2.70
Yes
AD
4.250
4.100
4.200
4.100
2.50
3.00
Yes
UB209B
AE
4.000
3.900
3.950
3.900
2.50
2.70
Yes
AF
4.250
4.100
4.100
4.000
2.75
3.05
Yes
AG
3.900
3.600
3.550
3.500
2.00
2.40
Yes
AH
3.900
3.700
3.600
3.600
2.50
2.80
No
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UB209B


Preliminary
CMOS IC
PIN CONFIGURATION
CTLC
1
8
CB
CTLD
2
7
CO
VDD
3
6
DO
CDT
4
5
VSS
PIN DESCRIPTION
PIN NO.
1
2
3
PIN NAME
CTLC
CTLD
VDD
4
CDT
5
6
7
8
VSS
DO
CO
CB
DESCRIPTION
Pin for charge control
Pin for discharge control
Connection pin for input positive power supply, for battery’s positive voltage
Connection pin to capacitor for overcharge detection delay, for over discharge detection
delay
Input pin for negative power supply, Connection pin for battery’s negative voltage
Output pin for discharge control (Pch open drain output)
Output pin for charge control (Pch open drain output)
Output pin for cell-balance control (CMOS output)
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UB209B

Preliminary
CMOS IC
BLOCK DIAGRAM
CO
Logic Control and Delay Circuit
8.31 MΩ
CDT
DO
VDD
+
CB
Cell-balance
detection
comparator
+
CTLC
Overcharge
detection
comparator
400 nA
+
CTLD
Overdischarge
detection
comparator
VSS
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400 nA
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
Preliminary
CMOS IC
ABSOLUTE MAXIMUM RATING (TA=25°C unless otherwise specified)
PARAMETER
SYMBOL
RATINGS
UNIT
Input Voltage Between VDD and VSS
VDS
VSS-0.3~VSS+12
V
CB Pin Output Voltage
VCB
VSS-0.3~VDD+0.3
V
CDT Pin Voltage
VCDT
VSS-0.3~VDD+0.3
V
DO Pin Output Voltage
VDO
VDD-24~VDD+0.3
V
CO Pin Output Voltage
VCO
VDD-24~VDD+0.3
V
CTLC Pin Input Voltage
VCTLC
VSS-0.3~VSS+24
V
CTLD Pin Input Voltage
VCTLD
VSS-0.3~VSS+24
V
Power Dissipation (Note 2)
PD
700
mW
Operating Ambient Temperature
TOPR
-40~+85
°C
Storage Temperature
TSTG
-55~+125
°C
Note: 1. Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
2. When mounted on board: 114.3mm×76.2mm×1.6mm
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
Preliminary
CMOS IC
ELECTRICAL CHARACTERISTICS (TA=25°C unless otherwise specified)
PARAMETER
Overcharge Detection Voltage
Overcharge Release Voltage
Cell-balance Detection
Voltage
Cell-balance Release Voltage
Over Discharge Detection
Voltage
Over Discharge Release
Voltage
CDT Pin Resistance (Note 1)
CDT Pin Detection Voltage
(Note 1)
Operating Voltage Between
VDD and VSS
CTLC Pin H Voltage
CTLD Pin H Voltage
CTLC Pin L Voltage
CTLD Pin L Voltage
Current Consumption During
Operation (Note 2)
MIN
TYP
MAX
UNIT
VCU
VCL
VCU -0.05
VCL-0.05
VCU
VCL
VCU +0.05
VCL+0.05
V
V
Test
circuit
1
1
VBU
VBU-0.05
VBU
VBU+0.05
V
1
VBL
VBL-0.05
VBL
VBL+0.05
V
1
VDL
VDL-0.10
VDL
VDL+0.10
V
1
VDU
VDU-0.10
VDU
VDU+0.10
V
1
4.76
8.31
10.9
MΩ
2
V
3
SYMBOL TEST CONDITIONS
RCDT
VDS=3.5V, VCDT=0V
VCDET
VDS=3.5V
VDSOP
VCTLCH
VCTLDH
VCTLCL
VCTLDL
IOPE
Output Voltage of
CO, DO, CB Fixed
VDS=3.5V
VDS=3.5V
VDS=3.5V
VDS=3.5V
VDS=3.5V
VDS×0.65 VDS×0.70 VDS×0.75
1.5
8.0
V
VDS×0.55
VDS×0.55
VDS×0.10
VDS×0.10
VDS×0.90
VDS×0.90
VDS×0.45
VDS×0.45
V
V
V
V
4
4
4
4
8.0
µA
5
3.5
VDS=3.5V,
300
400
500
nA
6
VCTLC=3.5V
VDS=3.5V,
300
400
500
nA
6
Sink Current CTLD (Note 2)
ICTLDL
VCTLD=3.5V
Source Current CB
ICBH
VCB=4.0V, VDS=4.5V
30
µA
7
Sink Current CB
ICBL
VCB=0.5V, VDS=3.5V
30
µA
7
Source Current CO
ICOH
VCO=3.0V, VDS=3.5V
30
µA
7
Leakage Current CO
ICOL
VCO=24V, VDS=4.5V
0.2
µA
8
Source Current DO
IDOH
VDO=3.0V, VDS=3.5V
30
µA
7
Leakage Current DO
IDOL
VDO=24V, VDS=1.8V
0.2
µA
8
Notes:1. In the UTC UB209B Series, users are able to set delay time for the output pins. By using the following
formula, delay time is calculated with the value of CDT pin’s resistance in the IC (RCDT) and the value
of capacitor set externally at the CDT pin (CCDT).
tD [s]=-ln(1-VCDET /VDS)×CCDT [µF]×RCDT [MΩ]
=-ln (1-0.7(Typ.) )×CCDT [µF]×8.31MΩ(Typ.)
=10.0MΩ(Typ.)×CCDT [µF]
In case of the capacitance of CDT pin CCDT=0.01µF, the output pin delay time tD is calculated by using
the above formula and as follows.
tD [s]=10.0MΩ (Typ.)×0.01µF=0.1s (Typ.)
Test RCDT and the CDT pin detection voltage (VCDET) by test circuits shown in this datasheet after
applying the power supply while pulling-down the CTLC, CTLD pins to the level of VDD pin outside the
IC.
2. In case of using CTLC, CTLD pins pulled-down to the level of VDD pin externally, the current flows into
the VSS pin (ISS) is calculated by the following formula.
ISS=IOPE+ICTLCL+ICTLDL
Sink Current CTLC (Note 2)
ICTLCL
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UB209B

Preliminary
CMOS IC
TEST CIRCUIT
CTLC
CB
CTLD
CO
VDD
CDT
UTC
UB209B
100 kΩ
100 kΩ
DO
CTLC
CB
CTLD
CO
VDD
DO
UTC
UB209B
VSS
CDT
VSS
V
V
A
V
COM
COM
Figure 1. Test Circuit 1
Figure 2. Test Circuit 2
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100 kΩ
100 kΩ
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UB209B

Preliminary
CMOS IC
TEST CIRCUIT(Cont.)
A
CTLC
CTLC
CB
CTLD UTC CO
UB209A
DO
VDD
CTLD UTC CO
UB209A
DO
VDD
CDT
COM

VSS
A
CB
A
A
Figure 7. Test Circuit 7
A
CDT
VSS
COM
Figure 8. Test Circuit 8
OPERATION
Figure 9 shows the operation transition of UTC UB209B.
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UB209B
Preliminary
CMOS IC
1. Normal Status
In the UTC UB209B, both of CO and DO pin get the VDD level; the voltage between VDD and VSS (VDS) is more
than the overdischarge detection voltage (VDL), and is less than the overcharge detection voltage (VCU) and
respectively, the CTLC pin input voltage (VCTLC) > the CTLC pin voltage “L” (VCTLCL), the CTLD pin input voltage
(VCTLD) > the CTLD pin voltage “L” (VCTLDL). This is the normal status.
2. Overcharge Status
In the UTC UB209B, the CO pin is in high impedance; when VDS gets VCU or more, or VCTLC gets VCTLCL or less.
This is the overcharge status.
If VDS gets the overcharge release voltage (VCL) or less, and VCTLC gets the CTLC pin voltage “H” (VCTLCH) or more,
the UTC UB209B releases the overcharge status to return to the normal status.
3. Overdischarge Status
In the UTC UB209B, the DO pin is in high impedance; when VDS gets VDL or less, or VCTLD gets VCTLDL or less.
This is the overdischarge status.
If VDS gets the overdischarge release voltage (VDU) or more, and VCTLD gets the CTLD pin voltage “H” (VCTLDH) or
more, the UTC UB209B releases the overdischarge status to return to the normal status.
4. Cell-balance Function
In the UTC UB209B, the CB pin gets the level of VDD pin; when VDS gets the cell-balance detection voltage (VBU)
or more. This is the charge cell-balance function.
If VDS gets the cell-balance release voltage (VBL) or less again, the UTC UB209B sets the CB pin the level of VSS
pin.
In addition, the CB pin gets the level of VDD pin; when VDS is more than VDL, and VCTLD is VCTLDL or less. This is the
discharge cell-balance function.
If VCTLD gets VCTLDH or more, or VDS is VDL or less again, the UTC UB209B sets the CB pin the level of VSS.
5. Delay Circuit
In the UTC UB209B, users are able to set delay time which is from detection of changes in VDS, VCTLC, VCTLD to
output to the CO, DO, CB pin.
For example in the detection of overcharge status, when VDS exceeds VCU, or VCTLC gets VCTLCH or less, charging
to CCDT starts via RCDT. If the voltage between CDT and VSS (VCDT) reaches the CDT pin detection voltage (VCDET),
the CO pin is in high impedance. The output pin delay time tD is calculated by the following formula.
tD [s]=10.0MΩ (Typ.)×CCDT [µF]
The electric charge in CCDT starts to be discharged when the delay time has finished.
The delay time that users have set for the CO pin, as seen above, is settable for each output pin DO, CB.
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
Preliminary
CMOS IC
TYPICAL APPLICATION CIRCUIT
EB+
1 kΩ
CFET
1 kΩ
DFET
CTLD1
1 MΩ
1 MΩ
VDD1
CTLC1
CB1
UTC UB209B
(1)
DO1
CDT1
CO1
1 kΩ
VSS1
BAT1
0.1 µF
470 Ω
1 kΩ
CTLD2
VDD2
CTLC2
CB2
UTC UB209B
(2)
DO2
CDT2
1 kΩ
CO2
0.1 µF
VSS2
470 Ω
1 kΩ
CTLD3
BAT2
VDD3
CTLC3
CB3
UTC UB209B
(3)
0.01 µF
DO3
CDT3
CO3
EB-
510 kΩ
510 kΩ
1 MΩ
1 MΩ
VSS3
BAT3
0.1 µF
470 Ω
Figure 10
Caution:
1. The above constants may be changed without notice.
2. The example of connection shown above and the constant do not guarantee proper operation. Perform thorough
evaluation using the actual application to set the constant.
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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