CA3162, CA3162A A/D Converters for 3-Digit Display August 1997 Features Description • Dual Slope A/D Conversion The CA3162E and CA3162AE are I2L monolithic A/D converters that provide a 3 digit multiplexed BCD output. They are used with the CA3161E BCD-to-Seven-Segment Decoder/Driver and a minimum of external parts to implement a complete 3-digit display. The CA3162AE is identical to the CA3162E except for an extended operating temperature range. • Multiplexed BCD Display • Ultra Stable Internal Band Gap Voltage Reference • Capable of Reading 99mV Below Ground with Single Supply • Differential Input • Internal Timing - No External Clock Required • Choice of Low Speed (4Hz) or High Speed (96Hz) Conversion Rate The CA3161E is described in the Display Drivers section of this data book. • “Hold” Inhibits Conversion but Maintains Delay • Overrange Indication - “EEE” for Reading Greater than +999mV, “-” for Reading More Negative than -99mV When Used With CA3161E • Extended Temperature Range Version Available Ordering Information PART NUMBER CA3162E CA3162AE TEMP. RANGE (oC) PKG. NO. PACKAGE 0 to 70 16 Ld PDIP E16.3 -40 to 85 16 Ld PDIP E16.3 Pinout CA3162 (PDIP) TOP VIEW 21 1 16 23 20 2 15 22 NSD 3 14 V+ MSD 4 13 GAIN ADJ LSD 5 12 HOLD/ BYPASS 6 11 HIGH INPUT GND 7 10 LOW INPUT ZERO ADJ 8 9 BCD OUTPUTS DIGIT SELECT OUTPUTS INTEGRATING CAP ZERO ADJ CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 3-5 BCD OUTPUTS File Number 1080.2 CA3162, CA3162A Functional Block Diagram V+ V+ BCD OUTPUTS ZERO ADJ INTEGRATING CAP 8 9 21 20 22 23 V+ 1 2 15 16 14 12 3 CONTROL LOGIC COUNTERS AND MULTIPLEX DIGIT DRIVE 4 DIGIT SELECT OUTPUTS † 5 HIGH INPUT 11 LOW INPUT 10 THRESHOLD DET. V/I CONVERTER REFERENCE CURRENT GENERATOR BAND GAP REFERENCE 13 † MSD = MOST SIGNIFICANT DIGIT NSD = NEXT SIGNIFICANT DIGIT LSD = LEAST SIGNIFICANT DIGIT GAIN ADJ 3-6 ÷2048 ÷96 OSC HOLD/ BYPASS GATES 7 6 GND 4 = MSD 5 = LSD 3 = NSD CONVERSION CONTROL CA3162, CA3162A Absolute Maximum Ratings Thermal Information DC Supply Voltage (Between Pins 7 and 14) . . . . . . . . . . . . . . . +7V Input Voltage (Pin 10 or 11 to Ground). . . . . . . . . . . . . . . . . . . ±15V Thermal Resistance (Typical, Note 1) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC Operating Conditions Temperature Range CA3162E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 75oC CA3162AE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications TA = 25oC, V+ = 5V, Zero Pot Centered, Gain Pot = 2.4kΩ, Unless Otherwise Specified PARAMETER TEST CONDITIONS Operating Supply Voltage Range, V+ Supply Current, I+ 100kΩ to V+ on Pins 3, 4, 5 Input Impedance, ZI MIN TYP MAX UNITS 4.5 5 5.5 V - - 17 mA - 100 - MΩ - -80 - nA Input Bias Current, IIB Pins 10 and 11 Unadjusted Zero Offset V11-V10 = 0V, Read Decoded Output -12 - +12 mV Unadjusted Gain V11-V10 = 900mV, Read Decoded Output 846 - 954 mV Linearity Notes 1 and 2 -1 - +1 Count Slow Mode Pin 6 = Open or GND - 4 - Hz Fast Mode Pin 6 = 5V - 96 - Hz 0.8 1.2 1.6 V Conversion Rate Conversion Control Voltage (Hold Mode) at Pin 6 Common Mode Input Voltage Range, VICR Notes 3, 4 -0.2 - +0.2 V BCD Sink Current at Pins 1, 2, 15, 16 VBCD ≥ 0.5V, at Logic Zero State 0.4 1.6 - mA Digit Select Sink Current at Pins 3, 4, 5 VDIGIT Select = 4V at Logic Zero State 1.6 2.5 - mA Zero Temperature Coefficient VI = 0V, Zero Pot Centered - 10 - µV/oV Gain Temperature Coefficient VI = 900mV, Gain Pot = 2.4kΩ - 0.005 - %/oC NOTES: 1. Apply 0V across V11 to V10 . Adjust zero potentiometer to give 000mV reading. Apply 900mV to input and adjust gain potentiometer to give 900mV reading. 2. Linearity is measured as a difference from a straight line drawn through zero and positive full scale. Limits do not include ±0.5 count bit digitizing error. 3. For applications where low input pin 10 is not operated at pin 7 potential, a return path of not more than 100kΩ resistance must be provided for input bias currents. 4. The common mode input voltage above ground cannot exceed +0.2V if the full input signal range of 999mV is required at pin 11. That is, pin 11 may not operate higher than 1.2V positive with respect to ground or 0.2V negative with respect to ground. If the maximum input signal is less than 999mV, the common mode input voltage may be raised accordingly. 3-7 CA3162, CA3162A Timing Diagram 200mV 12 5 (LSD) PIN NUMBER reference constant current source of opposite polarity is connected. The number of clock counts that elapse before the charge is restored to its original value is a direct measure of the signal induced current. The restoration is sensed by the comparator, which in turn latches the counter. The count is then multiplexed to the BCD outputs. 500mV 4 (MSD) The timing for the CA3162E is supplied by a 786Hz ring oscillator, and the input at pin 6 determines the sampling rate. A 5V input provides a high speed sampling rate (96Hz), and grounding or floating pin 6 provides a low speed (4Hz) sampling rate. When pin 6 is fixed at +1.2V (by placing a 12K resistor between pin 6 and the +5V supply) a “hold” feature is available. While the CA3162E is in the hold mode, sampling continues at 4Hz but the display data are latched to the last reading prior to the application of the 1.2V. Removal of the 1.2V restores continuous display changes. Note, however, that the sampling rate remains at 4Hz. 500mV 3 (NSD) 500mV 2ms/DIV. FIGURE 1. HIGH SPEED MODE Detailed Description The Functional Block Diagram of the CA3162E shows the V/I converter and reference current generator, which is the heart of the system. The V/I converter converts the input voltage applied between pins 10 and 11 to a current that charges the integrating capacitor on pin 12 for a predetermined time interval. At the end of the charging interval, the V/I converter is disconnected from the integrating capacitor, and a band gap NOTE 2 NOTE 1 9 The “EEE” or “---” displays indicate that the range of the system has been exceeded in the positive or negative direction, respectively. Negative voltages to -99mV are displayed with the minus sign in the MSD. The BCD code is 1010 for a negative overrange (---) and 1011 for a positive overrange (EEE). +5V 0.1 µF 0.27µF NORMAL 8 LOW SPEED MODE: V6 = GROUND OR OPEN Figure 1 shows the timing of sampling and digit select pulses for the high speed mode. Note that the basic A/D conversion process requires approximately 5ms in both modes. 12 14 MSD 16 HOLD: V6 = 1.2V NSD a 5 6 f e 4 HIGH SPEED MODE: V6 = 5V e c b g e c d c d 13 CA3161E BCD OUTPUTS 11 a f b g d DIGIT DRIVERS CA3162E a f b g 3 POWER 2N2907, 2N3906 OR EQUIV. COMMON ANODE LED DISPLAYS LSD 12 11 16 6 10 15 2 9 1 1 15 2 7 14 HIGH INPUTS LOW 10 13 GAIN ADJ 7 8 R1 150Ω 3 CA3162E PINS 3, 4, 5 10 kΩ NOTES: 1. The capacitor used here must be a low dielectric absorption type such as a polyester or polystyrene type. 2. This capacitor should be placed as close as possible to the power and ground Pins of the CA3161E. R2 150Ω CA3162E PINS 1, 2, 15, 16 1kΩ 75Ω DIGIT DRIVER BCD SEGMENT DRIVERS FIGURE 2. BASIC DIGITAL READOUT SYSTEM USING THE CA3162E AND THE CA3161E 3-8 R3 150Ω CA3162, CA3162A capacitors and pull-up resistors connected to the MSD, NSD and LSD outputs are there to shorten the digit drive signal thereby providing proper timing for the CD4056B latches. CA3162E Liquid Crystal Display (LCD) Application Figure 3 shows the CA3162E in a typical LCD application. LCDs may be used in favor of LED displays in applications requiring lower power dissipation, such as battery-operated equipment, or when visibility in high-ambient-light conditions is desired. Inverters G1 and G2 are used as an astable multivibrator to provide the AC drive to the LCD backplane. Inverters G3, G4 and G5 are the digit-select inverters and require pull-up resistors to interface the open-collector outputs of the CA3162E to CMOS logic. The BCD outputs of the CA3162E may be connected directly to the corresponding CD4056B inputs (using pull-up resistors). In this arrangement, the CD4056B decodes the negative sign (-) as an “L” and the positive overload indicator (E) as an “H”. Multiplexing of LCD digits is not practical, since LCDs must be driven by an AC signal and the average voltage across each segment is zero. Three CD4056B liquid-crystal decoder/drivers are therefore used. Each CD4056B contains an input latch so that the BCD data for each digit may be latched into the decoder using the inverted digit-select outputs of the CA3162E as strobes. The circuit as shown in Figure 3 using G7, G8 and G9 will decode the negative sign (-) as a negative sign (-), and the positive overload indicator (E) as “H”. The capacitors on the outputs of inverters G3 and G4 filter out the decode spikes on the MSD and NSD signals. The +5V 0.047µF 16 1 G3 0.047µF 6 4 +5V 2 TO MSD OF LCD CD4056B 3 5 7 8 6x 10kΩ 0.27µF ZERO 50kΩ 8 14 12 4 3 9 CA3162E “HOLD” 5 16 15 1 +5V 0.047 µF MSD NSD 16 1 G4 LSD 0.047µF 0.047 µF 23 22 6 4 2 21 TO NSD OF LCD CD4056B 3 20 VIN+ 11 2 VIN- 10 13 4x 7 100kΩ 5 7 8 +5V GAIN 10kΩ G5 16 1 6 +5V 4 G9 G7 2 TO LSD OF LCD CD4056B 3 G1 - G6: CD4049UB HEX INVERTER G7, G8, G9: CD4023B TRIPLE 3 INPUT NAND GATE 5 7 8 TO LCD BACKPLANE G8 15kΩ 100kΩ FIGURE 3. TYPICAL LCD APPLICATION 3-9 0.63µF CA3162, CA3162A CA3162E Common-Cathode, LED Display Application Figure 4 shows the CA3162E connected to a CD4511B decode/driver to operate a common-cathode LED display. Unlike the CA3161E, the CD4511B remains blank for all BCD codes greater than nine. After 999mV the display blanks rather than displaying EEE, as with the CA3161E. When displaying negative voltage, the first digit remains blank, instead of (-), and during a negative or positive overrange the display blanks. The additional logic shown within the dotted area of Figure 4 restores the negative sign (-), allowing the display of negative numbers as low as -99mV. Negative overrange is indicated by a negative sign (-) in the MSD position. The rest of the display is blanked. During a positive overrange, only segment b of the MSD is displayed. One inverter from the CD4049B is used to operate the decimal points. By connecting the inverter input to either the MSD or NSD line either DP1 or DP2 will be displayed. V+ DP1 100kΩ 22kΩ 1/ 3 DP2 1/ CD4049UB 6 CD4049UB CD4012B 1/ 3 CD4049UB 1/ CD4049UB 6 V+ V+ 16 1.8kΩ CD4511B f 15 2 C 1 B 100kΩ 100kΩ V+ 3 LT g 14 4 BL a 13 HP5082-7433 OR EQUIVALENT 1.2kΩ 1.8kΩ 1.2kΩ 5 LE/STROBE b 12 1.8kΩ 100kΩ 100kΩ 6 D c 11 7 A d 10 12 11 10 1.8kΩ 8 GND e 9 f a 9 8 g 7 b c3 1.8kΩ V+ DP1 1 B 100 kΩ 100 kΩ 100 kΩ CA3162E c1 D 16 1 C 15 2 A 3 NSD V+ 14 4 MSD GAIN 13 5 LSD INT 12 HIGH 11 7 GND LOW 10 8 ZERO 3 DP2 c2 4 c 5 dP 6 10kΩ GAIN 6 BUFFERS (1 CD4050B) ZERO 9 V+ 2 d V+ 0.27µF 6 HOLD e INPUT 50kΩ FIGURE 4. TYPICAL COMMON-CATHODE LED APPLICATION 3-10 CA3162, CA3162A Die Characteristics DIE DIMENSIONS: PASSIVATION: 101 mils x 124 mils x 20 mils ±1 mil Type: 3% PSG Thickness: 13kÅ ±2.5kÅ METALLIZATION: Type: Al Thickness: 17.5kÅ ±2.5kÅ Metallization Mask Layout GND ZERO ADJ ZERO ADJ LOW INPUT CA3162, CA3162A HIGH INPUT HOLD/BYPASS INTEGRATING CAP LSD MSD NSD 20 21 23 22 V+ GAIN ADJ All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 3-11