Generic Macro Library Reference Manual Table of Contents Arithmetic Functions ………………………………………………………………. 3 Adders ………………………………………………………………………………….4 G_FADD ………………………………………………………………………….. 4 G_HADD …………….………………………………………………………….… 5 I/O Pins ………………………………………………………………………………. 6 Bidirectional Pin – G_BIDIR …………………………………………………… 7 Input Pin – G_INPUT ……….…………………………………………………. 8 Output Pin – G_OUTPUT ……………………………………………………… 9 G_TRI …………………………………………………………… 10 Logic Gates …………………………………………………..………………………11 AND gates ……………………………………………………………………………..12 2 input AND gates ……………………………………………………………….12 3 input AND gates ……………………………………………………………….13 4 input AND gates ……………………………………………………………….14 OR gates …………………………………………………………………………… 15 2 input OR gates …………………………………………………………….… 15 3 input OR gates ……………………………………………………………… 16 4 input OR gates …………………………………………………………………17 NAND gates ………………………………………………………………………… 18 2 input NAND gates ……………………………………………………………..18 3 input NAND gates ……………………………………………………………..19 4 input NAND gates ……………………………………………………………..20 NOR gates ………………………………………………………………………… 21 2 input NOR gates ……………………………………………………………….21 3 input NOR gates ……………………………………………………………….22 4 input NOR gates ……………………………………………………………….23 BUF, INV, XOR, XNOR ……………………………………………………………...24 Generic Macro Library Reference Manual i Multiplexers ……………………………………………………………………… 25 G_MUX21 …….…….………………………………………………………….26 G_MUX41 …………..………………………………………………………….27 G_MUX81 …………………..………………………………………………….28 Registers ………………………………………………………………………….. 29 D Flip-flops …………………………………………………………………………..30 G_D, G_DC, G_DP ………..……………………………………………… 30 G_DEC, G_DEP ……………………………………………………………….31 JK Flip-flops ………………………………………………………………………….32 G_JK, G_JKC, G_JKP ..……………………………………………………….32 Toggle Flip-flops ….…………………………………………………………………33 G_T, G_TC, G_TP ……………………………………………………………..33 D Latch ……………………………………………………………………………….34 G_LATCH ……………………………………………………………………… 34 SR Latches …………………………………………………………………………..35 G_RS, G_RSC, G_RSP ……………………………………………………….35 Generic Macro Library Reference Manual ii Arithmetic Functions This chapter contains information on the following macros: • Adders Generic Macro Library Reference Manual 3 Adders G_FADD G_FADD A B CI Function: G_FADD : 1-bit full adder. CO SUM Type: Soft. Logic Resources: Macro G_FADD * Z0 : 3 PT PT * Macrocell 2 Output 2 Level 1 C0 : 3 PT Truth Table: A0 data data Input B0 data data CI 0 1 C0 * ** Output SUM A+B A+B+1 * If A+B <2n, C0 = 0. If A+B ≥ 2n, C0 = 1. ** If A+B+1 < 2n, C0 = 0. If A+B+1 ≥ 2n, C0 = 1. Generic Macro Library Reference Manual 4 G_HADD Function: G_HADD : 1-bit half adder. G_HADD A0 B0 Schematic appear on the following page. C0 SUM Type: Soft : G_HADD. Logic Resources: Macro G_FADD * Z0 : 2 PT PT * Macrocell 2 Output 2 Level 1 C0 : 1 PT Truth Table: A0 data Input B0 data CI 0 C0 * Output SUM A+B * If A+B <2n, C0 = 0. If A+B ≥ 2n, C0 = 1. Generic Macro Library Reference Manual 5 I/O Pins This chapter contains information on the following macros: • • • Bidirectional Pin Input Pin Output Pins Generic Macro Library Reference Manual 6 Bidirectional Pin G_BIDIR Function: G_BIDIR : 1-bit bidirectional pin. Type: Hard Truth Table: Do not drive XB when OE =1. OE 0 0 1 Input A x x d XB d Z Z Output XB Z d X d d D = any pattern of 1s and 0s on an input or set of inputs, x = don’t care, X = X (unknown) state, Z = high impedance state, - = appears in output column if a dibirectional pin acts as an input pin. Generic Macro Library Reference Manual 7 Input Pin G_INPUT Function: G_INPUT : 1-bit input pin. Type: Hard Truth Table: Input Output XI Z d d d = any pattern of 1s and 0s on an input or set of inputs, XI = external input pin, Z = output. Generic Macro Library Reference Manual 8 Output Pins G_OUTPUT Function: G_OUTPUT : 1-bit output pin. Type: Hard Truth Table: Input Output A X0 d d d = any pattern of 1s and 0s on an input or set of inputs. Generic Macro Library Reference Manual 9 Tri-state Output Pin G_TRI Function: G_TRI :1-bit tri-state output pin. Type: Hard Truth Table: Input OE 0 1 A x D Output X0 Z d d = any pattern of 1s and 0s on an input or set of inputs, x = don’t care, Z = high impedance state. Generic Macro Library Reference Manual 10 Logic Gates This chapter contains information on logic gate macros. Generic Macro Library Reference Manual 11 AND gates 2AND, 2AND1, 2AND2 G_2AND G_2AND1 G_2AND2 Function: G_2AND, G_2AND1, G_2AND2: 2 input AND gates. Note: Bubble(s) on the input(s) mean inverted input(s). Type: Logic Primitive. Truth Table: Inputs 0 0 0 1 1 0 1 1 2AND 0 0 0 1 2AND1 0 0 1 0 2AND2 1 0 0 0 Generic Macro Library Reference Manual 12 3AND, 3AND1, 3AND2, 3AND3 G_3AND G_3AND1 G_3AND2 G_3AND3 Function: G_3AND, G_3AND1, G_3AND2, G_3AND3: 3 input AND gates. Note: Bubble(s) on the input(s) mean inverted input(s). Type: Logic Primitive. Truth Table: Inputs 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 1 3AND 0 0 0 0 0 0 0 1 3AND1 0 0 0 0 0 0 1 0 3AND2 0 0 0 0 1 0 0 0 3AND3 1 0 0 0 0 0 0 0 Generic Macro Library Reference Manual 13 4AND, 4AND1, 4AND2, 4AND3, 4AND4 G_4AND G_4AND1 G_4AND2 G_4AND3 G_4AND4 Function: G_4AND, G_4AND1, G_4AND2, G_4AND3, G_4AND4: 4 input AND gates. Note: Bubble(s) on the input(s) mean inverted input(s). Type: Logic Primitive. Truth Table: Inputs 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 4AND 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 4AND1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 4AND2 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 4AND3 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Generic Macro Library Reference Manual 4AND4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 OR gates 2OR, 2OR1, 2OR2 G_2OR G_2OR1 G_2OR2 Function: G_2OR, G_2OR1, G_2OR2 : 2 input OR gates. Note: Bubble(s) on the input(s) mean inverted input(s). Type: Logic Primitive Truth Table: Inputs 0 0 0 1 1 0 1 1 2OR 0 1 1 1 2OR1 0 0 1 1 2OR2 1 1 1 0 Generic Macro Library Reference Manual 15 3OR, 3OR1, 3OR2, 3OR3 G_3OR G_3OR1 G_3OR2 G_3OR3 Function: G_3OR, G_3OR1, G_3OR2, G_3OR3: 3 input OR gates. Note: Bubble(s) on the input(s) mean inverted input(s). Type: Logic Primitive Truth Table: Inputs 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 1 3OR 0 1 1 1 1 1 1 1 3OR1 1 0 1 1 1 1 1 1 3OR2 1 1 1 0 1 1 1 1 3OR3 1 1 1 1 1 1 1 0 Generic Macro Library Reference Manual 16 4OR, 4OR1, 4OR2, 4OR3, 4OR4 G_4OR G_4OR1 G_4OR2 G_4OR3 G_4OR4 Function: G_4OR, G_4OR1, G_4OR2, G_4OR3, G_4OR4: 4 input OR gates. Note: Bubble(s) on the input(s) mean inverted input(s). Type: Logic Primitive Truth Table: Inputs 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 4OR 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4OR1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4OR2 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 4OR3 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 Generic Macro Library Reference Manual 4OR4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 17 NAND Gates 2NAND, 2NAND1, 2NAND2 G_2NAND G_2NAND1 G_2NAND2 Function: G_2NAND, G_2NAND1, G_2NAND2: 2 input NAND gates. Note: Bubble(s) on the input(s) mean inverted input(s). Type: Logic Primitive Truth Table: Inputs 0 0 0 1 1 0 1 1 2NAND 1 1 1 0 2NAND1 1 1 0 1 2NAND2 0 1 1 1 Generic Macro Library Reference Manual 18 3NAND, 3NAND1, 3NAND2, 3NAND3 G_3NAND G_3NAND1 G_3NAND2 G_3NAND3 Function: G_3NAND, G_3NAND1, G_3NAND2, G_3NAND3: 3 input NAND gates. Note: Bubble(s) on the input(s) mean inverted input(s). Type: Logic Primitive Truth Table: Inputs 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 1 3NAND 1 1 1 1 1 1 1 0 3NAND1 1 1 1 1 1 1 0 1 3NAND2 1 1 1 1 0 1 1 1 3NAND3 0 1 1 1 1 1 1 1 Generic Macro Library Reference Manual 19 4NAND, 4NAND1, 4NAND2, 4NAND3, 4NAND4 G_4NAND G_4NAND1 G_4NAND2 G_4NAND3 G_4NAND4 Function: G_4NAND, G_4NAND1, G_4NAND2, G_4NAND3, G_4NAND4: 4 input NAND gates. Note: Bubble(s) on the input(s) mean inverted input(s). Type: Logic Primitive Truth Table: Inputs 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 4NAND 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 4NAND1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 4NAND2 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 4NAND3 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 Generic Macro Library Reference Manual 4NAND4 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 20 NOR Gates 2NOR, 2NOR1, 2NOR2 G_2NOR G_2NOR1 G_2NOR2 Function: G_2NOR, G_2NOR1, G_2NOR2: 2 input NOR gates. Note: Bubble(s) on the input(s) mean inverted input(s). Type: Logic Primitive Truth Table: Inputs 0 0 0 1 1 0 1 1 2NOR 1 0 0 0 2NOR1 0 1 0 0 2NOR2 0 0 0 1 Generic Macro Library Reference Manual 21 3NOR, 3NOR1, 3NOR2, 3NOR3 G_3NOR G_3NOR1 G_3NOR2 G_3NOR3 Function: G_3NOR, G_3NOR1, G_3NOR2, G_3NOR3: 3 input NOR gates. Note: Bubble(s) on the input(s) mean inverted input(s). Type: Logic Primitive Truth Table: Inputs 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 1 3NOR 1 0 0 0 0 0 0 0 3NOR1 0 1 0 0 0 0 0 0 3NOR2 0 0 0 1 0 0 0 0 3NOR3 0 0 0 0 0 0 0 1 Generic Macro Library Reference Manual 22 4NOR, 4NOR1, 4NOR2, 4NOR3, 4NOR4 G_4NOR G_4NOR1 G_4NOR2 G_4NOR3 G_4NOR4 Function: G_4NOR, G_4NOR1, G_4NOR2, G_4NOR3, G_4NOR4: 4 input NOR gates. Note: Bubble(s) on the input(s) mean inverted input(s). Type: Logic Primitive Truth Table: Inputs 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 4NOR 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4NOR1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4NOR2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 4NOR3 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Generic Macro Library Reference Manual 4NOR4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 23 BUF, INV, XOR, XNOR G_BUF G_BUFB G_XOR G_INV G_XNOR Function: G_BUF: single input buffer. G_BUFB: single inverted input buffer. G_INV: single input inverter. G_XOR: 2 input exclusive OR gate. G_XNOR: 2 input exclusive NOR gate. Type: Logic Primitive Truth Table: Input 0 1 Inputs 0 0 0 1 1 0 1 1 G_BUF 0 1 XOR 0 1 1 0 G_BUFB 1 0 G_INV 1 0 XNOR 1 0 0 1 Generic Macro Library Reference Manual 24 Multiplexers This chapter contains information on the following macros: • • • 2-to-1 multiplexer 4-to-1 multiplexer 8-to-1 multiplexer Generic Macro Library Reference Manual 25 MUX21 G_MUX21 Function: G_MUX21: 2 input multiplexer with 1 select line. Type: Soft Logic Resources: Macro PT G_MUX21 2 Truth Table: Input S 0 1 Macrocell 1 Output 1 Level 1 Output Z B A Generic Macro Library Reference Manual 26 MUX41 G_MUX41 Function: G_MUX41: 4 input multiplexer with 2 select line. Type: Soft Logic Resources: Macro PT G_MUX41 4 Truth Table: Input S1 S0 0 0 0 1 1 0 1 1 Macrocell 1 Output 1 Level 1 Output Z D C B A Generic Macro Library Reference Manual 27 MUX81 G_MUX81 Function: G_MUX81: 8 input multiplexer with 3 select line. Type: Soft Logic Resources: Macro PT G_MUX81 8 Truth Table: Input S2 S1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Macrocell 2 S0 0 1 0 1 0 1 0 1 Output 1 Level 1 Output Z H G F E D C B A Generic Macro Library Reference Manual 28 Registers This chapter contains information on the following macros: • • • • • D Flip-Flops JK Flip-Flops Toggle Flip-Flops D Latches SR Latches Generic Macro Library Reference Manual 29 D Flip-Flops G_D, G_DC, G_DP G_D G_DC Function: G_D: 1-bit D flip-flop. G_DC: 1-bit D flip-flop with synchronous clear. G_DP: 1-bit D flip-flop with synchronous preset. G_DP Type: Logic Primitive Logic Resources: Macro PT Macrocell Output G_D 1* 1 1 G_DC 1* 1 1 G_DP 2* 1 1 * Add 1 PT per GLB if Product Term Clock is used. Level 1 1 1 Truth Table: D0~D n-1 x d x x Input CLK ↑ ↑ 0 1 C 1 0 0 0 P 1 0 x x Output (Q0~Q n-1 ) G_D G_DC G_DP 0 1 d d d Q0’~Qn’ Q0’~Qn’ Q0’~Qn’ Q0’~Qn’ Q0’~Qn’ Q0’~Qn’ d = any pattern of 1s and 0s in an input or set of inputs, Q0’~Qn’ = previous output of flip-flop or latch, - = not apply, x = don’t care, ↑ = rising clock edge. Generic Macro Library Reference Manual 30 G_DEC, G_DEP G_DEC G_DEP Function: G_DEC: 1-bit D flip-flop with synchronous clear and enable. G_DEP: 1-bit D flip-flop with synchronous preset and enable. Type: Soft Logic Resources: Macro PT Macrocell Output G_DEC 1* 1 1 G_DEP 2* 1 1 * Add 1 PT per GLB if Product Term Clock is used. Level 1 1 Truth Table: D0~D n-1 x d x x Input CLK ↑ ↑ 0 1 C 1 0 0 0 P 1 0 x x Output (Q0~Q n-1 ) G_DEC G_DEP 0 1 d d Q0’~Qn’ Q0’~Qn’ Q0’~Qn’ Q0’~Qn’ d = any pattern of 1s and 0s in an input or set of inputs, Q0’~Qn’ = previous output of flip-flop or latch, x = don’t care, ↑ = rising clock edge. Generic Macro Library Reference Manual 31 JK Flip-Flops G_JK, G_JKC, G_JKP G_JK G_JKC G_JKP Function: G_JK: JK flip-flop. G_JKC: JK flip-flop with synchronous clear. G_JKP: JK flip-flop with synchronous preset. Type: Soft Logic Resources: Macro PT Macrocell Output G_JK 2* 1 1 G_JKC 2* 1 1 G_JKP 2* 1 1 * Add 1 PT per GLB if Product Term Clock is used. Level 1 1 1 Truth Table: Input Output P C J K CLK Q x 1 x x x 0 0 0 0 0 Q0’ ↑ 0 0 0 1 0 ↑ 0 0 1 0 1 ↑ 0 0 1 1 ↑ Q0’ x 0 x x 0 Q0’ x 0 x x 1 Q0’ 1 0 x x 1 ↑ Q0’ = previous output of flip flop, Q0’=inverse of Q0’, X=don’t care, ↑ = rising clock edge Generic Macro Library Reference Manual 32 Toggle Flip-flop G_T, G_TC, G_TP G_T G_TC G_TP Function: G_T: Toggle flip-flop. G_TC: Toggle flip-flop with synchronous clear. G_TP: Toggle flip-flop with synchronous preset. Type: Soft Logic Resources: Macro PT Macrocell Output G_T 3* 1 1 G_TC 3* 1 1 G_TP 3* 1 1 * Add 1 PT per GLB if Product Term Clock is used. Level 1 1 1 Truth Table: Input Output P C T CLK Q 1 x x 1 ↑ 0 1 x 0 ↑ 0 0 0 Q0’ ↑ 0 0 1 ↑ Q0’ x x x 0 Q0’ x x x 1 Q0’ Q0’ = previous output of flip flop, Q0’=inverse of Q0’, X=don’t care, ↑ = rising clock edge Generic Macro Library Reference Manual 33 D Latch G_LATCH G_RS Function: G_LATCH: 1-bit D latch with enable. Type: Hard Logic Resources: Macro PT G_LATCH 3 Truth Table: Input D0~D n-1 E d 1 x 1 Macrocell 1 Output 1 Level 1 Output Q0~Q n-1 d Q0’~Qn’ d = any pattern of 1s and 0s in an input or set of inputs, Q0’~Qn’ = previous output of flip-flop or latch, x = don’t care. Generic Macro Library Reference Manual 34 SR Latches G_RS, G_RSC, G_RSP G_RS G_RSC G_RSP Function: G_RS: simple SR latch. G_RSC: simple SR latch with synchronous clear. G_RSP: simple SR latch with synchronous preset. Type: Soft Logic Resources: Macro PT G_RS 2 G_RSC 2 G_RSP 2 Macrocell 1 1 1 Output 1 1 1 Level 1 1 1 Truth Table: Input Output P C S R Q 0 0 0 0 Q 0 0 0 1 1 0 0 1 0 0 0 0 1 1 1* 1 0 x x 1 0 1 x x 0 * These outputs are not entirely stable. They may not remain when both S and R return to 1. Generic Macro Library Reference Manual 35