HD-6409 ® Datasheet July 29, 2005 CMOS Manchester Encoder-Decoder Features The HD-6409 Manchester Encoder-Decoder (MED) is a high speed, low power device manufactured using self-aligned silicon gate technology. The device is intended for use in serial data communication, and can be operated in either of two modes. In the converter mode, the MED converts Non return-to-Zero code (NRZ) into Manchester code and decodes Manchester code into Nonreturn-to-Zero code. For serial data communication, Manchester code does not have some of the deficiencies inherent in Nonreturn-to-Zero code. For instance, use of the MED on a serial line eliminates DC components, provides clock recovery, and gives a relatively high degree of noise immunity. Because the MED converts the most commonly used code (NRZ) to Manchester code, the advantages of using Manchester code are easily realized in a serial data link. • Converter or Repeater Mode In the Repeater mode, the MED accepts Manchester code input and reconstructs it with a recovered clock. This minimizes the effects of noise on a serial data link. A digital phase lock loop generates the recovered clock. A maximum data rate of 1MHz requires only 50mW of power. Manchester code is used in magnetic tape recording and in fiber optic communication, and generally is used where data accuracy is imperative. Because it frames blocks of data, the HD-6409 easily interfaces to protocol controllers. Ordering Information PACKAGE TEMPERATURE RANGE 1 MEGABIT/SEC PKG. DWG. # PDIP -40°C to +85°C HD3-6409-9 E20.3 SOIC -40°C to +85°C HD9P6409-9 M20.3 SOIC (Pb-free) -40°C to +85°C HD9P6409-9Z (Note) M20.3 SOIC Tape & Reel (Pb-free) -40°C to +85°C HD9P6409-9Z96 (Note) M20.3 FN2951.2 • Independent Manchester Encoder and Decoder Operation • Static to One Megabit/sec Data Rate Guaranteed • Low Bit Error Rate • Digital PLL Clock Recovery • On Chip Oscillator • Low Operating Power: 50mW Typical at +5V • Pb-Free Plus Anneal Available (RoHS Compliant) Pinouts HD-6409 (PDIP, SOIC) TOP VIEW BZI 1 20 VCC BOI 2 19 BOO UDI 3 18 BZO SD/CDS 4 17 SS SDO 5 16 ECLK SRST 6 15 CTS NVM 7 14 MS DCLK 8 13 OX RST 9 12 IX GND 10 11 CO NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1997, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HD-6409 Block Diagram SDO NVM BOI BZI BOO DATA INPUT LOGIC 5-BIT SHIFT REGISTER AND DECODER UDI OUTPUT SELECT LOGIC COMMAND SYNC GENERATOR EDGE DETECTOR BZO CTS SRST RST RESET SD SD/CDS INPUT/ OUTPUT SELECT MANCHESTER ENCODER MS IX OX OSCILLATOR ECLK DCLK COUNTER CIRCUITS CO SS Logic Symbol SS CO SD/CDS 17 11 CLOCK GENERATOR 4 16 ECLK ENCODER MS RST SDO DCLK NVM SRST 2 14 9 12 OX IX 19 18 15 BOO BZO CTS CONTROL 2 1 3 5 8 7 6 13 BOI BZI UDI DECODER FN2951.2 July 29, 2005 HD-6409 Pin Description PIN NUMBER TYPE SYMBOL 1 I BZl Bipolar Zero Input Used in conjunction with pin 2, Bipolar One Input (BOl), to input Manchester II encoded data to the decoder, BZI and BOl are logical complements. When using pin 3, Unipolar Data Input (UDI) for data input, BZI must be held high. 2 I BOl Bipolar One Input Used in conjunction with pin 1, Bipolar Zero Input (BZI), to input Manchester II encoded data to the decoder, BOI and BZI are logical complements. When using pin 3, Unipolar Data Input (UDI) for data input, BOl must be held low. 3 I UDI Unipolar Data Input An alternate to bipolar input (BZl, BOl), Unipolar Data Input (UDl) is used to input Manchester II encoded data to the decoder. When using pin 1 (BZl) and pin 2 (BOl) for data input, UDI must be held low. 4 I/O SD/CDS 5 O SDO Serial Data Out The decoded serial NRZ data is transmitted out synchronously with the decoder clock (DCLK). SDO is forced low when RST is low. 6 O SRST Serial Reset In the converter mode, SRST follows RST. In the repeater mode, when RST goes low, SRST goes low and remains low after RST goes high. SRST goes high only when RST is high, the reset bit is zero, and a valid synchronization sequence is received. 7 O NVM Nonvalid Manchester A low on NVM indicates that the decoder has received invalid Manchester data and present data on Serial Data Out (SDO) is invalid. A high indicates that the sync pulse and data were valid and SDO is valid. NVM is set low by a low on RST, and remains low after RST goes high until valid sync pulse followed by two valid Manchester bits is received. 8 O DCLK Decoder Clock The decoder clock is a 1X clock recovered from BZl and BOl, or UDI to synchronously output received NRZ data (SDO). 9 I RST Reset In the converter mode, a low on RST forces SDO, DCLK, NVM, and SRST low. A high on RST enables SDO and DCLK, and forces SRST high. NVM remains low after RST goes high until a valid sync pulse followed by two Manchester bits is received, after which it goes high. In the repeater mode, RST has the same effect on SDO, DCLK and NVM as in the converter mode. When RST goes low, SRST goes low and remains low after RST goes high. SRST goes high only when RST is high, the reset bit is zero and a valid synchronization sequence is received. 10 I GND Ground Ground NAME DESCRIPTION Serial Data/Command In the converter mode, SD/CDS is an input used to receive serial NRZ data. NRZ data is Data Sync accepted synchronously on the falling edge of encoder clock output (ECLK). In the repeater mode, SD/CDS is an output indicating the status of last valid sync pattern received. A high indicates a command sync and a low indicates a data sync pattern. 11 O CO Clock Output Buffered output of clock input IX. May be used as clock signal for other peripherals. 12 I IX Clock Input IX is the input for an external clock or, if the internal oscillator is used, IX and OX are used for the connection of the crystal. 13 O OX Clock Drive If the internal oscillator is used, OX and IX are used for the connection of the crystal. 14 I MS Mode Select MS must be held low for operation in the converter mode, and high for operation in the repeater mode. 15 I CTS Clear to Send In the converter mode, a high disables the encoder, forcing outputs BOO, BZO high and ECLK low. A high to low transition of CTS initiates transmission of a Command sync pulse. A low on CTS enables BOO, BZO, and ECLK. In the repeater mode, the function of CTS is identical to that of the converter mode with the exception that a transition of CTS does not initiate a synchronization sequence. 16 O ECLK Encoder Clock In the converter mode, ECLK is a 1X clock output used to receive serial NRZ data to SD/CDS. In the repeater mode, ECLK is a 2X clock which is recovered from BZl and BOl data by the digital phase locked loop. 17 I SS Speed Select A logic high on SS sets the data rate at 1/32 times the clock frequency while a low sets the data rate at 1/16 times the clock frequency. 18 O BZO Bipolar Zero Output BZO and its logical complement BOO are the Manchester data outputs of the encoder. The inactive state for these outputs is in the high state. 19 O BOO Bipolar One Out See pin 18. 20 I VCC VCC VCC is the +5V power supply pin. A 0.1µF decoupling capacitor from VCC (pin-20) to GND (pin-10) is recommended. NOTE: (I) Input (O) Output 3 FN2951.2 July 29, 2005 HD-6409 Encoder Operation The encoder uses free running clocks at 1X and 2X the data rate derived from the system clock lX for internal timing. CTS is used to control the encoder outputs, ECLK, BOO and BZO. A free running 1X ECLK is transmitted out of the encoder to drive the external circuits which supply the NRZ data to the MED at pin SD/CDS. A command sync pulse is a 3-bit wide pulse with the first 1 1/2 bits high followed by 1 1/2 bits low. 3 Serial NRZ data is clocked into the encoder at SD/CDS on the high to low transition of ECLK during the command sync pulse. The NRZ data received is encoded into Manchester II data and transmitted out on BOO and BZO following the command sync pulse. 4 Following the synchronization sequence, input data is encoded and transmitted out continuously without parity check or word framing. The length of the data block encoded is defined by CTS. Manchester data out is inverted. A low on CTS enables encoder outputs ECLK, BOO and BZO, while a high on CTS forces BZO, BOO high and holds ECLK low. When CTS goes from high to low 1 , a synchronization sequence is transmitted out on BOO and BZO. A synchronization sequence consists of eight Manchester “0” bits followed by a command sync pulse. 2 CTS 1 ECLK DON’T CARE SD/CDS ‘1’ ‘0’ ‘1’ ‘1’ ‘0’ ‘1’ BZO 2 0 0 0 0 0 0 0 0 3 4 BOO EIGHT “0’s” COMMAND SYNC SYNCHRONIZATION SEQUENCE tCE5 tCE6 FIGURE 1. ENCODER OPERATION Decoder Operation The decoder requires a single clock with a frequency 16X or 32X the desired data rate. The rate is selected on the speed select with SS low producing a 16X clock and high a 32X clock. For long data links the 32X mode should be used as this permits a wider timing jitter margin. The internal operation of the decoder utilizes a free running clock synchronized with incoming data for its clocking. The Manchester II encoded data can be presented to the decoder in either of two ways. The Bipolar One and Bipolar Zero inputs will accept data from differential inputs such as a comparator sensed transformer coupled bus. The Unipolar Data input can only accept noninverted Manchester II encoded data i.e. Bipolar One Out through an inverter to Unipolar Data Input. The decoder continuously monitors this data input for valid sync pattern. Note that while the MED encoder section can generate only a command sync pattern, the decoder can recognize either a command or data sync pattern. A data sync is a logically inverted command sync. 4 There is a three bit delay between UDI, BOl, or BZI input and the decoded NRZ data transmitted out of SDO. Control of the decoder outputs is provided by the RST pin. When RST is low, SDO, DCLK and NVM are forced low. When RST is high, SDO is transmitted out synchronously with the recovered clock DCLK. The NVM output remains low after a low to high transition on RST until a valid sync pattern is received. The decoded data at SDO is in NRZ format. DCLK is provided so that the decoded bits can be shifted into an external register on every high to low transition of this clock. Three bit periods after an invalid Manchester bit is received on UDI, or BOl, NVM goes low synchronously with the questionable data output on SDO. FURTHER, THE DECODER DOES NOT REESTABLISH PROPER DATA DECODING UNTIL ANOTHER SYNC PATTERN IS RECOGNIZED. FN2951.2 July 29, 2005 HD-6409 DCLK UDI COMMAND SYNC 1 0 0 1 0 1 0 1 0 1 0 1 0 SDO RST NVM FIGURE 2. DECODER OPERATION Repeater Operation Manchester Il data can be presented to the repeater in either of two ways. The inputs Bipolar One In and Bipolar Zero In will accept data from differential inputs such as a comparator or sensed transformer coupled bus. The input Unipolar Data In accepts only noninverted Manchester II coded data. The decoder requires a single clock with a frequency 16X or 32X the desired data rate. This clock is selected to 16X with Speed Select low and 32X with Speed Select high. For long data links the 32X mode should be used as this permits a wider timing jitter margin. A low on CTS enables ECLK, BOO, and BZO. In contrast to the converter mode, a transition on CTS does not initiate a synchronization sequence of eight 0’s and a command sync. The repeater mode does recognize a command or data sync pulse. SD/CDS is an output which reflects the state of the most recent sync pulse received, with high indicating a command sync and low indicating a data sync. When RST is low, the outputs SDO, DCLK, and NVM are low, and SRST is set low. SRST remains low after RST goes high and is not reset until a sync pulse and two valid manchester bits are received with the reset bit low. The reset bit is the first data bit after the sync pulse. With RST high, NRZ Data is transmitted out of Serial Data Out synchronously with the 1X DCLK. The inputs UDl, or BOl, BZl are delayed approximately 1/2 bit period and repeated as outputs BOO and BZO. The 2X ECLK is transmitted out of the repeater synchronously with BOO and BZO. INPUT COUNT 1 2 3 4 5 6 7 ECLK SYNC PULSE UDI BZO BOO RST SRST FIGURE 3. REPEATER OPERATION 5 FN2951.2 July 29, 2005 HD-6409 Manchester Code The synchronization advantages of using the HD-6409 and Manchester code are several fold. One is that Manchester is a self clocking code. The clock in serial data communication defines the position of each data cell. Non self clocking codes, as NRZ, often require an extra clock wire or clock track (in magnetic recording). Further, there can be a phase variation between the clock and data track. Crosstalk between the two may be a problem. In Manchester, the serial data stream contains both the clock and the data, with the position of the mid bit transition representing the clock, and the direction of the transition representing data. There is no phase variation between the clock and the data. Nonreturn-to-Zero (NRZ) code represents the binary values logic-O and Iogic-1 with a static level maintained throughout the data cell. In contrast, Manchester code represents data with a level transition in the middle of the data cell. Manchester has bandwidth, error detection, and synchronization advantages over NRZ code. The Manchester II code Bipolar One and Bipolar Zero shown below are logical complements. The direction of the transition indicates the binary value of data. A logic-0 in Bipolar One is defined as a Low to high transition in the middle of the data cell, and a logic-1 as a high to low mid bit transition, Manchester Il is also known as Biphase-L code. A second synchronization advantage is a result of the number of transitions in the data. The decoder resynchronizes on each transition, or at least once every data cell. In contrast, receivers using NRZ, which does not necessarily have transitions, must resynchronize on frame bit transitions, which occur far less often, usually on a character basis. This more frequent resynchronization eliminates the cumulative effect of errors over successive data cells. A final synchronization advantage concerns the HD-6409’s sync pulse used to initiate synchronization. This three bit wide pattern is sufficiently distinct from Manchester data that a false start by the receiver is unlikely. The bandwidth of NRZ is from DC to the clock frequency fc/2, while that of Manchester is from fc/2 to fc. Thus, Manchester can be AC or transformer coupled, which has considerable advantages over DC coupling. Also, the ratio of maximum to minimum frequency of Manchester extends one octave, while the ratio for NRZ is the range of 5-10 octaves. It is much easier to design a narrow band than a wideband amp. Secondly, the mid bit transition in each data cell provides the code with an effective error detection scheme. If noise produces a logic inversion in the data cell such that there is no transition, an error indiction is given, and synchronization must be re-established. This places relatively stringent requirements on the incoming data. BIT PERIOD 1 2 3 4 5 BINARY CODE 0 1 1 0 0 NONRETURN TO ZERO BIPOLAR ONE BIPOLAR ZERO FIGURE 4. MANCHESTER CODE Crystal Oscillator Mode LC Oscillator Mode C1 IX 16MHz C0 R1 X1 C1 = 32pF C0 = CRYSTAL + STRAY X1 = AT CUT PARALLEL RESONANCE FUNDAMENTAL MODE RS (TYP) = 30Ω OX R1 = 15MΩ C1 IX C1 = 20pF C0 = 5pF C1 CO FIGURE 5. CRYSTAL OSCILLATOR MODE 6 C1 – 2C0 C ≈ -------------------------E 2 L OX 1 f O ≈ ----------------------2π LC e C1 FIGURE 6. LC OSCILLATOR MODE FN2951.2 July 29, 2005 HD-6409 Using the 6409 as a Manchester Encoded UART BIPOLAR IN BZI VCC BIPOLAR IN BOI BOO BIPOLAR OUT UDI BZO BIPOLAR OUT SD/CDS SDO ECLK SRST CTS NVM MS DCLK RESET SS CTS OX RST IX GND CO LOAD A CP B CK ‘164 DATA IN ‘273 QH A B CK ‘164 DATA IN ‘273 CK LOAD ‘165 QH SI CK LOAD QH ‘165 PARALLEL DATA IN PARALLEL DATA OUT FIGURE 7. MANCHESTER ENCODER UART 7 FN2951.2 July 29, 2005 HD-6409 Absolute Maximum Ratings Thermal Information Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance (Typical) PDIP Package . . . . . . . . . . . . . . . . . . . . . SOIC Package. . . . . . . . . . . . . . . . . . . . . θJA θJC 75°C/W 100°C/W N/A N/A Storage Temperature Range . . . . . . . . . . . . . . . . . -65°C to +150°C Maximum Junction Temperature Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C Plastic Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C ( Lead Tips Only for Surface Mount Packages) Die Characteristics Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Gates CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . 50ns Max Sync. Transition Span (t2) . . . . . . . . . 1.5 DBP Typical, (Notes 1, 2) Short Data Transition Span (t4) . . . . . 0.5DBP Typical, (Notes 1, 2) Long Data Transition Span (t5). . . . . . 1.0DBP Typical, (Notes 1, 2) Zero Crossing Tolerance (tCD5). . . . . . . . . . . . . . . . . . . . . . (Note 3) NOTES: 1. DBP-Data Bit Period, Clock Rate = 16X, one DBP = 16 Clock Cycles; Clock Rate = 32X, one DBP = 32 Clock Cycles. 2. The input conditions specified are nominal values, the actual input waveforms transition spans may vary by ±2 IX clock cycles (16X mode) or ±6 IX clock cycles (32X mode). 3. The maximum zero crossing tolerance is ±2 IX clock cycles (16X mode) or ±6 IX clock cycles (32 mode) from the nominal. DC Electrical Specifications VCC = 5.0V ± 10%, TA = -40°C to +85°C (HD-6409-9) SYMBOL PARAMETER MIN MAX UNITS (NOTE 1) TEST CONDITIONS VIH Logical “1” Input Voltage 70% VCC - V VCC = 4.5V VIL Logical “0” Input Voltage - 20% VCC V VCC = 4.5V VIHR Logic “1” Input Voltage (Reset) VCC -0.5 - V VCC = 5.5V VILR Logic “0” Input Voltage (Reset) - GND +0.5 V VCC = 4.5V VIHC Logical “1” Input Voltage (Clock) VCC -0.5 - V VCC = 5.5V VILC Logical “0” Input Voltage (Clock) - GND +0.5 V VCC = 4.5V II Input Leakage Current (Except IX) -1.0 +1.0 µA VIN = VCC or GND, VCC = 5.5V II Input Leakage Current (IX) -20 +20 µA VIN = VCC or GND, VCC = 5.5V IO I/O Leakage Current -10 +10 µA VOUT = VCC or GND, VCC = 5.5V VOH Output HIGH Voltage (All Except OX) VCC -0.4 - V IOH = -2.0mA, VCC = 4.5V (Note 2) VOL Output LOW Voltage (All Except OX) - 0.4 V IOL = +2.0mA, VCC = 4.5V (Note 2) ICCSB Standby Power Supply Current - 100 µA VIN = VCC or GND, VCC = 5.5V, Outputs Open ICCOP Operating Power Supply Current - 18.0 mA f = 16.0MHz, VIN = VCC or GND VCC = 5.5V, CL = 50pF Functional Test - - - FT (Note 1) NOTES: 1. Tested as follows: f = 16MHz, VIH = 70% VCC, VIL = 20% VCC, VOH ≥ VCC/2, and VOL ≤ VCC/2, VCC = 4.5V and 5.5V. 2. Interchanging of force and sense conditions is permitted 8 FN2951.2 July 29, 2005 HD-6409 Capacitance TA = +25°C, Frequency = 1MHz SYMBOL CIN COUT PARAMETER TYP UNITS Input Capacitance 10 pF Output Capacitance 12 pF TEST CONDITIONS All measurements are referenced to device GND AC Electrical Specifications VCC = 5.0V ±10%, TA = -40°C to +85°C (HD-6409-9) SYMBOL PARAMETER fC Clock Frequency tC Clock Period t1 Bipolar Pulse Width t3 One-Zero Overlap MIN MAX UNITS (NOTE 1) TEST CONDITIONS - 16 MHz - 1/fC - sec - tC+10 - ns - - tC-10 ns - tCH Clock High Time 20 - ns f = 16.0MHz tCL Clock Low Time 20 - ns f = 16.0MHz tCE1 Serial Data Setup Time 120 - ns - tCE2 Serial Data Hold Time 0 - ns - tCD2 DCLK to SDO, NVM - 40 ns - ECLK to BZO - 40 ns - tr Output Rise Time (All except Clock) - 50 ns From 1.0V to 3.5V, CL = 50pF, Note 2 tf Output Fall Time (All except Clock) - 50 ns From 3.5V to 1.0V, CL = 50pF, Note 2 tr Clock Output Rise Time - 11 ns From 1.0V to 3.5V, CL = 20pF, Note 2 tf Clock Output Fall Time - 11 ns From 3.5V to 1.0V, CL = 20pF, Note 2 tR2 tCE3 ECLK to BZO, BOO 0.5 1.0 DBP Notes 2, 3 tCE4 CTS Low to BZO, BOO Enabled 0.5 1.5 DBP Notes 2, 3 tCE5 CTS Low to ECLK Enabled 10.5 11.5 DBP Notes 2, 3 tCE6 CTS High to ECLK Disabled - 1.0 DBP Notes 2, 3 tCE7 CTS High to BZO, BOO Disabled 1.5 2.5 DBP Notes 2, 3 tCD1 UDI to SDO, NVM 2.5 3.0 DBP Notes 2, 3 tCD3 RST Low to CDLK, SDO, NVM Low 0.5 1.5 DBP Notes 2, 3 tCD4 RST High to DCLK, Enabled 0.5 1.5 DBP Notes 2, 3 tR1 UDI to BZO, BOO 0.5 1.0 DBP Notes 2, 3 tR3 UDI to SDO, NVM 2.5 3.0 DBP Notes 2, 3 NOTES: 1. AC testing as follows: f = 4.0MHz, VIH = 70% VCC, VIL = 20% VCC, Speed Select = 16X, VOH ≥ VCC/2, VOL ≤ VCC/2, VCC = 4.5V and 5.5V. Input rise and fall times driven at 1ns/V, Output load = 50pF. 2. Guaranteed via characteristics at initial device design and after major process and/or design changes, not tested. 3. DBP-Data Bit Period, Clock Rate = 16X, one DBP = 16 Clock Cycles; Clock Rate = 32X, one DBP = 32 Clock Cycles. 9 FN2951.2 July 29, 2005 HD-6409 Timing Waveforms NOTE: UDI = 0, FOR NEXT DIAGRAMS BIT PERIOD BOI BIT PERIOD BIT PERIOD T1 T2 T3 T3 BZI T1 T2 COMMAND SYNC T1 BOI T2 T3 T3 T1 BZI DATA SYNC T2 T1 T1 BOI T3 BZI T3 T3 T3 T3 T1 T5 T4 T5 ONE T4 ZERO ONE NOTE: BOI = 0, BZI = 1 FOR NEXT DIAGRAMS T2 UDI T2 COMMAND SYNC T2 UDI T2 DATA SYNC T4 UDI T5 ONE T5 T4 ZERO ONE T4 ONE FIGURE 8. tC tCL tr 10% 90% 1.0V tCH tf tr 3.5V tf FIGURE 9. CLOCK TIMING 10 FIGURE 10. OUTPUT WAVEFORM FN2951.2 July 29, 2005 HD-6409 Timing Waveforms (Continued) ECLK tCE2 tCE1 SD/CDS tCE3 BZO BOO FIGURE 11. ENCODER TIMING CTS CTS BZO BOO tCE6 ECLK tCE7 tCE4 BZO tCE5 BOO ECLK FIGURE 12. ENCODER TIMING FIGURE 13. ENCODER TIMING DCLK tCD5 UDI MANCHESTER MANCHESTER MANCHESTER MANCHESTER LOGIC-1 LOGIC-0 LOGIC-0 LOGIC-1 tCD1 tCD2 SDO NRZ LOGIC-1 tCD2 NVM NOTE: Manchester Data-In is not synchronous with Decoder Clock. Decoder Clock is synchronous with decoded NRZ out of SDO. FIGURE 14. DECODER TIMING 50% RST RST tCD3 DCLK, SDO, NVM tCD4 50% FIGURE 15. DECODER TIMING 11 50% DCLK FIGURE 16. DECODER TIMING FN2951.2 July 29, 2005 HD-6409 Timing Waveforms (Continued) UDI MANCHESTER ‘1’ MANCHESTER ‘0’ MANCHESTER ‘0’ MANCHESTER ‘1’ ECLK tR2 tR1 tR2 BZO MANCHESTER ‘1’ MANCHESTER ‘0’ MANCHESTER ‘0’ tR3 SDO tR3 NVM FIGURE 17. REPEATER TIMING Test Load Circuit DUT CL (NOTE) NOTE: INCLUDES STRAY AND JIG CAPACITANCE FIGURE 18. TEST LOAD CIRCUIT All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12 FN2951.2 July 29, 2005