INTERSIL HFA3983IV

HFA3983
TM
Data Sheet
March 2000
File Number
4635.4
2.4GHz Power Amplifier and Detector
Features
The HFA3983 is a 2.4GHz monolithic
SiGe Power Amplifier designed to
operate in the ISM Band. It features two
low voltage single supply stages.
Cascaded, they deliver a 18dBm (Typ.)
of an output power for the typical DSSS signal (ACPR,
1st Side Lobe < -30dBc, 2nd Side Lobe < -50dBc).
• Single Supply . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 3.6V
In addition, the device includes a 2.4GHz detector which is
accurate over a 15dB of dynamic range with (±)1dB.
Therefore, an accurate ALC function can be implemented.
• Output Power . . . . . . . . . . . 18dBm (Typ) at ACPR, DSSS,
1st Side Lobe < -30dBc, 2nd Side Lobe < -50dBc
• Power Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . .30dB (Typ.)
• Detector Linear Input Power Range . . . . . . . . . . . . . .15dB
• Detector Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1.0dB
Applications
• EEE802.11 1 and 2Mbps Standard
The HFA3983 is housed in a 28 lead exposed paddle
EPTSSOP package well suited for PCMCIA board
applications.
• Systems Targeting IEEE802.11, 11Mbps Standard
Simplified Block Diagram
• PCMCIA Wireless Transceivers
• Wireless Local Area Networks
DS_VCC
• ISM Systems Including Automatic Level Control (ALC)
• TDMA Packet Protocol Radios
Ordering Information
PART NUMBER
RF_IN
RF_OUT
TEMP. RANGE
(oC)
PACKAGE
PKG. NO.
HFA3983IV
-40 to 85
28 Ld EPTSSOP M28.173A
HFA3983IV96
-40 to 85
Tape and Reel
PEAK DETECTOR
Pinout
BIAS
HFA3983
(EPTSSOP)
TOP VIEW
LOG
4-1
GND
1
28
VCC
VCC
2
27
GND
PE
3
26
DET_VOUT
GND
4
25
GND
VCC
5
24
GND
OS_REXT
6
23
GND
DS_REXT
7
22
RF_IN
DS_VCC
8
21
GND
GND
9
20
GND
19
GND
18
GND
17
GND
16
GND
15
GND
GND
10
RF_OUT
11
GND
12
GND
13
GND
14
PACKAGE PINOUT SUBJECT TO CHANGE
DET_VOUT
DS_REXT
PE
OS_REXT
INDEX AREA
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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PRISM is a registered trademark of Intersil Corporation. PRISM logo is a trademark of Intersil Corporation.
Further information is attainable upon NDA Agreement. NDA available on CD ROM or by contacting [email protected]
HFA3983
Pin Descriptions
PIN NUMBER
NAME
DESCRIPTION
1
GND
DC and RF Ground.
2
VCC
Power supply.
3
PE
4
GND
DC and RF Ground.
5
VCC
Power supply.
6
OS_REXT
Output stage bias resistor, biasing scheme independent of absolute temperature.
7
DS_REXT
Driver stage bias resistor, biasing scheme independent of absolute temperature.
8
DS_VCC
Driver stage power supply.
9, 10
GND
11
RF_OUT
12, 13, 14, 15, 16,
17, 18, 19, 20, 21
GND
22
RF_IN
23, 24, 25
GND
26
DET_VOUT
27
GND
DC and RF Ground.
28
VCC
Power supply.
Digital input control pin to enable the operation of the Power Amplifier. Enable logic level is High.
DC and RF Ground.
RF Output of the Power Amplifier.
DC and RF Ground.
RF Input of the Power Amplifier.
DC and RF Ground.
Detector output.
As part of the Prism II WLAN chip set, the HFA3983 works
seamlessly with the chip set components to give you a highly
integrated, cost effective 11Mb/s WLAN solution in the 2.4 to
2.5GHz ISM band. The HFA3983 is fabricated in the fastest
SiGe BiCMOS process available, allowing superior RF
performance, normally found only in GaAs ICs. Cost
effective functions, normally requiring external components,
are integrated into one IC. The HFA3983 integrates the
following functions in one compact 28 pin EPTSSOP:
Two Stage, 30dB Gain RFPA,
Logarithmic power detect function (15dB Dynamic Range),
CMOS level compatible Power Up/Down function,
Single Supply, 2.7V to 3.6V Operation.
The HFA3983 contains a highly linear RFPA designed to
deliver 18dBm and meet an ACPR specification of -30dBc in
the 2.4 to 2.5GHz ISM band. The performance of this two
stage RFPA can be optimized by adjusting the bias current in
each stage with a dedicated resistor. No external positive or
negative power supplies are required to set the bias
currents. The on chip bias network provides the optimum
bias current temperature compensation when low TC
external resistors are used. To get the best performance
from the HFA3983, the output stage matching network can
be tailored using external components.
The HFA3983 power detect function provides a DC output
voltage that is proportional to the logarithm of the output
power. For an output power of 18dBm, the detector is
accurate to within a dB. The slope of the detector output
4-2
voltage is 100mV/dB over a 15dB dynamic range. A simple
application of the detector is to provide in-line monitoring of
the output power using a DC voltmeter. No longer is a power
meter or spectrum analyzer required. A more value added
application would use the HFA3861 Baseband Processor to
dynamically monitor the HFA3983 output power and to
control transmit power by adjusting the AGC of the HFA3783
IF Quadrature Modem to provide the best possible error free
data transfer rate for any given environment. Closed loop
power control is very important feature which compensates
for variability in the transmit chain (radio to radio, channel to
channel, over temperature...).
The HFA3983 power up/down feature integrates the power
down capability onto the IC and requires no external
components, thus freeing up board space and reducing
external component count and cost. When the CMOS
compatible PE (power enable) pin is driven low, the total
supply current drops to under 200µA in, typically, 230nS.
When the PE pin is driven high, the full HFA3983 output
power is available in a few hundred nanoseconds.
In summary, the HFA3983 RFPA provides a highly cost
effective solution for the PA function by integrating many
features that would require significant development time,
drive up the total bill of materials cost and consume precious
board space. It interfaces seamlessly with the other Prism II
ICs to provide a highly integrated, cost effective 11Mb/s
WLAN solution in the 2.4 to 2.5GHz ISM band.
HFA3983
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4V
Voltage on Any Other Pin. . . . . . . . . . . . . . . . . . . -0.3 to VCC +0.3V
VCC to VCC Decouple . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +0.3V
Any GND to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +0.3V
Thermal Resistance (Typical, Note 1)
θJC (oC/W)
EPTSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . .
15
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
Moisture Sensitive Level (See Tech Brief 363) . . . . . . . . 72 Hrs (L4)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to 85oC
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 3.6V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJC is measured with the component mounted on an evaluation PC board in free air with the exposed paddle soldered to an infinite heatsink.
General DC Electrical Specifications
TEMP.
(oC)
MIN
TYP
MAX
UNITS
Supply Voltage
Full
2.7
-
3.6
V
Total Power Amplifier Supply Current at 3.3V, 18dBm Output
25
-
180
-
mA
RF Detector Supply Current
25
-
-
5
mA
Power Down Supply Current
Full
-
200
-
µA
Power Up/ Down Speed
Full
-
230
-
ns
CMOS Low Level Input Voltage
Full
-
-
0.3*VDD
V
CMOS High Level Input Voltage (VDD = 3.3V)
Full
0.7*VDD
-
3.6
V
CMOS Threshold Voltage
Full
-
0.5*VDD
-
V
CMOS High or Low Level Input Current
Full
-10
-
+10
µA
PARAMETER
Power Amplifier AC Electrical Specifications
VCC = 3.3V, f = 2.45GHz, Unless Otherwise Specified. Typical Application Circuit
(external input and output matching networks) has been used.
TEMP.
(oC)
MIN
TYP
MAX
UNITS
RF Frequency Range
Full
2400
-
2500
MHz
Power/Voltage Gain
Full
28
30
32
dB
Noise Figure
Full
-
-
7
dB
Input 50Ω VSWR
25
-
-
2.00:1
-
3.00:1
-
PARAMETER
TEST CONDITIONS
Output 50Ω VSWR
Output matching network
optimized for P1dB
compression
25
-
-
Output Power
ACPR, DSSS,
1st Side Lobe <-30dBc,
2nd Side Lobe <-50dBc
Full
17
18
Output Stability VSWR
Output Spurs Less than
-60dBc
Full
-
-
10:1
-
Output Load Mismatch
(Note 2)
Full
-
-
10:1
-
NOTE:
2. Devices sustain no damage when subjected to a mismatch of maximum 10:1.
4-3
dBm
HFA3983
Peak Detector AC Electrical Specifications
TEST CONDITIONS
TEMP.
(oC)
MIN
TYP
MAX
UNITS
RF Output Detector Response Time
External Capacitor, C = 5pF
Full
-
0.1
1
µs
RF Output Detector Voltage Range
Load > 1M
Full
0
-
1.5
V
RF Output Detector Linearity
Over Linear Range
Full
-0.5
-
+0.5
dB/V
RF Output Detector Accuracy
600mVDC Output
Full
-1
-
+1
dB
RF Output Detector Slope
Over Linear Range
Full
-
10
-
dB/V
PARAMETER
HFA3983EVAL Board Schematic
TYPICAL APPLICATION EXAMPLE
L1
BLM31P5005
3.3V
P1
C2
0.1µF
P2
VCC
VCC
C1
4.7µF
C4
1000pF
C5
1000pF
D1
DL4001
R3
10Ω
VCC
R6
100kΩ
C8
1000pF
R2
10Ω
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
DETOUT
PE
C6
1000pF
3.74kΩ R
4
R5
C7
1000pF
3.74kΩ
L2
2.2nH
L3
BLM10A1215
R1
1kΩ
C3
270pF
RFIN (50Ω)
C12
7pF
L6
4.7nH
RFOUT (50Ω)
C10
2.7pF
L5
6.8nH
V CC
C9
0.1µF
4-4
L4
BLM10A1215
C11
1000pF
C13
1pF
HFA3983
Typical Performance Curves
0
INPUT RETURN LOSS (dB)
INPUT RETURN LOSS (dB)
0
-12
-15
3.6V
-12
-15
85oC
-40oC
2.7V
25oC
-30
2.0
2.4
2.5
-30
2.0
3.0
2.4
FIGURE 1. INPUT RETURN LOSS OVER VOLTAGE
0
INPUT RETURN LOSS (dB)
-6
2.7V
-8
-40oC
-5
-8
25oC
3.6V
-10
2.0
2.4
85oC
2.5
-10
2.0
3.0
2.4
2.5
3.0
FREQUENCY (GHz)
FREQUENCY (GHz)
FIGURE 3. OUTPUT RETURN LOSS OVER VOLTAGE
FIGURE 4. OUTPUT RETURN LOSS OVER TEMPERATURE
34
34
3.6V
30
-40oC
30
2.7V
28
LINEAR GAIN (dB)
LINEAR GAIN (dB)
3.0
FIGURE 2. INPUT RETURN LOSS OVER TEMPERATURE
0
OUTPUT RETURN LOSS (dB)
2.5
FREQUENCY (GHz)
FREQUENCY (GHz)
14
2.0
2.4
2.5
FREQUENCY (GHz)
FIGURE 5. LINEAR GAIN OVER VOLTAGE
4-5
3.0
25oC
28
26
85oC
14
2.0
2.4
2.5
FREQUENCY (GHz)
FIGURE 6. LINEAR GAIN OVER TEMPERATURE
3.0
HFA3983
1
3.6V
2
2.7V
3.6V
2.7V
-25
-11
-5
0
85oC
1
2
25oC
-40oC
85oC
25oC
-40oC
-25
-11
INPUT POWER (dBm)
2dB/DIV.
0
OUTPUT POWER (dBm) COMPRESSION (dBm)
(Continued)
2dB/DIV.
OUTPUT POWER (dBm) COMPRESSION (dBm)
Typical Performance Curves
-5
INPUT POWER (dBm)
FIGURE 7. GAIN COMPRESSION OVER VOLTAGE
FIGURE 8. GAIN COMPRESSION OVER TEMPERATURE
-40oC
10dB/DIV.
10dB/DIV.
2.7V
3V
3.3V
3.6V
25oC
85oC
CENTER FREQUENCY 2450MHz
SPAN 50MHz
FIGURE 10. DSSS OUTPUT SIGNAL OVER TEMPERATURE
0.9
1
0.8
0.9
0.7
0.8
DETECTOR OUTPUT (V)
DETECTOR OUTPUT (V)
FIGURE 9. DSSS OUTPUT SIGNAL OVER VOLTAGE
0.6
0.5
0.4
0.3
2.7V
0.2
0.7
0.6
85oC
0.5
25oC
-40oC
0.4
0.3
0.2
3.6V
0.1
0
CENTER FREQUENCY 2450MHz
INPUT POWER -2dBm
SPAN 50MHz
INPUT POWER -2dBm
0.1
13
14
15
16
17
18
OUTPUT POWER (dBm)
19
FIGURE 11. DETECTOR OUTPUT OVER VOLTAGE
4-6
20
0
13
14
15
16
17
18
OUTPUT POWER (dBm)
19
20
FIGURE 12. DETECTOR OUTPUT OVER TEMPERATURE
HFA3983
Thin Shrink Small Outline Exposed Pad Plastic Packages (EPTSSOP)
M28.173A
N
28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
E
0.25(0.010) M
E1
GAUGE
PLANE
-B1
2
3
L
TOP VIEW
0.05(0.002)
-A-
A
D
α
A2
c
e
A1
b
0.10(0.004) M
2
0.25
0.010
SEATING PLANE
-C-
1
B M
0.10(0.004)
C A M
B S
3
P1
N
P
BOTTOM VIEW
SYMBOL
A
A1
A2
b
c
D
E1
e
E
L
N
INCHES
MIN
MAX
0.047
0.002
0.006
0.031
0.051
0.0075
0.0118
0.0035
0.0079
0.378
0.386
0.169
0.177
0.026 BSC
0.246
0.256
0.0177
0.0295
28
0o
8o
0.138
0.118
MILLIMETERS
MIN
MAX
1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.09
0.20
9.60
9.80
4.30
4.50
0.65 BSC
6.25
6.50
0.45
0.75
28
0o
8o
3.50
3.0
NOTES
9
3
4
6
7
α
P
11
P1
11
NOTES:
Rev. 1 6/99
1. These package dimensions are within allowable dimensions
of JEDEC MO-153-AET, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or
gate burrs. Mold flash, protrusion and gate burrs shall not
exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed
0.15mm (0.006 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total
in excess of “b” dimension at maximum material condition.
Minimum space between protrusion and adjacent lead is
0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
11. Dimensions “P” and “P1” are thermal and/or electrical enhanced variations. Values shown are maximum size of exposed pad within lead count and body size.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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