L DESIGN FEATURES Space-Saving, Dual Output DC/DC Converter Yields Plus/Minus Voltage Outputs with (Optional) I2C Programming by Mathew Wich Introduction with on-chip OTP (One-Time-Programming) memory. The input supply range is 2.55V to 5.5V and switch current limits are 350mA and 600mA for the boost and inverting switches, respectively. In addition, the LT3582 features power up sequencing with ramping from ground to regulation, power down discharging, positive output disconnect and soft-start. There are many applications that require both positive and negative DC voltages generated from a single input supply. The LT3582 is a highly integrated dual switching regulator that produces positive and negative voltages for AMOLEDs, CCDs, op amps, and general ±5V and ±12V supplies. The LT3582 uses a novel control scheme resulting in low output voltage ripple and high conversion efficiency over a wide load current range. The total solution size is very small due to the tiny 3mm × 3mm 16-pin QFN package, integrated feedback resistors, integrated loop compensation networks and the single-inductor negative output topology (see Figure 1). The LT3582-5 and LT3582-12 are factory configured for accurate ±5V and ±12V outputs respectively, making it easy to squeeze a high performance solution into a small space. For other voltage combinations, the LT3582 offers I2C digitally programmable outputs of 3.2V to 12.775V and –1.2V to –13.95V that can be made permanent D1 L1 6.8µH The LT3582 series uses integrated feedback resistors to select the output voltages. The LT3582-5 and LT358212 are pre-configured at the factory for ±5V and ±12V outputs with ±1.5% accuracy or better. The LT3582 allows other output voltages to be configured using the I2C interface. There are nine bits to configure the positive output voltage from 3.2V to 12.775V in 25mV steps and another eight bits to configure the negative output voltage from –1.2V to –13.95V in 50mV steps. Default settings can be stored SWP I2C INTERFACE OPTIONAL ON LT3582-12 REG0/OTP0 = B0h REG1/OTP1 = D8h REG2/OTP2 = 03h C4 1µF CAPP SDA VOUTP SCL VPP CA C1 4.7µF CAPP VOUTN RAMPP RAMPN C5 10nF D1-D2: DIODES INC. B0540WS-7 L1-L2: COILCRAFT XPL2010-682 C1: 4.7µF, 6.3V, X5R, 0805 The LT3582 is among several novel parts from Linear Technology that modulate peak switch current and switch off time to reduce ripple and improve light load efficiency (also see the LT3494, LT3495, LT8410 and VPOS 12V 80mA VOUTP VOUTN 85 L2 6.8µH D2 LT3582 C2 4.7µF Great Performance Includes Low Ripple and High Efficiency Across the Load Range 200 65 150 55 100 45 35 C2: 4.7µF, 16V, X5R, 0805 C3: 1s 4.7µF OR 2s 4.7µF OR 10µF 16V, X5R, 0805 300 250 75 50 C3 C6 10nF 350 POWER LOSS (mW) GND VNEG –12V 85mA INPUT 4.5V TO 5.5V VIN SWN in One-Time-Programmable memory and, if left unlocked, the voltages can be subsequently changed on the fly using the I2C interface. 95 SHDN EFFICIENCY (%) SWN Figure 1. Dual output supplies in a small board footprint Accurate Output Voltages without External Feedback Resistors 0.1 1 10 LOAD CURRENT (mA) 0 100 C4: 1µF, 16V, X5R, 0603 C5-C6: 10nF, 0603 Figure 2. ±12V supplies from a single 5V input 22 Linear Technology Magazine • June 2009 DESIGN FEATURES L VSWP 5V/DIV VSWP 5V/DIV VSWP 5V/DIV VVOUTP 10mV/DIV AC COUPLED VVOUTP 10mV/DIV AC COUPLED VVOUTP 10mV/DIV AC COUPLED IL2 0.2A/DIV IL2 0.2A/DIV IL2 0.2A/DIV 2µs/DIV 5µs/DIV Figure 3. Switching waveforms at 1mA load for the boost application shown in Figure 2 200ns/DIV Figure 4. Switching waveforms at 10mA load for the boost application shown in Figure 2 Figure 5. Switching waveforms at 100mA load for the boost application shown in Figure 2 RAMPP VRAMPP 0.5V/DIV VRAMPN 0.5V/DIV RAMPN L1 SWP D1 VVOUTP 5V/DIV CAPP LT3582 SERIES VOUTP C1 VVOUTN 5V/DIV C2 VIN DISCONNECT CONTROL C3 LOAD 5ms/DIV Figure 6. Power-Up Sequencing (VOUTP followed by VOUTN) LT8415). Under light load conditions, the LT3582 chooses an optimum combination of frequency and peak switch current to improve efficiency while moderating the output ripple. Figures 3–5 show how the frequency and peak inductor current vary from light to heavy loads. At very light loads (typically < 1mA), peak switching currents are dramatically reduced to further reduce ripple when frequencies are in the audio band. CAPP 2V/DIV VOUTP 2V/DIV VRAMPP 0.2V/DIV IL2 0.2A/DIV 1ms/DIV Figure 8. VOUTP soft-start ramping from ground Linear Technology Magazine • June 2009 Figure 7. Output disconnect PMOS Adjustable Power-Up Sequencing and Soft-Start Options The LT3582 has digitally configurable power-up sequencing that forces the outputs to power up in one of four ways: qVOUTP ramps up first, followed by VOUTN (shown in figure 6) qVOUTN ramps up first, followed by VOUTP qboth outputs ramp up simultaneously qboth outputs are disabled The LT3582-5 and LT3582-12 are factory configured for both outputs to ramp up simultaneously. The power-up ramp rates of the output voltages are also adjustable. Slowly ramping the outputs (also known as soft-start) reduces what would otherwise be high peak switching currents during start-up. Without soft-start, high start-up current is inherent in switching regulators due to VOUT being far from its final value. The regulator tries to charge the output capacitors as quickly as possible, which results in large peak currents. The output voltage ramp rates are proportional to the ramp rates of the RAMPP and RAMPN pin voltages. Upon chip enable, a programmable current (1µA, 2µA, 4µA or 8µA) linearly charges capacitors (typically about 10nF) connected to the RAMPP and RAMPN pins. By varying the capacitor sizes or charging currents, a wide range of output voltage ramp rates can be accommodated. VRAMPN 1V/DIV VRAMPP 1V/DIV VVOUTP 5V/DIV VVOUTN 5V/DIV 5ms/DIV Figure 9. Power-down discharge waveforms 23 L DESIGN FEATURES VIN SWP Q S Q R VARIABLE DELAY VARIABLE DELAY S Q R Q CAPP CAPP VOUTP DISCONNECT CONTROL – IPEAK TOFF CONTROL – OTP 2V OTP ADJUST – + + VCP – + + – FBN VCN GND – IPEAK TOFF CONTROL + VOUTN OTP + + + – SWN + SWN FBP 0.80V CHIP ENABLE SHDN 222k VIN VPP 0.80V SCL VIN VOUTP CAPP SERIAL INTERFACE, LOGIC AND OTP SDA RAMPN OUTPUT SEQUENCING BY OTP 2V OTP ADJUST + – 0.75V + – FBN CA FBP VOUTN 50mV OUTPUT SEQUENCING RAMPP Figure 10. LT3582 block diagram Output Disconnect and Improved Efficiency The LT3582 series has a PMOS output disconnect switch connected between CAPP and VOUTP (see Figure 7). During normal operation the switch is closed and current is limited to about 155mA to help protect against output shorts. During shutdown, the PMOS switch is open providing up to 5V–5.5V of isolation between CAPP and VOUTP. In most cases this allows VOUTP to discharge to ground. In normal operation, the output disconnect switch represents ~1.4Ω of resistance in series with the output leading to a 1%–2% efficiency loss under heavy load conditions. The CAPP pin can be externally shorted to the VOUTP pin to eliminate the power loss in the switch and improve efficiency. 24 Unique Ability to Ramp Output Up From Ground Smart control of the output disconnect PMOS also gives the LT3582 the unique ability to generate a smooth VOUTP voltage ramp starting from ground and continuing all the way up to regulation (see Figures 6 and 8). This ability is not possible with typical boost converters because the current path from VIN through the inductor (L1) and Schottky diode (D1) to the output prevents it from starting at 0V (see Figure 7). The disconnect control circuitry in the LT3582 allows VOUTP to discharge to ground when disabled. Once enabled, the gate of the output disconnect PMOS is precisely controlled such that VOUTP rises smoothly from ground up to regulation where the PMOS is fully turned on to reduce power losses. Power Down Discharge Assist The power down discharge feature assists in discharging the outputs after shutdown (see Figure 9). This option is factory enabled on the LT3582-5 and LT3582-12 and can be enabled through the I2C interface in conjunction with the “both together” power-up setting on the LT3582. Upon SHDN falling and when power-down discharge is enabled, internal transistors activate to assist in discharging the outputs toward ground. After both outputs are within ~0.5V to ~1.5V of ground, the chip powers down. Digital Control and One-Time Programming The LT3582 series supports the Standard Mode I2C interface. Although using this interface is not required Linear Technology Magazine • June 2009 DESIGN FEATURES L for the LT3582-5 or LT3582-12, it does permit reading of the chip’s configuration and the ability to disable the power switches through the interface. Additional I 2C functionality is available with the LT3582 including re-programmability of the output voltages, and setting the power up sequencing and power down discharge. L1 1.5µH D1 INPUT 2.7V TO 4.2V VIN SWN SWP CAPP VOUTN I2C INTERFACE CAPP SDA VOUTP SCL VPP CA REG0/OTP0 = 1Ch REG1/OTP1 = 4Ch REG2/OTP2 = 07h C4 10µF RAMPP RAMPN C5 10nF C6 10nF VPOS 4.6V 100mA C3 10µF 300 250 70 200 60 150 50 100 40 30 POWER LOSS (mW) LT3582 VNEG –5V 90mA C1 10µF D2 350 VIN = 3.3V 80 L2 1.5µH GND C2 10µF The LT3582 is an easy-to-use compact solution for DC/DC converter applications where positive and negative outputs are required. It is accurate, efficient and includes an outsized number of features for its diminutive 3mm × 3mm 16-pin QFN package. It is offered in ±5V (LT3582-5), ±12V (LT3582-12) and I2C-programmable (LT3582) output versions. L 90 SHDN EFFICIENCY (%) SWN Conclusion A default power-up configuration can be made permanent in the LT3582 through the One-Time-Programmable memory. The chip will always use the default configuration from OTP memory upon power-up. Unless locked by programming a specific OTP memory bit, the chip configuration can be changed after power-up by writing new settings through the I2C interface. 50 0.1 D1-D2: PANASONIC M21D3800L LOW VF SCHOTTKY L1-L2: TDK MLP3216S1R5L C1-C4: TAIYO YUDEN JMK212BJ106MK, 6.3V, X5R 0805 C5-C6: 0402 X5R 1 10 LOAD CURRENT (mA) 0 100 Figure 11. Tiny AMOLED power supply is 0.8mm (max) thin LTC4217, continued from page 17 This example places a 20k resistor on the IMON pin to set the gain of the current monitor output to 1V per amp of MOSFET current. Instead of tying the TIMER pin to the INTVCC pin for a default 2ms overcurrent timeout, an external 0.47µF capacitor is used to set a 5.7ms timeout. During an overcurrent event the external timing capacitor is charged with a100µA pull-up current. If the voltage on the capacitor reaches the 1.2V threshold, the MOSFET turns off. The equation for setting timing capacitor’s value is as follows: CT = TCB • 0.083(µF/ms) While the MOSFET is cooling off, the LTC4217 discharges the timing capacitor. When the capacitor voltage reaches 0.2V an internal 100ms timer is started. Following this cool down period the fault is cleared (when using auto-retry) and the MOSFET is allowed to turn on again. It is important to consider the safe operating area of the MOSFET when 10 2.0 1 1ms 1.5 ID (A) CURRENT LIMIT THRESHOLD VALUE (A) 2.5 1.0 10ms 0.5 0 100ms 0.1 1k 10k 100k RSET (Ω) 1M 10M Figure 6. Current limit adjustment Linear Technology Magazine • June 2009 0.01 1s 10s DC TA = 25°C MULTIPLE PULSE DUTY CYCLE = 0.2 0.1 1 10 VDS (V) Figure 7. MOSFET SOA curve 100 extending the circuit breaker timeout beyond 2ms. The SOA graph for the MOSFET used in LTC4217 is shown in Figure 7. The worse case power dissipation occurs when the voltage versus current profile of the foldback current limit is at maximum. This occurs when the current is 1A and the voltage is one half of the 12V or 6V (see Figure 4, FB pin at 0.7V). In this case the power is 6W, which dictates a maximum time of 100ms (Figure 7, at 6V and 1A). Conclusion The primary role of the LTC4217 is to control hot insertion and provide the electronic circuit breaker function. Additionally the part includes protection of the MOSFET with focus on SOA compliance, thermal protection and precise 2A current limit. It is also adaptable over a large range of applications due to adjustable inrush current, overcurrent fault timer and current limit threshold. A high level of integration makes the LTC4217 easy to use yet versatile. L 25