INTERSIL HIP6004BCB

HIP6004B
HIP6004B
TM
Data Sheet
February 1999
Buck and Synchronous-Rectifier (PWM)
Controller and Output Voltage Monitor
Features
The HIP6004B provides complete control and protection for
a DC-DC converter optimized for high-performance
microprocessor applications. It is designed to drive two
N-Channel MOSFETs in a synchronous-rectified buck
topology. The HIP6004B integrates all of the control, output
adjustment, monitoring and protection functions into a
single package.
• Operates from +5V or +12V Input
• Drives Two N-Channel MOSFETs
The output voltage of the converter is easily adjusted and
precisely regulated. The HIP6004B includes a fully TTLcompatible 5-input digital-to-analog converter (DAC) that
adjusts the output voltage from 1.3V DC to 2.05VDC in
0.05V and from 2.1V DC to 3.5VDC in 0.1V increments
steps. The precision reference and voltage-mode regulator
hold the selected output voltage to within ±1% over
temperature and line voltage variations.
The HIP6004B provides simple, single feedback loop,
voltage-mode control with fast transient response. It
includes a 200kHz free-running triangle-wave oscillator that
is adjustable from below 50kHz to over 1MHz. The error
amplifier features a 15MHz gain-bandwidth product and
6V/µs slew rate which enables high converter bandwidth for
fast transient performance. The resulting PWM duty ratio
ranges from 0% to 100%.
The HIP6004B monitors the output voltage with a window
comparator that tracks the DAC output and issues a Power
Good signal when the output is within ±10%. The
HIP6004B protects against over-current and overvoltage
conditions by inhibiting PWM operation. Additional built-in
overvoltage protection triggers an external SCR to crowbar
the input supply. The HIP6004B monitors the current by
using the rDS(ON) of the upper MOSFET which eliminates
the need for a current sensing resistor.
Ordering Information
PART NUMBER
TEMP.
RANGE ( oC)
PACKAGE
FN4567.2
PKG.
NO.
HIP6004BCB
0 to 70
20 Ld SOIC
M20.3
HIP6004BCV
0 to 70
20 Ld TSSOP
M20.173
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the TSSOP variant in tape and reel, e.g., HIP6004BCV-T.
• Simple Single-Loop Control Design
- Voltage-Mode PWM Control
• Fast Transient Response
- High-Bandwidth Error Amplifier
- Full 0% to 100% Duty Ratio
• Excellent Output Voltage Regulation
- ±1% Over Line Voltage and Temperature
• TTL-Compatible 5-Bit Digital-to-Analog Output
Voltage Selection
- Wide Range . . . . . . . . . . . . . . . . . . . 1.3V DC to 3.5VDC
- 0.1V Binary Steps . . . . . . . . . . . . . . 2.1V DC to 3.5VDC
- 0.05V Binary Steps . . . . . . . . . . . . 1.3VDC to 2.05VDC
• Power-Good Output Voltage Monitor
• Over-Voltage and Over-Current Fault Monitors
- Does Not Require Extra Current Sensing Element,
Uses MOSFET’s rDS(ON)
• Small Converter Size
- Constant Frequency Operation
- 200kHz Free-Running Oscillator Programmable from
50kHz to over 1MHz
Applications
• Power Supply for Pentium®, Pentium Pro, Pentium II,
PowerPC™, K6™, 6X86™ and Alpha™ Microprocessors
• High-Power 5V to 3.xV DC-DC Regulators
• Low-Voltage Distributed Power Supplies
Pinout
HIP6004B
(SOIC, TSSOP)
TOP VIEW
VSEN
1
20 RT
OCSET
2
19 OVP
SS
3
18 VCC
VID0
4
17 LGATE
VID1
5
16 PGND
VID2
6
15 BOOT
VID3
7
14 UGATE
VID4
8
13 PHASE
COMP
9
12 PGOOD
FB 10
11 GND
6X86™ is a trademark of Cyrix Corporation.
Alpha™ is a trademark of Digital Equipment Corporation.
K6™ is a trademark of Advanced Micro Devices, Inc.
Pentium® is a registered trademark of Intel Corporation.
PowerPC™ is a trademark of IBM.
74
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
HIP6004B
Typical Application
+12V
VIN = +5V OR +12V
VCC
PGOOD
OCSET
MONITOR AND
PROTECTION
SS
EN
OVP
BOOT
RT
VID0
VID1
VID2
VID3
VID4
OSC
UGATE
PHASE
HIP6004B
+VOUT
D/A
FB
LGATE
-
+
+
-
COMP
PGND
GND
VSEN
Block Diagram
VCC
VSEN
POWER-ON
RESET (POR)
110%
+
-
PGOOD
90%
+
-
OVERVOLTAGE
115%
10µA
+
OVP
-
SOFTSTART
+
-
OCSET
REFERENCE
200µA
OVERCURRENT
SS
BOOT
UGATE
4V
PHASE
VID0
VID1
VID2
VID3
VID4
FB
TTL D/A
CONVERTER
(DAC)
PWM
COMPARATOR
DACOUT
+
-
+
-
ERROR
AMP
GATE
INHIBIT CONTROL
LOGIC
PWM
LGATE
PGND
COMP
GND
RT
OSCILLATOR
HIP6004B
Absolute Maximum Ratings
Thermal Information
Supply Voltage, V CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+15V
Boot Voltage, VBOOT - VPHASE . . . . . . . . . . . . . . . . . . . . . . . .+15V
Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.3V to VCC +0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
110
86
SOIC Package (with 3in2 of Copper) . . . . . . . . . . . .
TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . .
140
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(Lead Tips Only)
Operating Conditions
Supply Voltage, V CC . . . . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
UGATE and LGATE Open
-
5
-
mA
Rising VCC Threshold
VOCSET = 4.5V
-
-
10.4
V
Falling VCC Threshold
VOCSET = 4.5V
8.2
-
-
V
-
1.26
-
V
V CC SUPPLY CURRENT
Nominal Supply
ICC
POWER-ON RESET
Rising VOCSET Threshold
OSCILLATOR
Free Running Frequency
RT = OPEN
185
200
215
kHz
Total Variation
6kΩ < RT to GND < 200kΩ
-15
-
+15
%
-
1.9
-
VP-P
DAC (VID0-VID4) Input Low Voltage
-
-
0.8
V
DAC (VID0-VID4) Input High Voltage
2.0
-
-
V
DACOUT Voltage Accuracy
-1.0
-
+1.0
%
-
88
-
dB
-
15
-
MHz
-
6
-
V/µs
350
500
-
mA
-
5.5
10
Ω
300
450
-
mA
-
3.5
6.5
Ω
-
115
120
%
VOCSET = 4.5VDC
170
200
230
µA
VSEN = 5.5V, VOVP = 0V
60
-
-
mA
-
10
-
µA
Ramp Amplitude
∆VOSC
RT = Open
REFERENCE AND DAC
ERROR AMPLIFIER
DC Gain
Gain-Bandwidth Product
Slew Rate
GBW
SR
COMP = 10pF
GATE DRIVERS
Upper Gate Source
IUGATE
VBOOT - VPHASE = 12V, VUGATE = 6V
Upper Gate Sink
RUGATE
ILGATE = 0.3A
Lower Gate Source
ILGATE
VCC = 12V, VLGATE = 6V
Lower Gate Sink
RLGATE
ILGATE = 0.3A
PROTECTION
Over-Voltage Trip (VSEN/DACOUT)
OCSET Current Source
IOCSET
OVP Sourcing Current
IOVP
Soft Start Current
ISS
HIP6004B
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
POWER GOOD
Upper Threshold (VSEN /DACOUT)
VSEN Rising
106
-
111
%
Lower Threshold (VSEN /DACOUT)
VSEN Falling
89
-
94
%
Hysteresis (V SEN /DACOUT)
Upper and Lower Threshold
-
2
-
%
IPGOOD = -5mA
-
0.5
-
V
PGOOD Voltage Low
VPGOOD
Typical Performance Curves
80
CGATE = 3300pF
70
60
RT PULLUP
TO +12V
ICC (mA)
RESISTANCE (kΩ)
1000
100
50
CUPPER = CLOWER = CGATE
40
CGATE = 1000pF
30
10
20
RT PULLDOWN TO VSS
CGATE = 10pF
10
10
100
SWITCHING FREQUENCY (kHz)
FIGURE 1. RT RESISTANCE vs FREQUENCY
1000
0
100
200
300
400
500
600
700
800
900
SWITCHING FREQUENCY (kHz)
FIGURE 2. BIAS SUPPLY CURRENT vs FREQUENCY
1000
HIP6004B
Functional Pin Descriptions
PGOOD (Pin 12)
VSEN
1
20 RT
OCSET
2
19 OVP
SS
3
18 VCC
VID0
4
17 LGATE
VID1
5
16 PGND
VID2
6
15 BOOT
VID3
7
14 UGATE
VID4
8
13 PHASE
COMP
9
12 PGOOD
FB 10
11 GND
VSEN (Pin 1)
This pin is connected to the converters output voltage. The
PGOOD and OVP comparator circuits use this signal to
report output voltage status and for overvoltage protection.
OCSET (Pin 2)
Connect a resistor (R OCSET) from this pin to the drain of
the upper MOSFET. R OCSET , an internal 200µA current
source (IOCS), and the upper MOSFET on-resistance
(rDS(ON)) set the converter over-current (OC) trip point
according to the following equation:
IOCSET x R OCSET
I PEAK = ----------------------------------------------------r DS ( ON )
An over-current trip cycles the soft-start function.
SS (Pin 3)
Connect a capacitor from this pin to ground. This capacitor,
along with an internal 10µA current source, sets the softstart interval of the converter.
VID0-4 (Pins 4-8)
VID0-4 are the input pins to the 5-bit DAC. The states of
these five pins program the internal voltage reference
(DACOUT). The level of DACOUT sets the converter
output voltage. It also sets the PGOOD and OVP
thresholds. Table 1 specifies DACOUT for the all
combinations of DAC inputs.
COMP (Pin 9) and FB (Pin 10)
COMP and FB are the available external pins of the error
amplifier. The FB pin is the inverting input of the error
amplifier and the COMP pin is the error amplifier output.
These pins are used to compensate the voltage-control
feedback loop of the converter.
GND (Pin 11)
Signal ground for the IC. All voltage levels are measured
with respect to this pin.
PGOOD is an open collector output used to indicate the
status of the converter output voltage. This pin is pulled low
when the converter output is not within ±10% of the
DACOUT reference voltage. Exception to this behavior is
the ‘11111’ VID pin combination which disables the
converter; in this case PGOOD asserts a high level.
PHASE (Pin 13)
Connect the PHASE pin to the upper MOSFET source.
This pin is used to monitor the voltage drop across the
MOSFET for over-current protection. This pin also provides
the return path for the upper gate drive.
UGATE (Pin 14)
Connect UGATE to the upper MOSFET gate. This pin
provides the gate drive for the upper MOSFET.
BOOT (Pin 15)
This pin provides bias voltage to the upper MOSFET driver.
A bootstrap circuit may be used to create a BOOT voltage
suitable to drive a standard N-Channel MOSFET.
PGND (Pin 16)
This is the power ground connection. Tie the lower
MOSFET source to this pin.
LGATE (Pin 17)
Connect LGATE to the lower MOSFET gate. This pin
provides the gate drive for the lower MOSFET.
VCC (Pin 18)
Provide a 12V bias supply for the chip to this pin.
OVP (Pin 19)
The OVP pin can be used to drive an external SCR in the
event of an overvoltage condition. Output rising 15% more
than the DAC-set voltage triggers a high output on this pin
and disables PWM gate drive circuitry.
RT (Pin 20)
This pin provides oscillator switching frequency
adjustment. By placing a resistor (R T) from this pin to GND,
the nominal 200kHz switching frequency is increased
according to the following equation:
6
5 x 10
Fs ≈ 200kHz + --------------------R T ( kΩ )
(R T to GND)
Conversely, connecting a pull-up resistor (R T) from this pin
to VCC reduces the switching frequency according to the
following equation:
7
4 x 10
Fs ≈ 200kHz – --------------------R T ( kΩ )
(RT to 12V)
HIP6004B
Over-Current Protection
Initialization
The over-current function protects the converter from a
shorted output by using the upper MOSFET’s on-resistance,
rDS(ON) to monitor the current. This method enhances the
converter’s efficiency and reduces cost by eliminating a
current sensing resistor.
Soft Start
The POR function initiates the soft start sequence. An internal
10µA current source charges an external capacitor (CSS) on
the SS pin to 4V. Soft start clamps the error amplifier output
(COMP pin) and reference input (+ terminal of error amp) to the
SS pin voltage. Figure 3 shows the soft start interval with
CSS = 0.1µF. Initially the clamp on the error amplifier (COMP
pin) controls the converter’s output voltage. At t1 in Figure 3,
the SS voltage reaches the valley of the oscillator’s triangle
wave. The oscillator’s triangular waveform is compared to the
ramping error amplifier voltage. This generates PHASE pulses
of increasing width that charge the output capacitor(s). This
interval of increasing pulse width continues to t2 . With sufficient
output voltage, the clamp on the reference input controls the
output voltage. This is the interval between t2 and t3 in Figure 3.
At t3 the SS voltage exceeds the DACOUT voltage and the
output voltage is in regulation. This method provides a rapid
and controlled output voltage rise. The PGOOD signal toggles
‘high’ when the output voltage (VSEN pin) is within ±5% of
DACOUT. The 2% hysteresis built into the power good
comparators prevents PGOOD oscillation due to nominal
output voltage ripple.
PGOOD
(2V/DIV.)
0V
2V
15A
10A
5A
0A
TIME (20ms/DIV.)
FIGURE 4. OVER-CURRENT OPERATION
The over-current function cycles the soft-start function in a
hiccup mode to provide fault protection. A resistor (ROCSET)
programs the over-current trip level. An internal 200µA current
sink develops a voltage across ROCSET that is referenced to
VIN . When the voltage across the upper MOSFET (also
referenced to VIN) exceeds the voltage across ROCSET , the
over-current function initiates a soft-start sequence. The softstart function discharges CSS with a 10µA current sink and
inhibits PWM operation. The soft-start function recharges
CSS , and PWM operation resumes with the error amplifier
clamped to the SS voltage. Should an overload occur while
recharging CSS , the soft start function inhibits PWM operation
while fully charging CSS to 4V to complete its cycle. Figure 4
shows this operation with an overload condition. Note that the
inductor current increases to over 15A during the CSS
charging interval and causes an over-current trip. The
converter dissipates very little power with this method. The
measured input power for the conditions of Figure 4 is 2.5W.
The over-current function will trip at a peak inductor current
(IPEAK) determined by:
SOFT-START
(1V/DIV.)
OUTPUT
VOLTAGE
(1V/DIV.)
0V
0V
t1
4V
0V
OUTPUT INDUCTOR
The HIP6004B automatically initializes upon receipt of power.
Special sequencing of the input supplies is not necessary. The
Power-On Reset (POR) function continually monitors the input
supply voltages. The POR monitors the bias voltage at the VCC
pin and the input voltage (VIN) on the OCSET pin. The level on
OCSET is equal to VIN less a fixed voltage drop (see overcurrent protection). The POR function initiates soft start
operation after both input supply voltages exceed their POR
thresholds. For operation with a single +12V power source, VIN
and VCC are equivalent and the +12V power source must
exceed the rising VCC threshold before POR initiates operation.
SOFT-START
Functional Description
t2
t3
TIME (5ms/DIV.)
FIGURE 3. SOFT START INTERVAL
IOCSET x R OCSET
I PEAK = ----------------------------------------------------r DS ( ON )
where IOCSET is the internal OCSET current source
(200µA typical). The OC trip point varies mainly due to the
MOSFET’s rDS(ON) variations. To avoid over-current
tripping in the normal operating load range, find the
ROCSET resistor from the equation above with:
1. The maximum rDS(ON) at the highest junction temperature.
2. The minimum IOCSET from the specification table.
3. Determine IPEAK for I PEAK > I OUT ( MAX ) + ( ∆I ) ⁄ 2 ,
where ∆I is the output inductor ripple current.
HIP6004B
For an equation for the ripple current see the section under
component guidelines titled ‘Output Inductor Selection’.
A small ceramic capacitor should be placed in parallel with
ROCSET to smooth the voltage across ROCSET in the
presence of switching noise on the input voltage.
Output Voltage Program
The output voltage of a HIP6004B converter is programmed
to discrete levels between 1.8VDC and 3.5VDC . The voltage
identification (VID) pins program an internal voltage reference
(DACOUT) with a TTL-compatible 5-bit digital-to-analog
converter (DAC). The level of DACOUT also sets the PGOOD
and OVP thresholds. Table 1 specifies the DACOUT voltage
for the 32 different combinations of connections on the VID
pins. The output voltage should not be adjusted while the
converter is delivering power. Remove input power before
changing the output voltage. Adjusting the output voltage
during operation could toggle the PGOOD signal and exercise
the overvoltage protection.
‘11111’ VID pin combination resulting in a 0V output setting
activates the Power-On Reset function and disables the gate
drives circuitry. For this specific VID combination, though,
PGOOD asserts a high level. This unusual behavior has been
implemented in order to allow for operation in dualmicroprocessor systems where AND-ing of the PGOOD signals
from two individual power converters is implemented.
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
wide, short printed circuit traces. The critical components
should be located as close together as possible, using ground
plane construction or single point grounding.
TABLE 1. OUTPUT VOLTAGE PROGRAM
PIN NAME
PIN NAME
VID4
VID3
VID2
VID1
VID0
NOMINAL OUTPUT
VOLTAGE DACOUT
VID4
VID3
VID2
VID1
VID0
NOMINAL OUTPUT
VOLTAGE DACOUT
0
1
1
1
1
1.30
1
1
1
1
1
0
0
1
1
1
0
1.35
1
1
1
1
0
2.1
0
1
1
0
1
1.40
1
1
1
0
1
2.2
0
1
1
0
0
1.45
1
1
1
0
0
2.3
0
1
0
1
1
1.50
1
1
0
1
1
2.4
0
1
0
1
0
1.55
1
1
0
1
0
2.5
0
1
0
0
1
1.60
1
1
0
0
1
2.6
0
1
0
0
0
1.65
1
1
0
0
0
2.7
0
0
1
1
1
1.70
1
0
1
1
1
2.8
0
0
1
1
0
1.75
1
0
1
1
0
2.9
0
0
1
0
1
1.80
1
0
1
0
1
3.0
0
0
1
0
0
1.85
1
0
1
0
0
3.1
0
0
0
1
1
1.90
1
0
0
1
1
3.2
0
0
0
1
0
1.95
1
0
0
1
0
3.3
0
0
0
0
1
2.00
1
0
0
0
1
3.4
0
0
0
0
0
2.05
1
0
0
0
0
3.5
NOTE: 0 = connected to GND or VSS , 1 = connected to VDD through pull-up resistors.
HIP6004B
PWM
COMPARATOR
HIP6004B
LO
PHASE
CIN
Q2
LGATE
D2
LO
-
DRIVER
+
∆VOSC
Q1
CO
ESR
(PARASITIC)
ZFB
-
ZIN
+
REFERENCE
ERROR
AMP
RETURN
FIGURE 5. PRINTED CIRCUIT BOARD POWER AND GROUND
PLANES OR ISLANDS
DETAILED COMPENSATION COMPONENTS
ZFB
C2
Figure 5 shows the critical power components of the converter.
To minimize the voltage overshoot the interconnecting wires
indicated by heavy lines should be part of ground or power
plane in a printed circuit board. The components shown in
Figure 5 should be located as close together as possible.
Please note that the capacitors CIN and CO each represent
numerous physical capacitors. Locate the HIP6004B within 3
inches of the MOSFETs, Q1 and Q2 . The circuit traces for the
MOSFETs’ gate and source connections from the HIP6004B
must be sized to handle up to 1A peak current.
Figure 6 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the SS PIN and locate the capacitor, C SS
close to the SS pin because the internal current source is
only 10µA. Provide local VCC decoupling between V CC and
GND pins. Locate the capacitor, C BOOT as close as
practical to the BOOT and PHASE pins.
D1
CBOOT
LO
VOUT
PHASE
VCC
SS
+12V
Q2
CO
LOAD
HIP6004B
CVCC
CSS
C1
VOUT
ZIN
C3
R2
R3
R1
COMP
FB
+
HIP6004B
DACOUT
FIGURE 7. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
The PWM wave is smoothed by the output filter (LO and CO).
The modulator transfer function is the small-signal transfer
function of VOUT/VE/A . This function is dominated by a DC
Gain and the output filter (L O and CO ), with a double pole
break frequency at F LC and a zero at FESR . The DC Gain
of the modulator is simply the input voltage (V IN ) divided by
the peak-to-peak oscillator voltage ∆VOSC .
Modulator Break Frequency Equations
+VIN
Q1
CO
VE/A
PGND
BOOT
VOUT
PHASE
VOUT
LOAD
UGATE
VIN
DRIVER
OSC
VIN
GND
FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
Feedback Compensation
Figure 7 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(VOUT) is regulated to the Reference voltage level. The
error amplifier (Error Amp) output (VE/A) is compared with
the oscillator (OSC) triangular wave to provide a pulsewidth modulated (PWM) wave with an amplitude of V IN at
the PHASE node.
1
F LC = ------------------------------------------2π x LO x C O
1
F ESR = -------------------------------------------2π x ESR x C
O
The compensation network consists of the error amplifier
(internal to the HIP6004B) and the impedance networks
ZIN and ZFB. The goal of the compensation network is to
provide a closed loop transfer function with the highest 0dB
crossing frequency (f0dB) and adequate phase margin.
Phase margin is the difference between the closed loop
phase at f0dB and 180 degrees. The equations below relate
the compensation network’s poles, zeros and gain to the
components (R 1 , R2 , R3 , C 1 , C2 , and C3) in Figure 7. Use
these guidelines for locating the poles and zeros of the
compensation network:
1.
2.
3.
4.
5.
6.
7.
Pick Gain (R2/R1) for desired converter bandwidth.
Place 1ST Zero Below Filter’s Double Pole (~75% FLC).
Place 2ND Zero at Filter’s Double Pole.
Place 1ST Pole at the ESR Zero.
Place 2ND Pole at Half the Switching Frequency.
Check Gain against Error Amplifier’s Open-Loop Gain.
Estimate Phase Margin - Repeat if Necessary.
HIP6004B
Compensation Break Frequency Equations
1
F Z1 = -----------------------------------2π x R 2 x C 1
1
FP1 = -------------------------------------------------------- C 1 x C 2
2π x R 2 x  ---------------------- 
 C1 + C2 
1
F Z2 = ------------------------------------------------------2π x ( R 1 + R 3 ) x C 3
1
FP2 = -----------------------------------2π x R 3 x C 3
Figure 8 shows an asymptotic plot of the DC-DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 8. Using the above guidelines should give a
Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
Check the compensation gain at FP2 with the capabilities of
the error amplifier. The Closed Loop Gain is constructed on
the log-log graph of Figure 8 by adding the Modulator Gain (in
dB) to the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.
The compensation gain uses external impedance networks
ZFB and ZIN to provide a stable, high bandwidth (BW)
overall loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
100
FZ1 FZ2
FP1
FP2
80
OPEN LOOP
ERROR AMP GAIN
GAIN (dB)
60
40
20
20LOG
(R2/R1)
0
20LOG
(VIN /∆VOSC)
MODULATOR
GAIN
-20
COMPENSATION
GAIN
CLOSED LOOP
GAIN
-40
FLC
-60
10
100
1K
FESR
10K
100K
1M
10M
FREQUENCY (Hz)
FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and
supply the load transient current. The filtering requirements
are a function of the switching frequency and the ripple
current. The load transient requirements are a function of
the slew rate (di/dt) and the magnitude of the transient load
current. These requirements are generally met with a mix
of capacitors and careful layout.
Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (Effective Series Resistance) and voltage rating
requirements rather than actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible.
Be careful not to add inductance in the circuit board wiring
that could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements. For example, Intel
recommends that the high frequency decoupling for the
Pentium Pro be composed of at least forty (40) 1µF
ceramic capacitors in the 1206 surface-mount package.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient. An
aluminum electrolytic capacitor’s ESR value is related to the
case size with lower ESR available in larger case sizes.
However, the Equivalent Series Inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient loading.
Unfortunately, ESL is not a specified parameter. Work with
your capacitor supplier and measure the capacitor’s
impedance with frequency to select a suitable component. In
most cases, multiple electrolytic capacitors of small case size
perform better than a single large case capacitor.
Output Inductor Selection
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines
the converter’s ripple current and the ripple voltage is a
function of the ripple current. The ripple voltage and current
are approximated by the following equations:
∆I =
VIN - VOUT
Fs x L
x
VOUT
VIN
∆VOUT = ∆I x ESR
Increasing the value of inductance reduces the ripple
current and voltage. However, the large inductance values
reduce the converter’s response time to a load transient.
HIP6004B
One of the parameters limiting the converter’s response to
a load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
HIP6004B will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
value to the transient current level. During this interval the
difference between the inductor current and the transient
current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.
The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:
tRISE =
L x ITRAN
VIN - VOUT
tFALL =
L x ITRAN
VOUT
where: ITRAN is the transient load current step, tRISE is the
response time to the application of load, and tFALL is the
response time to the removal of load. With a +5V input
source, the worst case response time can be either at the
application or removal of load and dependent upon the
DACOUT setting. Be sure to check both of these equations
at the minimum and maximum output levels for the worst
case response time. With a +12V input, and output voltage
level equal to DACOUT, tFALL is the longest response time.
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk capacitors
to supply the current needed each time Q1 turns on. Place the
small ceramic capacitors physically close to the MOSFETs
and between the drain of Q1 and the source of Q2 .
The important parameters for the bulk input capacitor are
the voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and
current ratings above the maximum input voltage and
largest RMS current required by the circuit. The capacitor
voltage rating should be at least 1.25 times greater than the
maximum input voltage and a voltage rating of 1.5 times is
a conservative guideline. The RMS current rating
requirement for the input capacitor of a buck regulator is
approximately 1/2 the DC load current.
For a through hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo MV-GX
or equivalent) may be needed. For surface mount designs,
solid tantalum capacitors can be used, but caution must be
exercised with regard to the capacitor surge current rating.
These capacitors must be capable of handling the surgecurrent at power-up. The TPS series available from AVX, and
the 593D series from Sprague are both surge current tested.
MOSFET Selection/Considerations
The HIP6004B requires 2 N-Channel power MOSFETs. These
should be selected based upon rDS(ON) , gate supply
requirements, and thermal management requirements.
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss components;
conduction loss and switching loss. The conduction losses are
the largest component of power dissipation for both the upper
and the lower MOSFETs. These losses are distributed between
the two MOSFETs according to duty factor (see the equations
below). Only the upper MOSFET has switching losses, since
the Schottky rectifier clamps the switching node before the
synchronous rectifier turns on. These equations assume linear
voltage-current transitions and do not adequately model power
loss due the reverse-recovery of the lower MOSFET’s body
diode. The gate-charge losses are dissipated by the HIP6004B
and don't heat the MOSFETs. However, large gate-charge
increases the switching interval, tSW which increases the upper
MOSFET switching losses. Ensure that both MOSFETs are
within their maximum junction temperature at high ambient
temperature by calculating the temperature rise according to
package thermal-resistance specifications. A separate heatsink
may be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.
PUPPER = Io2 x rDS(ON) x D +
1
Io x VIN x tSW x FS
2
PLOWER = Io2 x rDS(ON) x (1 - D)
Where: D is the duty cycle = VOUT / VIN ,
tSW is the switch ON time, and
FS is the switching frequency.
Standard-gate MOSFETs are normally recommended for
use with the HIP6004B. However, logic-level gate
MOSFETs can be used under special circumstances. The
input voltage, upper gate drive level, and the MOSFET’s
absolute gate-to-source voltage rating determine whether
logic-level MOSFETs are appropriate.
Figure 9 shows the upper gate drive (BOOT pin) supplied by a
bootstrap circuit from VCC. The boot capacitor, CBOOT
develops a floating supply voltage referenced to the PHASE
pin. This supply is refreshed each cycle to a voltage of VCC
less the boot diode drop (VD) when the lower MOSFET, Q2
turns on. Logic-level MOSFETs can only be used if the
MOSFET’s absolute gate-to-source voltage rating exceeds
the maximum voltage applied to VCC .
HIP6004B
+12V
+12V
DBOOT
VCC
HIP6004B
VCC
BOOT
BOOT
HIP6004B
CBOOT
UGATE
Q1
UGATE
PHASE
-
+
+5V OR LESS
+5V OR +12V
+ VD -
LGATE
PGND
NOTE:
VG-S ≈ VCC -VD
Q2
D2
-
LGATE
+
NOTE:
VG-S ≈ VCC
GND
FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION
Figure 10 shows the upper gate drive supplied by a direct
connection to VCC . This option should only be used in
converter systems where the main input voltage is +5VDC or
less. The peak upper gate-to-source voltage is approximately
VCC less the input supply. For +5V main power and +12VDC
for the bias, the gate-to-source voltage of Q1 is 7V. A logiclevel MOSFET is a good choice for Q1 and a logic-level
MOSFET can be used for Q2 if its absolute gate-to-source
voltage rating exceeds the maximum voltage applied to VCC .
Q1
PHASE
PGND
NOTE:
VG-S ≈ VCC -5V
Q2
D2
NOTE:
VG-S ≈ VCC
GND
FIGURE 10. UPPER GATE DRIVE - DIRECT VCC DRIVE OPTION
Schottky Selection
Rectifier D 2 is a clamp that catches the negative inductor
swing during the dead time between turning off the lower
MOSFET and turning on the upper MOSFET. The diode
must be a Schottky type to prevent the lossy parasitic
MOSFET body diode from conducting. It is acceptable to
omit the diode and let the body diode of the lower MOSFET
clamp the negative inductor swing, but efficiency will drop
one or two percent as a result. The diode’s rated reverse
breakdown voltage must be greater than the maximum
input voltage.
HIP6004B
HIP6004B DC-DC Converter Application Circuit
in Application Note AN9672. Although the Application Note
details the HIP6004, the same evaluation platform can be
used to evaluate the HIP6004B.
Figure 11 shows an application circuit of a DC-DC
Converter for an Intel Pentium Pro microprocessor.
Detailed information on the circuit, including a complete
Bill-of-Materials and circuit board description, can be found
VIN =
+5V
OR
+12V
L1 - 1µH
F1
2x 1µF
2N6394
CIN
5x 1000µF
+12V
2K
D1
0.1µF
1000pF
VCC
OVP
18
19
2 OCSET
MONITOR
AND
PROTECTION
SS 3
12 PGOOD
15 BOOT
VSEN 1
0.1µF
RT
VID0
VID1
VID2
VID3
VID4
FB
20
4
5
6
7
8
1K
OSC
0.1µF
14 UGATE
Q1
L2
3µH
13 PHASE
HIP6004B
+VO
D/A
-
10
17 LGATE
+
+
16 PGND
-
9
D2
COUT
9x 1000µF
11
COMP
2.2nF
Q2
GND
20K
8.2nF
0.1µF
1.33K
15
Component Selection Notes:
COUT - Each 1000µF 6.3W VDC, Sanyo MV-GX or Equivalent.
CIN - Each 330µF 25W VDC, Sanyo MV-GX or Equivalent.
L2 - Core: Micrometals T50-52B; Each Winding: 10 Turns of 16AWG.
L1 - Core: Micrometals T50-52; Winding: 5 Turns of 18AWG.
D 1 - 1N4148 or Equivalent.
D 2 - 3A, 40V Schottky, Motorola MBR340 or Equivalent.
FIGURE 11. PENTIUM PRO DC-DC CONVERTER
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
7585 Irvine Center Drive
Suite 100
Irvine, CA 92618
TEL: (949) 341-7000
FAX: (949) 341-7123
Intersil Corporation
2401 Palm Bay Rd.
Palm Bay, FL 32905
TEL: (321) 724-7000
FAX: (321) 724-7946
85
EUROPE
Intersil Europe Sarl
Ave. William Graisse, 3
1006 Lausanne
Switzerland
TEL: +41 21 6140560
FAX: +41 21 6140579
ASIA
Intersil Corporation
Unit 1804 18/F Guangdong Water Building
83 Austin Road
TST, Kowloon Hong Kong
TEL: +852 2723 6339
FAX: +852 2730 1433