INTERSIL DG409DY

DG408, DG409
Data Sheet
June 1999
File Number
3283.5
Single 8-Channel/Differential 4-Channel,
CMOS Analog Multiplexers
Features
The DG408 Single 8-Channel, and DG409 Differential
4-Channel monolithic CMOS analog multiplexers are drop-in
replacements for the popular DG508A and DG509A series
devices. They each include an array of eight analog
switches, a TTL/CMOS compatible digital decode circuit for
channel selection, a voltage reference for logic thresholds
and an ENABLE input for device selection when several
multiplexers are present.
• Low Power Consumption (PD) . . . . . . . . . . . . . . . <11mW
The DG408 and DG409 feature lower signal ON resistance
(<100Ω) and faster switch transition time (tTRANS < 250ns)
compared to the DG508A or DG509A. Charge injection has
been reduced, simplifying sample and hold applications. The
improvements in the DG408 series are made possible by
using a high-voltage silicon-gate process. An epitaxial layer
prevents the latch-up associated with older CMOS
technologies. Power supplies may be single-ended from +5V
to +34V, or split from ±5V to ±20V.
• Single or Split Supply Operation
The analog switches are bilateral, equally matched for AC or
bidirectional signals. The ON resistance variation with
analog signals is quite low over a ±5V analog input range.
Ordering Information
PART
NUMBER
TEMP. RANGE
(oC)
PACKAGE
PKG. NO.
-40 to 85
16 Ld PDIP
E16.3
DG408DY
-40 to 85
16 Ld SOIC
M16.15
DG409DY
-40 to 85
16 Ld PDIP
-40 to 85
• Fast Switching Action
- tTRANS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <250ns
- tON/OFF(EN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . <150ns
• Low Charge Injection
• Upgrade from DG508A/DG509A
• TTL, CMOS Compatible
Applications
• Data Acquisition Systems
• Audio Switching Systems
• Automatic Testers
• Hi-Rel Systems
• Sample and Hold Circuits
• Communication Systems
• Analog Selector Switch
Pinouts
DG408 (PDIP, SOIC)
TOP VIEW
DG408DJ
DG409DJ
• ON Resistance (Max, 25oC). . . . . . . . . . . . . . . . . . . 100Ω
16 Ld SOIC
E16.3
M16.15
A0 1
16 A1
EN 2
15 A2
V- 3
14 GND
S1 4
13 V+
S2 5
12 S5
S3 6
11 S6
S4 7
10 S7
D 8
9 S8
DG409 (PDIP, SOIC)
TOP VIEW
A0 1
16 A1
EN 2
15 GND
V- 3
1
14 V+
S1A 4
13 S1B
S2A 5
12 S2B
S3A 6
11 S3B
S4A 7
10 S4B
DA 8
9 DB
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
DG408, DG409
Functional Block Diagrams
DG408
DG409
S1
D
S1A
DA
S4A
S2
DECODER/
DRIVER
DB
S1B
DECODER/
DRIVER
S4B
S8
5V
REF
† DIGITAL
INPUT
LEVEL
SHIFT
†
†
5V
REF
†
† DIGITAL
INPUT
†
PROTECTION
LEVEL
SHIFT
†
†
†
A0
A1
EN
PROTECTION
A0
A1
A2
EN
TRUTH TABLE DG408
TRUTH TABLE DG409
A2
A1
A0
EN
ON SWITCH
A1
A0
EN
ON SWITCH
X
X
X
0
NONE
X
X
0
NONE
0
0
0
1
1
0
0
1
1
0
0
1
1
2
0
1
1
2
0
1
0
1
3
1
0
1
3
0
1
1
1
4
1
1
1
4
1
0
0
1
5
1
0
1
1
6
1
1
0
1
7
1
1
1
1
8
2
NOTES:
1. VAH Logic “1” ≥2.4V.
2. VAL Logic “0” ≤0.8V.
DG408, DG409
Pin Descriptions - (DG408)
PIN
SYMBOL
1
A0
2
DESCRIPTION
Pin Descriptions - (DG409)
PIN
SYMBOL
Logic Decode Input (Bit 0, LSB)
1
A0
Logic Decode Input (Bit 0, LSB)
EN
Enable Input
2
EN
Enable Input
3
V-
Negative Power Supply Terminal
3
V-
Negative Power Supply Terminal
4
S1
Source (Input) for Channel 1
4
S1A
Source (Input) for Channel 1a
5
S2
Source (Input) for Channel 2
5
S2A
Source (Input) for Channel 2a
6
S3
Source (Input) for Channel 3
6
S3A
Source (Input) for Channel 3a
7
S4
Source (Input) for Channel 4
7
S4A
Source (Input) for Channel 4a
8
D
Drain (Output)
8
DA
Drain a (Output a)
9
S8
Source (Input) for Channel 8
9
DB
Drain b (Output b)
10
S7
Source (Input) for Channel 7
10
S4B
Source (Input) for Channel 4b
11
S6
Source (Input) for Channel 6
11
S3B
Source (Input) for Channel 3b
12
S5
Source (Input) for Channel 5
12
S2B
Source (Input) for Channel 2b
13
V+
Positive Power Supply Terminal (Substrate)
13
S1B
Source (Input) for Channel 1b
14
GND
Ground Terminal (Logic Common)
14
V+
Positive Power Supply Terminal
15
A2
Logic Decode Input (Bit 2, MSB)
15
GND
16
A1
Logic Decode Input (Bit 1)
16
A1
3
DESCRIPTION
Ground Terminal (Logic Common)
Logic Decode Input (Bit 1, MSB)
DG408, DG409
Absolute Maximum Ratings
Thermal Information
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44.0V
GND to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25V
Digital Inputs, VS , VD (Note 3). . . . . .(V-) -2V to (V+) + 2V or 20mA,
Whichever Occurs First
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA
Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max) . . 100mA
Thermal Resistance (Typical, Note 4)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
110
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 125oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. Signals on SX , DX, EN or AX exceeding V+ or V- are clamped by internal diodes. Limit diode current to maximum current ratings.
4. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Test Conditions: V+ = +15V, V- = -15V, VAL = 0.8V, VAH = 2.4V, Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
TEMP (oC)
(NOTE 5)
MIN
(NOTE 6)
TYP
(NOTE 5)
MAX
UNITS
160
250
ns
DYNAMIC CHARACTERISTICS
Transition Time, tTRANS
(See Figure 1)
Full
-
Break-Before-Make Interval, tOPEN
(See Figure 3)
25
10
-
-
ns
Enable Turn-ON Time, tON(EN)
(See Figure 2)
25
-
115
150
ns
Full
-
-
225
ns
Enable Turn-OFF Time, tOFF(EN)
(See Figure 2)
Full
-
105
150
ns
Charge Injection, Q
CL = 10nF, VS = 0V
25
-
20
-
pC
OFF Isolation
VEN = 0V, RL = 1kΩ,
f = 100kHz (Note 9)
25
-
-75
-
dB
Logic Input Capacitance, CIN
f = 1MHz
25
-
8
-
pF
Source OFF Capacitance, CS(OFF)
VEN = 0V, VS = 0V,
f = 1MHz
25
-
3
-
pF
Drain OFF Capacitance, CD(OFF)
DG408
VEN = 0V, VD = 0V,
f = 1MHz
25
-
26
-
pF
25
-
14
-
pF
25
-
37
-
pF
25
-
25
-
pF
DG409
Drain ON Capacitance, CD(ON)
DG408
VEN = 3V, VD = 0V,
f = 1MHz, VA = 0V or 3V
DG409
DIGITAL INPUT CHARACTERISTICS
Logic Input Current,
Input Voltage High, IAH
VA = 2.4V, 15V
Full
-10
-
10
µA
Logic Input Current,
Input Voltage Low, IAL
VEN = 0V, 2.4V,
VA = 0V
Full
-10
-
10
µA
Full
-15
-
15
V
25
-
40
100
Ω
Full
-
-
125
Ω
-
15
Ω
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
Drain-Source ON Resistance,
rDS(ON)
VD = ±10V, IS = -10mA
(Note 7)
rDS(ON) Matching Between Channels,
∆rDS(ON)
VD = 10V, -10V (Note 8)
25
-
Source OFF Leakage Current, IS(OFF)
VEN = 0V, VS = ±10V,
VD = +10V
25
-0.5
-
0.5
nA
Full
-5
-
5
nA
4
DG408, DG409
Electrical Specifications
Test Conditions: V+ = +15V, V- = -15V, VAL = 0.8V, VAH = 2.4V, Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
TEMP (oC)
(NOTE 5)
MIN
(NOTE 6)
TYP
(NOTE 5)
MAX
UNITS
25
-1
-
1
nA
Full
-20
-
20
nA
25
-1
-
1
nA
Full
-10
-
10
nA
VEN = 0V, VD = ±10V,
VS = +10V
Drain OFF Leakage Current, ID(OFF)
DG408
DG409
VS = VD = ±10V (Note 7)
Drain ON Leakage Current, ID(ON)
DG408
DG409
25
-1
-
1
nA
Full
-20
-
20
nA
25
-1
-
1
nA
Full
-10
-
10
nA
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
VEN = 0V, VA = 0V (Standby)
Negative Supply Current, IPositive Supply Current, I+
VEN = 2.4V, VA = 0V
(Enabled)
Negative Supply Current, I-
Electrical Specifications
Full
-
10
75
µA
Full
-75
1
-
µA
25
-
0.2
0.5
mA
Full
-
-
2
mA
Full
-500
-
-
µA
Single Supply Test Conditions: V+ = 12V, V- = 0V, VAL = 0.8V, VAH = 2.4V,
Unless Otherwise Specified
TEST
CONDITION
PARAMETER
TEMP (oC)
(NOTE 5)
MIN
(NOTE 6)
TYP
(NOTE 5)
MAX
UNITS
DYNAMIC CHARACTERISTICS
Switching Time of Multiplexer, tTRANS
VS1 = 8V, VS8 = 0V, VIN = 2.4V
25
-
180
-
ns
Enable Turn-ON Time, tON(EN)
VINH = 2.4V, VINL = 0V,
VS1 = 5V
25
-
180
-
ns
25
-
120
-
ns
25
-
5
-
pC
Full
0
-
12
V
25
-
90
-
Ω
Enable Turn-OFF Time, tOFF(EN)
Charge Injection, Q
CL = 10nF, VGEN = 0V,
RGEN = 0Ω
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
Drain-Source ON-Resistance,
rDS(ON)
VD = 3V, 10V, IS = -1mA
(Note 7)
NOTES:
5. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
6. Typical values are for DESIGN AID ONLY, not guaranteed nor production tested.
7. Sequence each switch ON.
8. ∆rDS(ON) = rDS(ON) (Max) - rDS(ON) (Min).
9. Worst case isolation occurs on channel 4 due to proximity to the drain pin.
5
DG408, DG409
Test Circuits and Waveforms
+15V
+15V
+2.4V
LOGIC
INPUT
A1
A2
V+
S1
S2 - S7
DG408 S
8
GND
V-
±10V
±
EN
A0
EN
SWITCH
OUTPUT
VO
10V
D
50Ω
300Ω
S1A - S4A, DA
A0 DG409 S4B
LOGIC
INPUT
35pF
V+
S1B
A1 GND
V-
±10V
±
+2.4V
10V
DB
50Ω
300Ω
-15V
SWITCH
OUTPUT
VO
35pF
-15V
FIGURE 1A. DG408 TEST CIRCUIT
LOGIC
INPUT
FIGURE 1B. DG409 TEST CIRCUIT
3V
50%
50%
0V
VS1
SWITCH
OUTPUT
VO
tr < 20ns
tf < 20ns
S1
ON
0.8 VS1
0V
0.8 VS8
VS8
tTRANS
tTRANS
S8
ON
FIGURE 1C. MEASUREMENT POINTS
FIGURE 1. TRANSITION TIME
+15V
A0
LOGIC
INPUT
A1
VIN
A2
+15V
V+
S1
DG408
S2 - S8
EN GND
V-
50Ω
V+
S1B
DG409
A1
S1A - S4A
S2B - S4B, DA
EN GND V- DB
A0
-5V
SWITCH
OUTPUT
VO
D
300Ω
LOGIC
INPUT
35pF
VIN
50Ω
SWITCH
OUTPUT
Vo
300Ω
-15V
-15V
FIGURE 2A. DG408 TEST CIRCUIT
LOGIC
INPUT
VIN
FIGURE 2B. DG409 TEST CIRCUIT
tr < 20ns
tf < 20ns
3V
50%
50%
0V
tON(EN)
0V
SWITCH
OUTPUT
VO
VO
0.9 VO
tOFF(EN)
FIGURE 2C. MEASUREMENT POINTS
FIGURE 2. ENABLE SWITCHING TIMES
6
-5V
35pF
DG408, DG409
Test Circuits and Waveforms
(Continued)
+15V
LOGIC
INPUT
+2.4V
V+
EN ALL S AND DA
A0
LOGIC
INPUT
A1
A2
V-
0V
+5V (VS)
VS
DG408
DG409
GND
tr < 20ns
tf < 20ns
3V
SWITCH
OUTPUT
VO
D, DB
50Ω
300Ω
SWITCH
OUTPUT
VO
35pF
80%
80%
0V
tOPEN
-15V
FIGURE 3A. TEST CIRCUIT
FIGURE 3B. MEASUREMENT POINTS
FIGURE 3. BREAK-BEFORE-MAKE INTERVAL
+15V
RGEN
V+
SX
VGEN
LOGIC
INPUT
CL
10nF
EN GND
0V
VO
D
A0
A1
A2
CHANNEL
SELECT
3V
SWITCH
OUTPUT
ON
V∆VO IS THE MEASURED VOLTAGE DUE
TO CHARGE TRANSFER ERROR, Q
Q = CL x ∆VO
-15V
LOGIC INPUT
∆VO
OFF
FIGURE 4A. TEST CIRCUIT
FIGURE 4B. MEASUREMENT POINTS
FIGURE 4. CHARGE INJECTION
5V +15V
0V +15V
VIN
SX
EN
V+
1kΩ
|
|
S8
VO
D
A2
SIGNAL
GENERATOR
VIN
A0
V-
EN
V+
|
|
S8
VO
D
A2
1kΩ
A1
S1
SX
SIGNAL
GENERATOR
GND
1kΩ
A1
A0
VGND
-15V
ANALYZER
-15V
ANALYZER
V OUT
OFF ISOLATION = 20 Log ----------------V IN
FIGURE 5. OFF ISOLATION
7
V OUT
CROSSTALK = 20 Log ----------------V IN
FIGURE 6. CROSSTALK
DG408, DG409
Test Circuits and Waveforms
(Continued)
5V +15V
3V OR 0V
+15V
VIN
S1
EN
V+
EN
V+
A2
S1
|
|
S8
VO
CHANNEL
SELECT
D
SIGNAL
GENERATOR
A2
A1
IMPEDANCE
ANALYZER
RL
A1
A0
A0
D
V-
V-
GND
GND
-15V
-15V
ANALYZER
V OUT
INSERTION LOSS = 20 Log ----------------V IN
FIGURE 7. INSERTION LOSS
FIGURE 8. SOURCE/DRAIN CAPACITANCES
Typical Applications
Overvoltage Protection
V+
A very convenient form of overvoltage protection consists of
adding two small signal diodes (1N4148, 1N914 type) in
series with the supply pins (see Figure 9). This arrangement
effectively blocks the flow of reverse currents. It also floats
the supply pin above or below the normal V+ or V- value. In
this case the overvoltage signal actually becomes the power
supply of the IC. From the point of view of the chip, nothing
has changed, as long as the difference V+ - (V-) doesn’t
exceed 44V. The addition of these diodes will reduce the
analog signal range to 1V below V+ and 1V above V-, but it
preserves the low channel resistance and low leakage
characteristics.
Typical application information is for Design Aid Only, not
guaranteed and not subject to production testing.
8
1N4148
SX
D
DG408
VG
1N4148
V-
FIGURE 9. OVERVOLTAGE PROTECTION USING BLOCKING
DIODES
DG408, DG409
Typical Performance Curves
75
3.5
3.0
CD(ON)
V+ = +15V
V- = -15V
50
CS, D (pF)
IIN (pA)
2.0
1.0
CD(OFF)
25
0.5pA
0.0
CS(OFF)
0
-1.0
0
5
10
0
15
4
8
FIGURE 10. INPUT LOGIC CURRENT vs LOGIC INPUT
VOLTAGE
FIGURE 11. SOURCE/DRAIN CAPACITANCE vs ANALOG
VOLTAGE (SINGLE 12V SUPPLY)
80
VSUPPLY = ±15V
VIN = 0V
V+ = +15V
V- = -15V
0
CD(ON)
-200
CD(OFF)
IIN (pA)
CS, D (pF)
60
40
-400
20
CS(OFF)
-600
0
-15
0
VA (V)
-800
15
FIGURE 12. SOURCE/DRAIN CAPACITANCE vs ANALOG
VOLTAGE
-55
5
45
TEMPERATURE (oC)
85
125
FIGURE 13. LOGIC INPUT CURRENT vs TEMPERATURE
60
100
DG408 ID(OFF)
40
60
DG409 ID(OFF)
DG409 ID(ON)
20
V+ = 15V
V- = -15V
VS = -VD FOR ID(OFF)
VD = VS(OPEN) FOR ID(ON)
20
DG408 ID(ON)
ID (pA)
ID (pA)
12
VA (V)
VIN (V)
0
-20
-60
-20
DG409 ID(OFF)
VS = 0V FOR ID(OFF)
VS = VD FOR ID(ON)
-40
-100
DG408 ID(ON), ID(OFF)
-60
0
2
4
6
VD (V)
8
10
12
FIGURE 14. DRAIN LEAKAGE CURRENT vs SOURCE/DRAIN
VOLTAGE (SINGLE 12V SUPPLY)
9
DG409 ID(ON)
-140
-15
0
15
VS , VD (V)
FIGURE 15. DRAIN LEAKAGE CURRENT vs SOURCE/DRAIN
VOLTAGE
DG408, DG409
Typical Performance Curves
(Continued)
20
2.0
15
1.5
V+ = +15V
V- = -15V
VIN (V)
IS(OFF) (pA)
10
5
0
V+ = +12V
V- = 0V
1.0
0.5
-5
0.0
-10
-15
0
4
15
8
12
FIGURE 16. SOURCE LEAKAGE CURRENT vs SOURCE
VOLTAGE
20
FIGURE 17. INPUT SWITCHING THRESHOLD vs SUPPLY
VOLTAGE
104
105
VSUPPLY = ±15V
VSUPPLY = ±15V
103
104
EN = 2.4V
102
I+ (mA)
103
-(I-) (µA)
16
VSUPPLY (±V)
VS (V)
102
10
EN = 0V
10
1
1
EN = 2.4V
0.1
EN = 0V
0.1
0.01
100
1K
10K
100K
1M
10M
100
FIGURE 18. NEGATIVE SUPPLY CURRENT vs SWITCHING
FREQUENCY
105
100K
1M
10M
0
I+
103
-200
102
I- (nA)
I+, I- (nA)
10K
FIGURE 19. POSITIVE SUPPLY CURRENT vs SWITCHING
FREQUENCY
VSUPPLY = ±15V
104
1K
SWITCHING FREQUENCY (Hz)
SWITCHING FREQUENCY (Hz)
10
-400
1
-600
0.1
-(I-)
0.01
-55
5
45
85
TEMPERATURE (oC)
FIGURE 20. ISUPPLY vs TEMPERATURE
10
125
-800
-55
V+ = 15V
V- = -15V
VIN = 0V
VEN = 0V
45
5
TEMPERATURE (oC)
85
125
FIGURE 21. NEGATIVE SUPPLY CURRENT vs TEMPERATURE
DG408, DG409
Typical Performance Curves
(Continued)
90
20
15
CL = 10,000pF
VIN = 5VP-P
80
V+ = 15V
V- = -15V
VIN = 0V
VEN = 0V
70
60
V+ = 15V
V- = -15V
Q (pC)
I+ (µA)
50
10
40
30
20
10
5
V+ = 12V
V- = 0V
0
-10
0
-55
45
5
85
-15
125
-10
-5
TEMPERATURE (oC)
FIGURE 22. POSITIVE SUPPLY CURRENT vs TEMPERATURE
(DG408)
0
VS (V)
5
15
10
FIGURE 23. CHARGE INJECTION vs ANALOG VOLTAGE
160
120
140
V+ = 7.5V
100
±5V
120
rDS(ON) (Ω)
rDS(ON) (Ω)
80
±8V
60
±10V
±12V
40
10V
100
12V
80
15V
20V
60
40
20
22V
V- = 0V
±15V
20
±20V
0
0
-20 -16
-12
-8
-4
0
VD (V)
4
8
12
16
0
20
FIGURE 24. rDS(ON) vs VD AND SUPPLY
4
8
12
VD (V)
20
22
FIGURE 25. rDS(ON) vs VD (SINGLE SUPPLY)
130
80
125oC
V+ = 15V
V- = -15V
70
110
85oC
60
125oC
50
90
rDS(ON) (Ω)
rDS(ON) (Ω)
16
85oC
40
25oC
30
25oC
70
50
20
0oC
10
-40oC
-55oC
0oC
-40oC
-55oC
30
0
V+ = 12V
V- = 0V
10
-15
0
VS (V)
FIGURE 26. rDS(ON) vs VS AND TEMPERATURE
11
15
0
8
4
VS (V)
FIGURE 27. rDS(ON) vs VS AND TEMPERATURE
(SINGLE SUPPLY)
12
DG408, DG409
Typical Performance Curves
(Continued)
275
-150
V+ = +15V
V- = -15V
RL = 1kΩ
-130
250
225
OFF ISOLATION
-90
t (ns)
(dB)
-110
200
tTRANS
175
-70
tOFF(EN)
150
CROSSTALK
-50
tON(EN)
125
-30
100
100
1K
10K
100K
1M
10M
100M
8
9
10
11
12
13
14
15
VSUPPLY (V)
FREQUENCY (Hz)
FIGURE 28. OFF ISOLATION AND CROSSTALK vs FREQUENCY
FIGURE 29. SWITCHING TIME vs SINGLE SUPPLY
190
200
tTRANS
tTRANS
170
175
tON(EN)
150
t (ns)
t (ns)
150
130
125
tOFF(EN)
tOFF(EN)
110
100
tON(EN)
75
10
90
12
14
16
18
20
22
2
3
4
5
VIN (V)
VSUPPLY (±V)
FIGURE 30. SWITCHING TIME vs BIPOLAR SUPPLY
FIGURE 31. SWITCHING TIME vs VIN (SINGLE SUPPLY)
1
180
RL = 1kΩ
0
tTRANS
160
-1
t (ns)
LOSS (dB)
140
120
V+ = +15V
V- = -15V
REF. 1VRMS
-2
-3
-4
tOFF(EN)
100
RL = 50Ω
-5
tON(EN)
-6
80
2
3
4
5
VIN (V)
FIGURE 32. SWITCHING TIME vs VIN (BIPOLAR SUPPLY)
Die Characteristics
12
10
102
103
104
105
106
FREQUENCY (Hz)
107
FIGURE 33. INSERTION LOSS vs FREQUENCY
108
DG408, DG409
DIE DIMENSIONS:
PASSIVATION:
1800µm x 3320µm x 485µm
Type: Nitride
Thickness: 8kÅ ±1kÅ
METALLIZATION:
WORST CASE CURRENT DENSITY:
Type: SiAl
Thickness: 12kÅ ±1kÅ
9.1 x 104 A/cm2
Metallization Mask Layout
DG408
EN
(2)
A1
(16)
A0
(1)
A2
(15)
GND
(14)
NC
V- (3)
(13) V+
S1 (4)
(12) S5
S2 (5)
(11) S6
S3 (6)
NC
S4 (7)
(8)
D
13
(9)
S8
(10)
S7
DG408, DG409
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
1800µm x 3320µm x 485µm
Type: Nitride
Thickness: 8kÅ ±1kÅ
METALLIZATION:
WORST CASE CURRENT DENSITY:
Type: SiAl
Thickness: 12kÅ ±1kÅ
9.1 x 104 A/cm2
Metallization Mask Layout
DG409
EN
(2)
A1
(16)
A0
(1)
GND
(15)
NC
NC
V- (3)
(14) V+
S1A (4)
(13) S1B
S2A (5)
(12) S2B
S3A (6)
(11) S3B
S4A (7)
(8)
DA
14
(9)
DB
(10)
S4B
DG408, DG409
Dual-In-Line Plastic Packages (PDIP)
E16.3 (JEDEC MS-001-BB ISSUE D)
N
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
-B-
-AD
E
BASE
PLANE
-C-
A2
SEATING
PLANE
A
L
D1
e
B1
D1
A1
eC
B
0.010 (0.25) M
C A B S
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.045
0.070
1.15
1.77
8, 10
eA
C
0.008
0.014
C
D
0.735
0.775
18.66
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
15
MILLIMETERS
0.204
0.355
-
19.68
5
D1
0.005
-
0.13
-
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
e
0.100 BSC
eA
0.300 BSC
eB
-
L
0.115
N
16
2.54 BSC
7.62 BSC
0.430
-
0.150
2.93
10.92
3.81
16
6
7
4
9
Rev. 0 12/93
DG408, DG409
Small Outline Plastic Packages (SOIC)
M16.15 (JEDEC MS-012-AC ISSUE C)
N
INDEX
AREA
H
0.25(0.010) M
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
B M
E
INCHES
-B-
1
2
SYMBOL
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
α
e
B
0.25(0.010) M
C
0.10(0.004)
C A M
B S
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
MAX
MILLIMETERS
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.3859
0.3937
9.80
10.00
3
E
0.1497
0.1574
3.80
4.00
4
e
A1
MIN
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
N
α
16
0o
16
8o
0o
7
8o
Rev. 0 12/93
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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16
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