ICL7126 ® Data Sheet October 25, 2004 3 1/2 Digit, Low Power, Single Chip A/D Converter The ICL7126 is a high performance, very low power 31/2-digit, A/D converter. All the necessary active devices are contained on a single CMOS IC, including seven segment decoders, display drivers, reference, and clock. The ICL7126 is designed to interface with a liquid crystal display (LCD) and includes a backplane drive. The supply current of 100µA is ideally suited for 9V battery operation. The ICL7126 brings together an unprecedented combination of high accuracy, versatility, and true economy. It features auto-zero to less than 10µV, zero drift of less than 1µV/oC, input bias current of 10pA maximum, and rollover error of less than one count. The versatility of true differential input and reference is useful in all systems, but gives the designer an uncommon advantage when measuring load cells, strain gauges and other bridge-type transducers. And finally the true economy of single power operation allows a high performance panel meter or multi-meter to be built with the addition of only 10 passive components and a display. Features • 8,000 Hours Typical 9V Battery Life • Guaranteed Zero Reading for 0V Input on All Scales • True Polarity at Zero for Precise Null Detection • 1pA Typical Input Current • True Differential Input and Reference • Direct LCD Display Drive - No External Components Required • Pin Compatible With the ICL7106 • Low Noise - Less Than 15µVP-P • On-Chip Clock and Reference • Low Power Dissipation Guaranteed Less Than 1mW • No Additional Active Circuits Required • Pb-Free Available (RoHS Compliant) Pinout ICL7126 (PDIP) TOP VIEW The ICL7126 can be used as a plug-in replacement for the ICL7106 in a wide variety of applications, changing only the passive components. Ordering Information TEMP. RANGE PART NUMBER (°C) PACKAGE PKG. DWG. # FN3084.5 (1s) V+ 1 40 OSC 1 D1 2 39 OSC 2 C1 3 38 OSC 3 B1 4 37 TEST A1 5 36 REF HI F1 6 35 REF LO ICL7126CPL 0 to 70 40 Ld PDIP E40.6 G1 7 34 CREF+ ICL7126CPLZ (Note 1) 0 to 70 40 Ld PDIP E40.6 (Pb-free) (Note 2) E1 8 D2 9 33 CREF32 COMMON C2 10 31 IN HI B2 11 30 IN LO A2 12 29 A-Z F2 13 28 BUFF E2 14 27 INT D3 15 26 V- B3 16 25 G2 (10s) F3 17 24 C3 E3 18 23 A3 (1000) AB4 19 22 G3 POL (MINUS) 20 21 BP/GND NOTES: 1. Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C. 2. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. 1 (10s) (100s) (100s) CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003, 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ICL7126 Absolute Maximum Ratings Thermal Information Supply Voltage V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V Analog Input Voltage (Either Input) (Note 1) . . . . . . . . . . . . .V+ to VReference Input Voltage (Either Input) . . . . . . . . . . . . . . . . .V+ to VClock Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEST to V+ Thermal Resistance (Typical, Note 2) θJA (oC/W) PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC NOTE: Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Input voltages may exceed the supply voltages provided the input current is limited to ±100µA. 2. θJA is measured with the component mounted on an evaluation PC board in free air. TA = 25oC, VREF = 100mV, fCLOCK = 48kHz (Notes 1, 3) Electrical Specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNITS -000.0 ±000.0 +000.0 Digital Reading 999 999/100 0 1000 Digital Reading SYSTEM PERFORMANCE Zero Input Reading VIN = 0.0V, Full Scale = 200mV Ratiometric Reading VlN = VREF , VREF = 100mV Rollover Error -VIN = +VlN ≅ 200mV Difference in Reading for Equal Positive and Negative Inputs Near Full Scale - ±0.2 ±1 Counts Linearity Full Scale = 200mV or Full Scale = 2V Maximum Deviation from Best Straight Line Fit (Note 5) - ±0.2 ±1 Counts Common Mode Rejection Ratio VCM = ±1V, VIN = 0V, Full Scale = 200mV (Note 5) - 50 - µV/V Noise VIN = 0V, Full Scale = 200mV (Peak-To-Peak Value Not Exceeded 95% of Time) (Note 5) - 15 - µV Leakage Current Input VlN = 0V (Note 5) - 1 10 pA Zero Reading Drift VlN = 0V, 0oC To 70oC (Note 5) VIN = 199mV, 0oC To 70oC, (Ext. Ref. 0ppm/×oC) (Note 5) - 0.2 1 µV/oC - 1 5 ppm/oC V+ Supply Current VIN = 0V (Does Not Include COMMON Current) - 70 100 µA COMMON Pin Analog Common Voltage 25kΩ Between Common and Positive Supply (With Respect to + Supply) 2.4 3.0 3.2 V Temperature Coefficient of Analog Common 25kΩ Between Common and Positive Supply (With Respect to + Supply) (Note 5) - 80 - ppm/oC Peak-To-Peak Segment Drive Voltage Peak-To-Peak Backplane Drive Voltage V+ = to V- = 9V (Note 4) 4 5.5 6 V Power Dissipation Capacitance vs Clock Frequency - 40 - pF Scale Factor Temperature Coefficient NOTES: 3. Unless otherwise noted, specifications are tested using the circuit of Figure 1. 4. Back plane drive is in phase with segment drive for ‘off’ segment, 180 degrees out of phase for ‘on’ segment. Frequency is 20 times conversion rate. Average DC component is less than 50mV. 5. Not tested, guaranteed by design. 2 FN3084.5 ICL7126 Typical Application Schematics - 9V + IN - + 750Ω R1 R5 240kΩ 1MΩ 0.047µF A3 23 G3 22 BP 21 20 POL C3 24 17 F3 19 AB4 G2 25 16 B3 18 E3 V- 26 INT 27 C1 = 0.1µF C2 = 0.22µF C3 = 0.047µF C4 = 50pF C5 = 0.01µF R1 = 240kΩ R2 = 180kΩ R3 = 180kΩ R4 = 10kΩ R5 = 1MΩ DISPLAY 15 D3 A-Z 29 IN HI 31 BUFF 28 0.01 C3 0.22µF C2 R2 IN LO 30 COM 32 CREF- 33 REF LO 35 TEST 37 C1 0.1µF REF HI 36 OSC 3 38 180kΩ OSC 2 39 OSC 1 40 R4 10kΩ C4 50pF CREF+ 34 R3 180kΩ C5 14 E2 13 F2 12 A2 11 B2 D2 9 10 C2 E1 8 A1 5 F1 B1 4 G1 C1 3 7 D1 2 6 V+ 1 ICL7126 DISPLAY FIGURE 1. ICL7126 TEST CIRCUIT AND TYPICAL APPLICATION WITH LCD DISPLAY COMPONENTS SELECTED FOR 200mV FULL SCALE - + SET REF = 100.0mV IN 9V - + R1 R5 240kΩ 1MΩ C5 V- 26 G2 25 C3 24 A3 23 G3 22 BP 21 16 B3 17 F3 18 E3 19 AB4 20 POL DISPLAY 15 D3 INT 27 0.15µF BUFF 28 14 E2 180kΩ C3 13 F2 IN LO 30 IN HI 31 COM 32 CREF- 33 CREF+ 34 REF HI 36 REF LO 35 TEST 37 OSC 3 38 A-Z 29 0.33µF C2 R2 C1 0.1µF OSC 2 39 OSC 1 40 180kΩ C4 50pF 0.01 R3 R4 10kΩ B1 A1 F1 G1 E1 D2 4 5 6 7 8 9 11 B2 C1 3 12 A2 D1 2 10 C2 V+ 1 ICL7126 C1 = 0.1µF C2 = 0.33µF C3 = 0.5µF C4 = 50pF C5 = 0.01µF R1 = 240kΩ R2 = 180kΩ R3 = 180kΩ R4 = 10kΩ R5 = 1MΩ DISPLAY FIGURE 2. ICL7126 CLOCK FREQUENCY 16kHz, 1 READING/S 3 FN3084.5 ICL7126 (Continued) R1 240kΩ IN - + + 9V - Typical Application Schematics 750Ω R5 1MΩ C5 0.047µF A3 23 BP 21 20 POL C3 24 17 F3 G3 22 G2 25 16 B3 19 AB4 V- 26 15 D3 18 E3 INT 27 14 E2 180kΩ DISPLAY BUFF 28 A-Z 29 C3 13 F2 0.22µF 0.01 IN HI 31 IN LO 30 COM 32 CREF- 33 REF LO 35 TEST 37 C2 R2 C1 0.1µF REF HI 36 OSC 3 38 180kΩ OSC 2 39 OSC 1 40 R4 10kΩ C4 50pF CREF+ 34 R3 B1 A1 F1 G1 E1 D2 4 5 6 7 8 9 12 A2 C1 3 11 B2 D1 2 10 C2 V+ 1 ICL7126 C1 = 0.1µF C2 = 0.22µF C3 = 0.047µF C4 = 50pF C5 = 0.01µF R1 = 240kΩ R2 = 180kΩ R3 = 180kΩ R4 = 10kΩ R5 = 1MΩ DISPLAY FIGURE 3. CLOCK FREQUENCY 48kHz, 3 READINGS/S 4 FN3084.5 ICL7126 Design Information Summary Sheet • OSCILLATOR FREQUENCY fOSC = 0.45/RC COSC > 50pF; ROSC > 50kΩ fOSC (Typ) = 48kHz • DISPLAY COUNT • OSCILLATOR PERIOD tOSC = RC/0.45 • CONVERSION CYCLE tCYC = tCL0CK x 4000 tCYC = tOSC x 16,000 when fOSC = 48KHz; tCYC = 333ms V IN COUNT = 1000 × --------------V REF • INTEGRATION CLOCK FREQUENCY fCLOCK = fOSC /4 • COMMON MODE INPUT VOLTAGE (V- + 1V) < VlN < (V+ - 0.5V) • INTEGRATION PERIOD tINT = 1000 x (4/fOSC) • AUTO-ZERO CAPACITOR 0.01µF < CAZ < 1µF • 60/50Hz REJECTION CRITERION tINT /t60Hz or tlNT /t50Hz = Integer • REFERENCE CAPACITOR 0.1µF < CREF < 1µF • OPTIMUM INTEGRATION CURRENT IINT = 4µA • FULL-SCALE ANALOG INPUT VOLTAGE VlNFS (Typ) = 200mV or 2V • INTEGRATE RESISTOR V INFS R INT = ---------------I INT • VCOM Biased between V+ and V• VCOM ≅ V+ - 2.8V Regulation lost when V+ to V- < ≅6.8V; If VCOM is externally pulled down to (V + to V -)/2, the VCOM circuit will turn off • ICL7126 POWER SUPPLY: SINGLE 9V V+ - V- = 9V Digital supply is generated internally VTEST ≅ V+ - 4.5V • INTEGRATE CAPACITOR ( t INT ) ( I INT ) C INT = ------------------------------V INT • INTEGRATOR OUTPUT VOLTAGE SWING ( t INT ) ( I INT ) V INT = ------------------------------C INT • ICL7126 DISPLAY: LCD Type: Direct drive with digital logic supply amplitude • VINT MAXIMUM SWING: (V- + 0.5V) < VINT < (V+ - 0.5V), VINT (Typ) = 2V Typical Integrator Amplifier Output Waveform (INT Pin) AUTO ZERO PHASE (COUNTS) 2999 - 1000 SIGNAL INTEGRATE PHASE FIXED 1000 COUNTS DE-INTEGRATE PHASE 0 - 1999 COUNTS TOTAL CONVERSION TIME = 4000 x tCLOCK = 16,000 x tOSC 5 FN3084.5 ICL7126 Detailed Description De-integrate Phase The final phase is de-integrate, or reference integrate. Input low is internally connected to analog COMMON and input high is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator to output to return to zero. The time required for the output to return to zero is proportional to the input signal. Analog Section Figure 4 shows the Functional Diagram of the Analog Section for the ICL7126. Each measurement cycle is divided into three phases. They are (1) auto-zero (A-Z), (2) signal integrate (INT) and (3) de-integrate (DE). Auto-Zero Phase During auto-zero three things happen. First, input high and low are disconnected from the pins and internally shorted to analog COMMON. Second, the reference capacitor is charged to the reference voltage. Third, a feedback loop is closed around the system to charge the auto-zero capacitor CAZ to compensate for offset voltages in the buffer amplifier, integrator, and comparator. Since the comparator is included in the loop, the A-Z accuracy is limited only by the noise of the system. In any case, the offset referred to the input is less than 10µV. Specifically, the digital reading displayed is: VIN Display Count = 1000 --------------- . VREF Differential Input The input can accept differential voltages anywhere within the common mode range of the input amplifier, or specifically from 0.5V below the positive supply to 1V above the negative supply. In this range, the system has a CMRR of 86dB typical. However, care must be exercised to assure the integrator output does not saturate. A worst case condition would be a large positive common mode voltage with a near full-scale negative differential input voltage. The negative input signal drives the integrator positive when most of its swing has been used up by the positive common mode voltage. For these critical applications the integrator output swing can be reduced to less than the recommended 2V full scale swing with little loss of accuracy. The integrator output can swing to within 0.5V of either supply without loss of linearity. Signal Integrate Phase During signal integrate, the auto-zero loop is opened, the internal short is removed, and the internal input high and low are connected to the external pins. The converter then integrates the differential voltage between IN HI and IN LO for a fixed time. This differential voltage can be within a wide common mode range: up to 1V from either supply. If, on the other hand, the input signal has no return with respect to the converter power supply, IN LO can be tied to analog COMMON to establish the correct common mode voltage. At the end of this phase, the polarity of the integrated signal is determined. CREF RINT CREF+ REF HI 34 36 V+ REF LO 35 A-Z CREF33 28 A-Z CAZ BUFFER V+ 1 CINT A-Z INT 29 27 INTEGRATOR - + 1µA - + 2.8V 31 + TO DIGITAL SECTION IN HI DE- INT DE+ 6.2V INPUT HIGH A-Z A-Z DE+ 32 COMPARATOR + N - DE- COMMON INPUT LOW A-Z AND DE(±) 30 IN LO INT 26 V- FIGURE 4. ANALOG SECTION OF ICL7126 6 FN3084.5 ICL7126 V+ V+ V+ V+ REF HI 6.8V ZENER REF LO 27kΩ 200kΩ ICL7126 ICL7126 IZ REF HI REF LO ICL8069 1.2V REFERENCE COMMON V- FIGURE 5B. FIGURE 5A. FIGURE 5. Differential Reference The reference voltage can be generated anywhere within the power supply voltage of the converter. The main source of common mode error is a roll-over voltage caused by the reference capacitor losing or gaining charge to stray capacity on its nodes. If there is a large common mode voltage, the reference capacitor can gain charge (increase voltage) when called up to de-integrate a positive signal but lose charge (decrease voltage) when called up to de-integrate a negative input signal. This difference in reference for positive or negative input voltage will give a roll-over error. However, by selecting the reference capacitor large enough in comparison to the stray capacitance, this error can be held to less than 0.5 count worst case. (See Component Value Selection.) Analog COMMON COMMON, a common mode voltage exists in the system and is taken care of by the excellent CMRR of the converter. However, in some applications IN LO will be set at a fixed known voltage (power supply common for instance). In this application, analog COMMON should be tied to the same point, thus removing the common mode voltage from the converter. The same holds true for the reference voltage. If reference can be conveniently tied to analog COMMON, it should be since this removes the common mode voltage from the reference system. Within the lC, analog COMMON is tied to an N channel FET that can sink approximately 3mA of current to hold the voltage 2.8V below the positive supply (when a load is trying to pull the common line positive). However, there is only 1µA of source current, so COMMON may easily be tied to a more negative voltage thus overriding the internal reference. This pin is included primarily to set the common mode voltage for battery operation or for any system where the input signals are floating with respect to the power supply. The COMMON pin sets a voltage that is approximately 2.8V more negative than the positive supply. This is selected to give a minimum end-of-life battery voltage of about 6.8V. However, analog COMMON has some of the attributes of a reference voltage. When the total supply voltage is large enough to cause the zener to regulate (<6.8V), the COMMON voltage will have a low voltage coefficient (0.001%/V), low output impedance (≅15Ω), and a temperature coefficient typically less than 80ppm/oC. The limitations of the on-chip reference should also be recognized, however. The reference Temperature Coefficient (TC), can cause some degradation in performance. Temperature changes of 2oC to 8oC, typical for instruments, can give a scale factor error of a count or more. Also the common voltage will have a poor voltage coefficient when the total supply voltage is less than that which will cause the zener to regulate (<7V). These problems are eliminated if an external reference is used, as shown in Figure 5. Analog COMMON is also used as the input low return during auto-zero and de-integrate. If IN LO is different from analog 7 FN3084.5 ICL7126 V+ V+ V+ BP 1MΩ TO LCD DECIMAL POINT ICL7126 BP TEST ICL7126 TO LCD DECIMAL POINTS DECIMAL POINT SELECT 21 TEST 37 TO LCD BACKPLANE FIGURE 6. SIMPLE INVERTER FOR FIXED DECIMAL POINT TEST The TEST pin serves two functions. It is coupled to the internally generated digital supply through a 500Ω resistor. Thus it can be used as the negative supply for externally generated segment drivers such as decimal points or any other presentation the user may want to include on the LCD display. Figures 6 and 7 show such an application. No more than a 1mA load should be applied. The second function is a “lamp test”. When TEST is pulled high (to V+) all segments will be turned on and the display should read “-1888”. The TEST pin will sink about 10mA under these conditions. V+ = DP ON GND = DP OFF CD4030 GND FIGURE 7. EXCLUSIVE ‘OR’ GATE FOR DECIMAL POINT DRIVE to 3000 counts). For signals less than full-scale, auto-zero gets the unused portion of reference de-integrate. This makes a complete measure cycle of 4,000 counts (16,000 clock pulses) independent of input voltage. For three readings/second, an oscillator frequency of 48kHz would be used. To achieve maximum rejection of 60Hz pickup, the signal integrate cycle should be a multiple of 60Hz. Oscillator frequencies of 60kHz, 48kHz, 40kHz, 331/3kHz, etc. should be selected. For 50Hz rejection, oscillator frequencies of 662/3kHz, 50kHz, 40kHz, etc. would be suitable. Note that 40kHz (2.5 readings/sec.) will reject both 50Hz and 60Hz (also 400Hz and 440Hz). CAUTION: In the lamp test mode, the segments have a constant DC voltage (no square-wave) and may burn the LCD display if left in this mode for several minutes. Digital Section Figure 8 shows the digital section for the ICL7126. An internal digital ground is generated from a 6V Zener diode and a large P-Channel source follower. This supply is made stiff to absorb the relative large capacitive currents when the back plane (BP) voltage is switched. The BP frequency is the clock frequency divided by 800. For three readings/second this is a 60Hz square wave with a nominal amplitude of 5V. The segments are driven at the same frequency and amplitude and are in phase with BP when OFF, but out of phase when ON. In all cases negligible DC voltage exists across the segments. The polarity indication is “ON” for negative analog inputs. If IN LO and IN HI are reversed, this indication can be reversed also, if desired. System Timing Figure 9 shows the clocking arrangement used in the ICL7126. Two basic clocking arrangements can be used: Figure 9A, an external oscillator connected to pin 40. Figure 9B, an R-C oscillator using all three pins. The oscillator frequency is divided by four before it clocks the decade counters. It is then further divided to form the three convert-cycle phases. These are signal integrate (1000 counts), reference de-integrate (0 to 2000 counts) and auto-zero (1000 8 FN3084.5 ICL7126 a f a b g b e c d BACKPLANE 21 LCD PHASE DRIVER 7 SEGMENT DECODE TYPICAL SEGMENT OUTPUT V+ 7 SEGMENT DECODE 7 SEGMENT DECODE ÷200 0.5mA LATCH SEGMENT OUTPUT 2mA 1000’s COUNTER 100’s COUNTER 10’s COUNTER 1’s COUNTER INTERNAL DIGITAL GROUND TO SWITCH DRIVERS FROM COMPARATOR OUTPUT 35 V+ CLOCK † THREE INVERTERS. ÷4 † ONE INVERTER SHOWN FOR CLARITY. 6.2V LOGIC CONTROL 500Ω TEST INTERNAL DIGITAL GROUND 37 VTH = 1V 26 40 OSC 1 39 OSC 2 38 1 V- HLDR OSC 3 FIGURE 8. DIGITAL SECTION INTERNAL TO PART INTERNAL TO PART ÷4 40 39 38 ÷4 CLOCK 40 39 38 R C CLOCK TEST ICL7126 FIGURE 9A. EXTERNAL SIGNAL FIGURE 9B. RC OSCILLATOR FIGURE 9. CLOCK CIRCUITS 9 FN3084.5 ICL7126 Component Value Selection Integrating Resistor Both the buffer amplifier and the integrator have a class A output stage with 6µA of quiescent current. They can supply ~1µA of drive current with negligible nonlinearity. The integrating resistor should be large enough to remain in this very linear region over the input voltage range, but small enough that undue leakage requirements are not placed on the PC board. For 2V full-scale, 1.8MΩ is near optimum and similarly a 180kΩ for a 200mV scale. Integrating Capacitor The integrating capacitor should be selected to give the maximum voltage swing that ensures tolerance build-up will not saturate the integrator swing (approximately. 0.3V from either supply). When the analog COMMON is used as a reference, a nominal ±2V full-scale integrator swing is fine. For three readings/second (48kHz clock) nominal values for ClNT are 0.047µF, for 1/s (16kHz) 0.15µF. Of course, if different oscillator frequencies are used, these values should be changed in inverse proportion to maintain the same output swing. The integrating capacitor should have a low dielectric absorption to prevent roll-over errors. While other types may be adequate for this application, polypropylene capacitors give undetectable errors at reasonable cost. At three readings/sec, a 750Ω resistor should be placed in series with the integrating capacitor, to compensate for comparator delay. VREF should equal 100mV and 1V, respectively. However, in many applications where the A/D is connected to a transducer, there will exist a scale factor other than unity between the input voltage and the digital reading. For instance, in a weighing system, the designer might like to have a full-scale reading when the voltage from the transducer is 0.682V. Instead of dividing the input down to 200mV, the designer should use the input voltage directly and select VREF = 0.341V. Suitable values for integrating resistor 330kΩ. This makes the system slightly quieter and also avoids a divider network on the input. Another advantage of this system occurs when a digital reading of zero is desired for VIN ≠ 0. Temperature and weighing systems with a variable fare are examples. This offset reading can be conveniently generated by connecting the voltage transducer between IN HI and COMMON and the variable (or fixed) offset voltage between COMMON and IN LO. Typical Applications The ICL7126 may be used in a wide variety of configurations. The circuits which follow show some of the possibilities, and serve to illustrate the exceptional versatility of these A/D converters. The following application notes contain very useful information on understanding and applying this part and are available from Intersil Corporation. Application Notes NOTE # DESCRIPTION AN016 “Selecting A/D Converters” AN017 “The Integrating A/D Converter” The size of the auto-zero capacitor has some influence on the noise of the system. For 200mV full-scale where noise is very important, a 0.32µF capacitor is recommended. On the 2V scale, a 0.33µF capacitor increases the speed of recovery from overload and is adequate for noise on this scale. AN018 “Do’s and Don’ts of Applying A/D Converters” AN023 “Low Cost Digital Panel Meter Designs” AN032 “Understanding the Auto-Zero and Common Mode Performance of the ICL7136/7/9 Family” AN046 “Building a Battery-Operated Auto Ranging DVM with the ICL7106” Reference Capacitor AN052 “Tips for Using Single-Chip 31/2 Digit A/D Converters” Auto-Zero Capacitor A 0.1µF capacitor gives good results in most applications. However, where a large common mode voltage exists (i.e., the REF LO pin is not at analog COMMON) and a 200mV scale is used, a larger value is required to prevent roll-over error. Generally 1µF will hold the roll-over error to 0.5 count in this instance. Oscillator Components For all ranges of frequency a 50pF capacitor is recommended and the resistor is selected from the approximation equation 0.45 f ∼ ----------- • For 48kHz clock (3 readings/sec), R = 180kΩ RC Reference Voltage The analog input required to generate full-scale output (2000 counts) is: VlN = 2VREF. Thus, for the 200mV and 2V scale, 10 FN3084.5 ICL7126 Typical Applications OSC 1 40 OSC 1 40 180kΩ OSC 3 38 OSC 3 38 SET VREF = 100mV 50pF TEST 37 TEST 37 10kΩ CREF 34 220kΩ CREF 34 0.1µF CREF 33 CREF 33 COMMON 32 1MΩ IN 0.01µF 0.33µF IN LO 30 - A-Z 29 + A-Z 29 180kΩ BUFF 28 BUFF 28 9V - INT 27 750kΩ V - 26 C3 24 TO DISPLAY A3 23 A3 23 G3 22 G3 22 BP/GND 21 BP/GND 21 TO BACKPLANE Values shown are for 200mV full scale, 3 readings/sec., floating supply voltage (9V battery). FIGURE 10. ICL7126 USING THE INTERNAL REFERENCE 0.33µF IN - 180kΩ 0.15µF V- OSC 2 39 100kΩ OSC 3 38 SET VREF = 1.000V 50pF TO DISPLAY IN LO is tied to COMMON, thus establishing the correct common mode voltage. COMMON acts as a pre-regulator for the reference. Values shown are for 1 reading/sec. OSC 1 40 180kΩ OSC 3 38 TEST 37 REF HI 36 100pF SET VREF = 100mV REF HI 36 V+ 35 V+ 250kΩ CREF 34 240kΩ CREF 33 COMMON 32 1MΩ IN HI 31 0.22µF A-Z 29 IN 0.1µF 1.2V (ICL8069) A-Z 29 BUFF 28 INT 27 1MΩ + IN HI 31 IN LO 30 - 1.8MΩ BUFF 28 1kΩ 10kΩ 15kΩ COMMON 32 + 0.01µF +5V V+ 35 CREF 34 0.1µF CREF 33 IN 0.01µF 0.47µF - 47kΩ INT 27 750Ω 0.047µF V - G2 25 V - 26 0.22µF G2 25 TO DISPLAY C3 24 A3 23 G3 22 BP/GND 21 + 0.01µF FIGURE 11. ICL7126 WITH AN EXTERNAL BAND-GAP REFERENCE (1.2V TYPE) OSC 2 39 A3 23 1MΩ G2 25 C3 24 C3 24 0.1µF INT 27 0.047µF G2 25 V - 26 V+ IN HI 31 IN LO 30 IN LO 30 SET VREF = 100mV 200kΩ 27kΩ COMMON 32 + IN HI 31 TEST 37 20kΩ V+ 35 V+ 35 OSC 1 40 50pF REF HI 36 REF HI 36 V - 26 560kΩ OSC 2 39 OSC 2 39 TO DISPLAY G3 22 TO BACK PLANE BP/GND 21 3 reading/s. For 1 reading/sec., delete 750Ω resistor, change CINT, ROSC to values of Figure 11. Since low TC zeners have breakdown voltages ~6.8V, diode must be placed across the total supply (10V). As in the case of Figure 12, IN LO may be tied to COMMON. FIGURE 12. RECOMMENDED COMPONENT VALUES FOR 2.0V FULL SCALE FIGURE 13. ICL7126 WITH ZENER DIODE REFERENCE 11 FN3084.5 ICL7126 Typical Applications (Continued) V+ OSC 1 40 OSC 2 39 OSC 1 40 † OSC 2 39 OSC 3 38 TEST 37 OSC 3 38 SET VREF = 100mV 50pF TEST 37 20kΩ 100kΩ CREF 34 CREF 34 27kΩ CREF 33 0.1µF CREF 33 1.2V (ICL8069) COMMON 32 1MΩ A-Z 29 IN HI 31 IN LO 30 IN 0.01µF 0.33µF A-Z 29 - BUFF 28 180kΩ BUFF 28 INT 27 V - 26 † A3 23 C3 24 A3 23 TO DISPLAY † TO DISPLAY G3 22 GND 21 G3 22 GND 21 0.33µF RINT G2 25 G2 25 C3 24 0.1µF COMMON 32 + IN HI 31 V - 26 V+ 35 +5V V+ 35 INT 27 50pF REF HI 36 REF HI 36 IN LO 30 † TO BACK PLANE TO BACK PLANE An external reference must be used in this application, since the voltage between V+ and V- is insufficient for correct operation of the internal reference. † indicates values depend on clock frequency. The resistor values within the bridge are determined by the desired sensitivity. † indicates values depend on clock frequency. FIGURE 14. ICL7126 OPERATED FROM SINGLE +5V SUPPLY FIGURE 15. ICL7126 MEASURING RATIOMETRIC VALUES OF QUAD LOAD CELL OSC 1 40 † OSC 2 39 OSC 3 38 SCALE FACTOR ADJUST 50pF TEST 37 REF HI 36 V+ 35 CREF 34 CREF 33 100kΩ 100kΩ 1MΩ 200kΩ 470kΩ 0.1µF COMMON 32 ZERO ADJUST 0.01µF 0.33µF A-Z 29 390kΩ BUFF 28 9V INT 27 - V - 26 SILICON NPN MPS 3704 OR SIMILAR + IN HI 31 IN LO 30 † G2 25 C3 24 A3 23 TO DISPLAY G3 22 BP 21 TO BACKPLANE A silicon diode-connected transistor has a temperature coefficient of about -2mV/oC. Calibration is achieved by placing the sensing transistor in ice water and adjusting the zeroing potentiometer for a 000.0 reading. The sensor should then be placed in boiling water and the scale-factor potentiometer adjusted for a 100.0 reading. FIGURE 16. ICL7126 USED AS A DIGITAL CENTIGRADE THERMOMETER 12 FN3084.5 ICL7126 Typical Applications (Continued) V+ TO LOGIC VCC 1 V+ OSC 1 40 2 D1 OSC 2 39 3 C1 OSC 3 38 4 B1 TEST 37 5 A1 REF HI 36 6 F1 REF LO 35 TO CREF 34 LOGIC GND CREF 33 7 G1 8 E1 COMMON 32 9 D2 O /RANGE U /RANGE CD4023 OR 74C10 10 C2 IN HI 31 11 B2 IN LO 30 12 A2 A-Z 29 13 F2 BUFF 28 14 E2 INT 27 15 D3 V- 26 16 B3 G2 25 17 F3 C3 24 18 E3 A3 23 19 AB4 G3 22 20 POL BP 21 V- CD4077 FIGURE 17. CIRCUIT FOR DEVELOPING UNDERRANGE AND OVERRANGE SIGNAL FROM ICL7126 OUTPUTS TO PIN 1 OSC 1 40 180kΩ OSC 2 39 10µF SCALE FACTOR ADJUST (VREF = 100mV FOR AC TO RMS) OSC 3 38 50pF TEST 37 5µF ICL7611 REF HI 36 10kΩ CREF 34 220kΩ AC IN 470kΩ 0.1µF CREF 33 2.2MΩ COMMON 32 10kΩ 1µF IN HI 31 1µF 10kΩ 1µF 4.3kΩ IN LO 30 0.22µF 0.22µF A-Z 29 + 180kΩ 10µF 750Ω 9V - BUFF 28 - 1N914 REF LO 35 100kΩ + INT 27 0.047µF V - 26 100pF (FOR OPTIMUM BANDWIDTH) G2 25 C3 24 A3 23 TO DISPLAY G3 22 BP 21 TO BACKPLANE Test is used as a common-mode reference level to ensure compatibility with most op amps. FIGURE 18. AC TO DC CONVERTER WITH ICL7126 13 FN3084.5 ICL7126 Die Characteristics DIE DIMENSIONS: PASSIVATION: 127 mils x 149 mils Type: PSG Nitride Thickness: 15kÅ ±3kÅ METALLIZATION: WORST CASE CURRENT DENSITY: Type: Al Thickness: 10kÅ ±1kÅ 9.1 x 104 A/cm2 Metallization Mask Layout ICL7126 E2 F2 A2 B2 C2 D2 E1 G1 F1 A1 (14) (13) (12) (11) (10) (9) (8) (7) (6) (5) D3 (15) (4) B1 B3 (16) (3) C1 F3 (17) E3 (18) (2) D1 AB4 (19) (1) V+ POL (20) (40) OSC 1 BP/GND (21) G3 (22) A3 (23) (39) OSC 2 C3 (24) G2 (25) (38) OSC 3 (37) TEST V- (26) 14 (27) (28) (29) (30) (31) (32) INT BUFF A/Z IN LO IN HI COMM (33) (34) CREF- CREF+ (35) (36) LO HI REF REF FN3084.5 ICL7126 Dual-In-Line Plastic Packages (PDIP) E40.6 (JEDEC MS-011-AC ISSUE B) N 40 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 SYMBOL -B- A2 -C- SEATING PLANE e B1 D1 A1 eC B 0.010 (0.25) M C A B S MAX NOTES - 0.250 - 6.35 4 0.015 - 0.39 - 4 A2 0.125 0.195 3.18 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.030 0.070 0.77 1.77 8 eA C 0.008 0.015 0.204 0.381 - D 1.980 2.095 D1 0.005 - A L D1 MIN A E BASE PLANE MAX A1 -AD MILLIMETERS MIN C eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 50.3 53.2 5 - 5 0.13 E 0.600 0.625 15.24 15.87 6 E1 0.485 0.580 12.32 14.73 5 e 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC 6 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. eB - 0.700 - 17.78 7 L 0.115 0.200 2.93 5.08 4 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. N 40 40 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 9 Rev. 0 12/93 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 15 FN3084.5