IDT ICS81006I

ICS81006I
VCXO-TO-LVCMOS OUTPUTS
GENERAL DESCRIPTION
FEATURES
The ICS81006I is a high performance, low jitter/
ICS
low phase noise VCXO and is a member of the
HiPerClockS™
HiPerClockS™ family of high performance clock
solutions from IDT. The ICS81006I works in
conjunction with a pullable crystal to generate
an output clock over the range of 12MHz - 40MHz and has
6 LVCMOS outputs, effectively integrating a fanout buffer
function.
• Six LVCMOS/LVTTL outputs, 20Ω nominal
output impedance
• Output Q5 can be selected for ÷1 or ÷2 frequency relative to
the crystal frequency
• Output frequency range: 12MHz to 40MHz
• Crystal pull range: ± 90ppm (typical)
• Synchronous output enable places outputs in High-Z state
The frequency of the VCXO is adjusted by the VC control
voltage input. The output range is ±100ppm around the
nominal crystal frequency. The VC control voltage range is
0 - V DD . The device is packaged in a small 4mm x 4mm
VFQFN package and is ideal for use on space constrained
boards typically encountered in ADSL/VDSL applications.
• On-chip filter on VIN to suppress noise modulation of VCXO
• VDD/VDDO combinations
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
• 4mm x 4mm 20 Lead VFQFN package is ideal for space
constrained designs
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
VCXO
Q2
XTAL_OUT
Q1
VDDO
20 19 18 17 16
15
XTAL_OUT
2
14
Q2
VDD
3
13
VDDO
VC
4
12
Q3
DIV_SEL_Q5
5
6
7
8
9
11
10
Q4
XTAL_IN
1
VDDO
Q1
XTAL_IN
Q5
Q0
LP Filter
Q0
OE0
SYNC
GND
VC
(Pullup)
OE1
OE0
PIN ASSIGNMENT
GND
BLOCK DIAGRAM
GND
GND
Q3
ICS81006I
Q4
0: ÷1
1: ÷2
DIV_SEL_Q5
OE1
20-Lead VFQFN
4mm x 4mm x 0.95 package body
K Package
Top View
Q5
(Pulldown)
(Pullup)
SYNC
IDT ™ / ICS™ VCXO-TO-LVCMOS OUTPUTS
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ICS81006I
VCXO-TO-6 LVCMOS OUTPUTS
TABLE 1. PIN DESCRIPTIONS
Number
3
Name
XTAL_IN,
XTAL_OUT
VDD
Power
4
VC
Input
1, 2
Type
Input
Description
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
Core supply pin.
Control voltage input.
Output divider select pin for Q5 output. When LOW, ÷1. When HIGH,
5
DIV_SEL_Q5 Input Pulldown
÷2, LVCMOS/LVTTL interface levels.
Output enable pin. When HIGH, Q5 output is enabled.
6
OE1
Input
Pullup
When LOW, forces Q5 to HiZ state. LVCMOS/LVTTL interface levels.
7 , 1 1, 1 5 , 1 9
GND
Power
Power supply ground.
8 , 1 0, 12,
Q5, Q4, Q3,
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Output
14, 16, 18
Q2, Q1, Q0
15Ω typical output impedance.
Power
Output supply pins.
9, 13, 17
VDDO
Output enable pin. When HIGH, Q0:Q4 outputs are enabled. When
20
OE0
Input
Pullup
LOW, forces Q0:Q4 to HiZ state. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
CPD
Test Conditions
Maximum
Units
VDD = VDDO = 3.465V
3
pF
VDD = 3.465V or 2.625V,
VDDO = 2.625V
4
pF
VDD = 3.465V or 2.625V,
VDDO = 2V
6
pF
OE0, OE1
Power Dissipation Capacitance
Minimum
Typical
4
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
ROUT
Output Impedance
IDT ™ / ICS™ VCXO-TO-LVCMOS OUTPUTS
VDDO = 3.3V
20
Ω
VDDO = 2.5V
25
Ω
VDDO = 1.8V
38
Ω
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ICS81006I
VCXO-TO-6 LVCMOS OUTPUTS
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5 V
Outputs, VO
-0.5V to VDD + 0.5V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause per manent damage to the
device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, θJA 60.4°C/W (0 mps)
Storage Temperature, TSTG
-65°C to 150°C
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 3.3V±5% = 2.5V±5% = 1.8V±0.2V, TA = -40°C TO 85°C
Symbol
Parameter
Minimum
Typical
Maximum
Units
VDD
Core Supply Voltage
Test Conditions
3.135
3.3
3.465
V
3.135
3.3
3.465
V
VDDO
Output Supply Voltage
2.375
2.5
2.625
V
1.6
1.8
2.0
V
IDD
Power Supply Current
50
mA
IDDO
Output Supply Current
20
mA
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V±5%, VDDO = 2.5V±5% = 1.8V±0.2V, TA = -40°C TO 85°C
Symbol
Parameter
VDD
Core Supply Voltage
Test Conditions
VDDO
Output Supply Voltage
IDD
Power Supply Current
IDDO
Output Supply Current
Minimum
Typical
Maximum
Units
2.375
2.5
2.625
V
2.375
2. 5
2.625
V
1.6
1.8
2.0
V
50
mA
20
mA
TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, TA = -40°C TO 85°C
Symbol
VIH
Parameter
Input High Voltage
OE0, OE1,
DIV_SEL_Q5
VIL
Input Low Voltage
VC
VCXO Control Voltage
IIH
Input High Current
Maximum
Units
2
VDD + 0.3
V
VDD = 2.5V ± 5%
1.7
VDD + 0.3
V
VDD = 3.3V ± 5%
-0.3
0. 8
V
VDD = 2.5V ± 5%
-0.3
0.7
V
0
VDD = 3.3V or 2.5V ± 5%
Typical
VDD
V
150
µA
5
µA
OE0, OE1
VDD = 3.3V or 2.5V ± 5%
DIV_SEL_Q5
VDD = 3.3V or 2.5V ± 5%
-5
µA
OE0, OE1
VDD = 3.3V or 2.5V ± 5%
-150
µA
VDD = 3.465V or 2.625V
-100
VDDO = 3.3V ± 5%
2.6
V
VDDO = 2.5V ± 5%
1.8
V
VDDO = 1.8V ± 0.2V
1.5
Input Low Current
II
Input Current of VC pin
VOL
Minimum
VDD = 3.3V ± 5%
DIV_SEL_Q5
IIL
VOH
Test Conditions
Output High Voltage;NOTE 1
Output Low Voltage;NOTE 1
100
µA
V
VDDO = 3.3V or 2.5V ± 5%
0.5
V
VDDO = 1.8V ± 0.2V
0.4
V
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement section, "Load Test Circuit" diagrams.
IDT ™ / ICS™ VCXO-TO-LVCMOS OUTPUTS
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VCXO-TO-6 LVCMOS OUTPUTS
TABLE 4A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
fOUT
Output Frequency
RMS Phase Jitter (Random);
NOTE 1
Q0:Q4
Output Skew;
NOTE 2, 3
Q0:Q5
tjit(Ø)
tsk(o)
t R / tF
Output Rise/Fall Time
Test Conditions
Minimum
Typical
Maximum
Units
12
19.44
40
MHz
Integration Range: 1kHz- 1MHz
0.35
DIV_SEL_Q5 = ÷1
20% to 80%
200
odc
Output Duty Cycle
44
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
ps
30
ps
100
ps
750
ps
56
%
TABLE 4B. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
fOUT
Output Frequency
RMS Phase Jitter (Random);
NOTE 1
Q0:Q4
Output Skew;
NOTE 2, 3
Q0:Q5
tjit(Ø)
tsk(o)
t R / tF
Output Rise/Fall Time
Test Conditions
Minimum
Typical
Maximum
Units
12
19.44
40
MHz
Integration Range: 1kHz- 1MHz
0.38
DIV_SEL_Q5 = ÷1
20% to 80%
300
odc
Output Duty Cycle
45
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
ps
20
ps
90
ps
800
ps
55
%
TABLE 4C. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C
Symbol
Parameter
fOUT
Output Frequency
RMS Phase Jitter (Random);
NOTE 1
Q0:Q4
Output Skew;
NOTE 2, 3
Q0:Q5
tjit(Ø)
tsk(o)
t R / tF
Output Rise/Fall Time
Test Conditions
Minimum
Typical
Maximum
Units
12
19.44
40
MHz
Integration Range: 1kHz-1MHz
0.27
DIV_SEL_Q5 = ÷1
20% to 80%
450
odc
Output Duty Cycle
45
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
IDT ™ / ICS™ VCXO-TO-LVCMOS OUTPUTS
4
ps
50
ps
180
ps
1400
ps
55
%
ICS81006AKI REV A OCTOBER 2, 2006
ICS81006I
VCXO-TO-6 LVCMOS OUTPUTS
TABLE 4D. AC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
fOUT
Output Frequency
RMS Phase Jitter (Random);
NOTE 1
Q0:Q4
Output Skew;
NOTE 2, 3
Q0:Q5
tjit(Ø)
tsk(o)
t R / tF
Output Rise/Fall Time
Test Conditions
Minimum
Typical
Maximum
Units
12
19.44
40
MHz
Integration Range: 1kHz-1MHz
0.28
ps
25
DIV_SEL_Q5 = ÷1
20% to 80%
300
odc
Output Duty Cycle
45
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
ps
105
ps
800
ps
55
%
TABLE 4E. AC CHARACTERISTICS, VDD = 2.5V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C
Symbol
Parameter
fOUT
Output Frequency
RMS Phase Jitter (Random);
NOTE 1
Q0:Q4
Output Skew;
NOTE 2, 3
Q0:Q5
tjit(Ø)
tsk(o)
t R / tF
Output Rise/Fall Time
Test Conditions
Minimum
Typical
Maximum
Units
12
19.44
40
MHz
Integration Range: 1kHz-1MHz
0.26
DIV_SEL_Q5 = ÷1
20% to 80%
450
odc
Output Duty Cycle
40
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
IDT ™ / ICS™ VCXO-TO-LVCMOS OUTPUTS
5
ps
40
ps
185
ps
1400
ps
60
%
ICS81006AKI REV A OCTOBER 2, 2006
ICS81006I
VCXO-TO-6 LVCMOS OUTPUTS
PARAMETER MEASUREMENT INFORMATION
1.65V±5%
2.05V±5%
1.25V±5%
SCOPE
VDD,
VDDO
SCOPE
VDD
Qx
VDDO
Qx
LVCMOS
GND
LVCMOS
GND
-1.65V±5%
-1.25V±5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
2.4V±0.065V
1.25V±5%
0.9V±0.1V
SCOPE
VDD
VDDO
SCOPE
VDD,
VDDO
Qx
Qx
LVCMOS
GND
LVCMOS
GND
-1.25V±5%
-0.9V±0.1V
3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
1.6V±0.025V
Phase Noise Plot
Noise Power
0.9V±0.1V
SCOPE
VDD
VDDO
Phase Noise Mask
Qx
GND
LVCMOS
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
-0.9V±0.1V
2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
IDT ™ / ICS™ VCXO-TO-LVCMOS OUTPUTS
RMS PHASE JITTER
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VCXO-TO-6 LVCMOS OUTPUTS
V
V
DD
DDO
Qx
2
2
Q0:Q5
t PW
t
V
DDO
Qy
2
t sk(o)
odc =
PERIOD
t PW
x 100%
t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT SKEW
Clock
Outputs
80%
80%
tR
tF
20%
20%
OUTPUT RISE/FALL TIME
IDT ™ / ICS™ VCXO-TO-LVCMOS OUTPUTS
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APPLICATION INFORMATION
VCXO CRYSTAL SELECTION
accuracy of a VCXO. Below are the key variables and an example
of using the crystal parameters to calculate the tuning range of
the VCXO.
Choosing a crystal with the correct characteristics is one of the
most critical steps in using a Voltage Controlled Crystal Oscillator
(VCXO). The crystal parameters affect the tuning range and
➤
VC
Oscillator
Control Voltage
CV
➤
➤C
V
VCXO (Internal)
XTAL
CS1
CS2
➤
CL1
Optional
➤
CL2
FIGURE 1: VCXO OSCILLATOR CIRCUIT
CL1, CL2 Load tuning capacitance used for fine tuning or
centering nominal frequency
VC Control voltage used to tune frequency
CV Varactor capacitance, varies due to the change in
control voltage
CS1, CS2 Stray Capacitance caused by pads, vias, and other
board parasitics
TABLE 5. EXAMPLE CRYSTAL PARAMETERS
Symbol
Parameter
fN
Nominal Frequency
fT
Frequency Tolerance
fS
Frequency Stability
Test Conditions
Minimum
Typical
Maximum
19.44
Operating Temperature Range
0
Units
MHz
±20
ppm
±20
ppm
70
°C
CL
Load Capacitance
12
pF
CO
Shunt Capacitance
4
pF
C0, C1
Pullability Ratio
ESR
Equivalent Series Resistance
220
20
Drive Level
1
Aging @ 25°C
±3 per year
Mode of Operation
IDT ™ / ICS™ VCXO-TO-LVCMOS OUTPUTS
240
mW
ppm
Fundamental
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VCXO-TO-6 LVCMOS OUTPUTS
TABLE 6. VARACTOR PARAMETERS
Symbol
Parameter
CV_LOW
Low Varactor Capacitance
Test Conditions
VC = 0V
Minimum
15.4
pF
CV_HIGH
High Varactor Capacitance
VC = 3.3V
29. 6
pF
FORMULAS
C Low =
(C
(C
L1
L1
+ C S 1 + CV _ Low ) ⋅ (C L 2 + C S 2 + CV _ Low )
C High =
+ C S 1 + CV _ Low ) + (C L 2 + C S 2 + CV _ Low )
(C
(C
L1
Typical
Maximum
Units
+ C S1 + CV _ High ) ⋅ (C L 2 + C S 2 + CV _ High )
L1 + C S 1 + CV _ High ) + (C L 2 + C S 2 + CV _ High )
• CLow is the effective capacitance due to the low varactor capacitance, load capacitance and stray capacitance.
CLow determines the high frequency component on the TPR.
• CHigh is the effective capacitance due to the high varactor capacitance, load capacitance and stray capacitance.
CHigh determines the low frequency component on the TPR.




1
1

 ⋅ 10 6
Total Pull Range (TPR ) =
−


C Low 
C



C
0
High
 2 ⋅ C 0 C 1 ⋅ 1 +
 2 ⋅ C 1 ⋅ 1 +

C
0
C
0





Absolute Pull Range (APR) = Total Pull Range – (Frequency Tolerance + Frequency Stability + Aging)
EXAMPLE CALCULATIONS
aging is ±15ppm. Third, though many boards will not require load
tuning capacitors (CL1, CL2), it is recommended for long-term
consistent performance of the system that two tuning capacitor
pads be placed into every design. Typical values for the load tuning
capacitors will range from 0 to 4pF.
Using the tables and figures above, we can now calculate the
TPR and APR of the VCXO using the example crystal parameters.
For the numerical example below there were some assumptions
made. First, the stray capacitance (CS1, CS2), which is all the excess
capacitance due to board parasitic, is 4pF. Second, the expected
lifetime of the project is 5 years; hence the inaccuracy due to
CLow =
(0 + 4 pf + 15.4 pf ) ⋅ (0 + 4 pf + 15.4 pf ) = 9.7 pf
(0 + 4 pf + 15.4 pf ) + (0 + 4 pf + 15.4 pf )
CHigh =
(0 + 4 pf + 29.6 pf ) ⋅ (0 + 4 pf + 29.6 pf ) = 16.8 pf
(0 + 4 pf + 29.6 pf ) + (0 + 4 pf + 29.6 pf )




1
1
 ⋅ 106 ⋅ = 226.5 ppm
−
TPR = 
 2 ⋅ 220 ⋅ 1 + 16.8 pF
 
 2 ⋅ 220 ⋅ 1 + 9.7 pF
4 pF 
4 pF  



TPR = ±113.25ppm
APR = 113.25ppm – (20ppm + 20ppm + 15ppm) = ±58.25ppm
The example above will ensure a total pull range of
±113.25 ppm with an APR of ±58.25ppm. Many times, board
designers may select their own cr ystal based on their
application. If the application requires a tighter APR, a crystal
IDT ™ / ICS™ VCXO-TO-LVCMOS OUTPUTS
with better pullability (C0/C1 ratio) can be used. Also, with the
equations above, one can vary the frequency tolerance,
temperature stability, and aging or shunt capacitance to achieve
the required pullability.
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VCXO-TO-6 LVCMOS OUTPUTS
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
INPUTS:
LVCMOS OUTPUT:
All unused LVCMOS output can be left floating. We recommend
that there is no trace attached.
CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used. The VC pin can not be
floated.
SCHEMATIC EXAMPLE
Figure 2 shows an example of ICS81006I application schematic.
The decoupling capacitors should be located as close as
possible to the power pin. For the LVCMOS 20Ω output drivers,
series termination example is shown in the schematic. Additional
termination approaches are shown in the LVCMOS Termination
Application Note.
Pull-up VDD
example
R4
1K
VDD
R1
Zo = 50
U1
1
2
3
4
5
XTAL
XTAL_IN
XTAL_OUT
VDD
VC
DIV_SEL_Q5
GND
Q2
VDDO
Q3
GND
15
14
13
12
11
OE1
GND
Q5
VDDO
Q4
C2
SPARE
81006I81006
Pull-down
example
6
7
8
9
10
VC
VC = 0V to VDD
30
OE0
GND
Q0
VDDO
Q1
C1
SPARE
20
19
18
17
16
Quartz crystal should be
placed as close to the
device as possible.
VDDO
R3
1K
R2
Zo = 50
VDD
30
R5
(U1-3)
(U1-9)
VDD
C7
10uf
1K
(U1-13)
(U1-17)
VDDO
C6
0.1uF
C5
0.1uF
C4
0.1uF
Unused outputs can be left floating. There should be
no trace attached to unused outputs. Device
characterized and specification limits set with all
outputs terminated.
C3
0.1uF
FIGURE 2. ICS81006I SCHEMATIC EXAMPLE
IDT ™ / ICS™ VCXO-TO-LVCMOS OUTPUTS
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VCXO-TO-6 LVCMOS OUTPUTS
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
FOR
20 LEAD VFQFN
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
3
60.4°C/W
52.8°C/W
46.0°C/W
TRANSISTOR COUNT
The transistor count for ICS81006I is: 983
IDT ™ / ICS™ VCXO-TO-LVCMOS OUTPUTS
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PACKAGE OUTLINE - K SUFFIX FOR 20 LEAD VFQFN
TABLE 8. PACKAGE DIMENSIONS FOR 20 LEAD VFQFN
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
MINIMUM
20
N
A
0.80
A1
0
1.0
0.05
0.25 Reference
A3
b
MAXIMUM
0.18
0.30
e
0.50 BASIC
ND
5
NE
5
D
4.0
D2
0.75
2.80
4.0
E
E2
0.75
2.80
L
0.35
0.75
Reference Document: JEDEC Publication 95, MO-220
IDT ™ / ICS™ VCXO-TO-LVCMOS OUTPUTS
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VCXO-TO-6 LVCMOS OUTPUTS
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS81006AKI
1006AI
20 lead VFQFN
tube
-40°C to 85°C
ICS81006AKIT
1006AI
20 lead VFQFN
2500 tape & reel
-40°C to 85°C
ICS81006AKILF
TBD
20 lead "Lead-Free" VFQFN
tube
-40°C to 85°C
ICS81006AKILFT
TBD
20 lead "Lead-Free" VFQFN
2500 tape & reel
-40°C to 85°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT ™ / ICS™ VCXO-TO-LVCMOS OUTPUTS
13
ICS81006AKI REV A OCTOBER 2, 2006
ICS81006I
VCXO-TO-6 LVCMOS OUTPUTS
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Singapore (1997) Pte. Ltd.
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England
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© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA