Datasheet

UNISONIC TECHNOLOGIES CO., LTD
UTDA8024
Preliminary
LINEAR INTEGRATED CIRCUIT
IC CARD INTERFACE

DESCRIPTION
The UTC UTDA8024 is analog interface IC for 3V or 5V smart
cards. It is placed between the card and the microcontroller to
perform communication, control function, all supply and protection
functions. It requires very few external components for
application. It can be applied in many fields, such as IC card
readers for banking, pay TV, Identification, Electronic payment,
etc.

TSSOP-28
FEATURES
* Three specifically protected half-duplex bidirectional buffered
I/O lines to card contacts C4, C7 and C8
* Automatic activation and deactivation sequences; initiated by
software or by hardware in the event of a short-circuit, card
take-off, overheating, VDD or VDDP drop-out
* 26MHz integrated crystal oscillator
* DC/DC converter for VCC generation separately powered from a
5 V ± 20% supply (VDDP and PGND)
* 3V or 5V ± 5% regulated card supply voltage (VCC) with
appropriate decoupling has the following capabilities:
- ICC<80mA at VDDP=4~6.5V
- Handles current spikes of 40nAs up to 20MHz
- Controls rise and fall times
- Filtered overload detection at approximately 120mA
* Built-in debounce on card presence contacts
* Supply supervisor for spike-killing during power-on and
power-off and Power-on reset (threshold fixed internally
or externally by a resistor bridge)
* Thermal and short-circuit protection on all card contacts
* Clock generation for cards up to 20MHz (divided by 1, 2, 4 or 8
through CLKDIV1 and CLKDIV2 signals) with synchronous
frequency changes
* Non-inverted control of RST via pin RSTIN
* ISO 7816, GSM11.11 and EMV (payment systems)
Compatibility
* Enhanced ESD protection on card side (>6kV)
* One multiplexed status signal OFF
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
Preliminary
LINEAR INTEGRATED CIRCUIT
ORDERING INFORMATION
Ordering Number
UTDA8024G-P28-R
UTDA8024G-P28-R
Package
TSSOP-28
(1)Packing Type
(1) R: Tape Reel
(2)Package Type
(2) P28: TSSOP-28
(3)Green Package
(3) G: Halogen Free and Lead Free

MARKING

PIN CONFIGURATION
CLKDIV1
1
28 AUX2UC
CLKDIV2
2
27 AUX1UC
5V/3V
3
26 I/OUC
PGND
4
25 XTAL2
S2
5
24 XTAL1
VDDP
6
23 OFF
S1
7
VUP
8
21 VDD
PRES
9
20 RSTIN
UTC UTDA8024
PRES 10
I/O 11
22 GND
19 CMDVCC
18 PORADJ
AUX2 12
17 VCC
AUX1 13
16 RST
CGND 14
15 CLK
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Packing
Tape Reel
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Preliminary
LINEAR INTEGRATED CIRCUIT
PIN DESCRIPTION

PIN NO.
1
2
PIN NAME
CLKDIV1
CLKDIV2
DESCRIPTION
3
5V/ 3 V
Card supply voltage selection input; VCC=5V (HIGH) or VCC=3V (LOW)
4
PGND
5
S2
6
VDDP
7
S1
8
VUP
DC/DC converter power supply ground
DC/DC converter capacitor; connected between pins S1 and S2; C=100nF with
ESR<100mΩ
DC/DC converter power supply voltage
DC/DC converter capacitor; connected between pins S1 and S2; C=100nF with
ESR<100mΩ
DC/DC converter output decoupling capacitor connection; C=100nF with ESR<100mW
must be connected between VUP and PGND
9
PRES
10
PRES
11
12
13
14
15
16
I/O
AUX2
AUX1
CGND
CLK
RST
17
VCC
18
PORADJ
19
CMDVCC
20
21
22
RSTIN
VDD
GND
23
OFF
CLK frequency selection input 1
CLK frequency selection input 2
Card presence contact input (active LOW); if PRES or PRES is active, the card is
considered ‘present’ and a built-in debounce feature of 8 ms (typ.) is activated
Card presence contact input (active HIGH); if PRES or PRES is active, the card is
considered ‘present’ and a built-in debounce feature of 8 ms (typ.) is activated
Data line to/from card reader contact C7; integrated 11kΩ pull-up resistor to VCC
Data line to/from card reader contact C8; integrated 11kΩ pull-up resistor to VCC
Data line to/from card reader contact C4; integrated 11kΩ pull-up resistor to VCC
Card signal ground
Card clock to/from card reader contact C3
Card reset output from card reader contact C2
Card supply voltage to card reader contact C1; decoupled to CGND via 2 × 100nF or
100+220nF capacitors with ESR<100mΩ; Note 1
Power-on reset threshold adjustment input for changing the reset threshold with an
external resistor bridge; doubles the width of the POR pulse when used
Input from the host to start activation sequence (active LOW)
Card reset input from the host
Supply voltage
Ground
NMOS interrupt output to the host (active LOW); 20kΩ integrated pull-up resistor to VDD
24
XTAL1
Crystal connection or input for external clock
25
XTAL2
Crystal connection (leave open-circuit if external clock source is used)
26
I/OUC
Host data I/O line; integrated 11kΩ pull-up resistor to VDD
27
AUX1UC
Auxiliary data line to/from the host; integrated 11kΩ pull-up resistor to VDD
28
AUX2UC
Auxiliary data line to/from the host; integrated 11 kΩ pull-up resistor to VDD
Note 1. The noise margin on VCC will be higher with the 220nF capacitor
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UTDA8024

Preliminary
LINEAR INTEGRATED CIRCUIT
BLOCK DIAGRAM
GND
22
I/OUC 26
I/O
TRANSCEIVER
11 I/O
AUX2UC 28
I/O
TRANSCEIVER
12 AUX2
AUX1UC 27
I/O
TRANSCEIVER
13 AUX1
XTAL2 25
OSCILLATOR
XTAL1 24
THERMAL
PROTECTION
EN3
CLK
9 PRES
CLOCK
CIRCUITRY
CLKDIV2 2
10 PRES
CLKDIV1 1
EN4
HORSEQ
SEQUENCER
5V/3V 3
EN5
CMDVCC 19
RSTIN 20
PVCC
OFF 23
EN2
CLOCK
BUFFER
15 CLK
RST
BUFFER
16 RST
VCC
GENERATOR
14 CGND
17 VCC
ALARM
POWER_ON
EN1 CLKUP
VOLTAGE SENSE
PORADJ 18
INTERNAL
REFERENCE
Vref
VDD
6
VDDP
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4 PGND
DC/DC CONVERTER
SUPPLY
21
8 VUP
INTERNAL OSCILLATOR
2.5 MHz
7
S1
5
S2
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
Preliminary
LINEAR INTEGRATED CIRCUIT
ABSOLUTE MAXIMUM RATING
PARAMETER
Supply Voltage
DC/DC Converter Supply Voltage
Voltage On Input and Output
Pins
Pins XTAL1, XTAL2, 5V/ 3 V ,
RSTIN, AUX1UC, AUX2UC,
I/OUC, CLKDIV1, CLKDIV2,
SYMBOL
VDD
VDDP
RATINGS
-0.3~+6.5
-0.3~+6.5
UNIT
V
V
VI, VO
-0.3~+6.5
V
VCARD
-0.3~+6.5
V
VN
-0.3~+6.5
V
-6~+6
kV
-2~+2
kV
CMDVCC , OFF and PORADJ
Voltage On Card Pins
Voltage On Other Pins
Electrostatic Discharge Voltage
Pins PRES, PRES , I/O, RST,
AUX1, AUX2 and CLK
Pins VUP, S1 and S2
Card Contacts in Typical
Application (Note 2)
Pins I/O, RST, VCC, AUX1, AUX2,
CLK, PRES and PRES
Human Body
All Pins (Note 2) Model
Machine Model
VESD
-200~+200
V
Maximum Junction Temperature
TJ(MAX)
150
°C
Storage Temperature
TSTG
-55~+150
°C
Notes: 1. Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
2. All card contacts are protected against any short-circuit with any other card contact.

THERMAL RESISTANCES CHARACTERISTICS
PARAMETER
Junction to Ambient
in Free Air
SYMBOL
θJA
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RATINGS
100
UNIT
K/W
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UTDA8024

Preliminary
LINEAR INTEGRATED CIRCUIT
ELECTRICAL CHARACTERISTICS
VDD=3.3V; VDDP=5V; TAMB=25°C; fXTAL=10MHz; all currents flowing into the IC are positive; see Note 1; unless
otherwise specified.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Temperature
Ambient Temperature
TAMB
-25
+85
°C
Supplies
Supply Voltage
VDD
2.7
6.5
V
DC/DC Converter Supply Voltage
Supply Current
DC/DC Converter Supply Current
Falling Threshold Voltage on VDD
Hysteresis of Threshold Voltage
Vth2
Pin PORADJ (Note 2)
External Rising Threshold Voltage
on VDD
External Falling Threshold Voltage
on VDD
Hysteresis of Threshold Voltage
Vth(ext)
Hysteresis of Threshold Voltage
Vth(ext) Variation with Temperature
Width of Internal Power-On
Reset Pulse
Leakage Current On Pin PORADJ
Total Power Dissipation
DC/DC converter
Clock Frequency
Threshold Voltage for Voltage
Doubler to Change to Voltage
Follower
Output Voltage On Pin VUP
(Average Value)
VDDP
IDD
IDDP
Vth2
Vhys2
Vth(ext)(rise)
Vth(ext)(fall)
Vhys(ext)
∆Vhys(ext)
tw
IL(PORADJ)
Ptot
fCLK
Vth(vd-vf)
VUP(av)
VCC=5V, ICC <50mA
4.0
VCC=5V, ICC <20mA
2.5
6.5
V
6.5
V
1.2
mA
1.5
mA
0.1
mA
10
mA
VCC=5V, ICC =80mA
200
mA
VCC=3V, ICC =65mA
100
mA
Card Inactive
Card Active, fCLK=fXTAL,
CL=30pF
Inactive Mode
active mode, fCLK=fXTAL,
CL=30Pf, ICC =0
No External Resistors at
Pin PORADJ, VDD Level Falling
No External Resistors at
Pin PORADJ
External Resistor Bridge at
Pin PORADJ, VDD Level Rising
External Resistor Bridge at
Pin POR ADJ, VDD Level
Falling
External Resistor Bridge at
Pin POR ADJ
External Resistor Bridge at
Pin PORADJ
No External Resistors at
Pin PORADJ
External Resistor Bridge at
Pin PORADJ
VPORADJ<0.5V
VPORADJ>1V
Continuous Operation,
TAMB=-25~+85°C
2.35
2.45
2.55
V
50
100
150
mV
1.240
1.28
1.310
V
1.190
1.22
1.26
V
30
60
90
mV
0.25
mV/K
4
8
12
ms
8
16
24
ms
-0.1
-1
4
10
+1
µA
µA
0.56
W
MHz
V
Card Active
5V Card
2.2
5.2
5.8
3.2
6.2
3V Card
3.8
4.1
4.4
V
VCC=5V
VCC=3V, VDDP=3.3V
5.2
3.5
5.7
3.9
6.2
4.3
V
V
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
Preliminary
LINEAR INTEGRATED CIRCUIT
ELECTRICAL CHARACTERISTICS (Cont.)
PARAMETER
SYMBOL
TEST CONDITIONS
Card supply voltage (pin VCC) (Note 3)
External Capacitance On Pin VCC
CVCC
Note 4
Card Inactive,
ICC =0mA
Card Inactive,
ICC =1mA
Card Active,
ICC <50mA
5V Card
Card Active, Single
Current Pulse,
Ip=-100mA, tp=2ms
Card Active, Current
Pulses, Ip=40nA
Card Active, Current
Pulses, Ip=40nA with
ICC <200mA,
Card Supply Voltage
(Including Ripple Voltage)
tp<400ns
Card Inactive,
VCC
ICC =0mA
Card Inactive,
ICC =1mA
Card Active,
ICC <50mA
3V Card
Card Active, Single
Current Pulse,
Ip=-100mA, tp=2ms
Card Active, Current
Pulses, Ip=40nA
Card Active, Current
Pulses, Ip=40nA with
ICC <200mA,
MIN
TYP
80
MAX
UNIT
400
nF
-0.1
0
+0.1
V
-0.1
0
+0.3
V
4.75
5.0
5.25
V
4.65
5.0
5.25
V
4.65
5.0
5.25
V
4.65
5.0
5.25
V
-0.1
0
+0.1
V
-0.1
0
+0.3
V
2.85
3.0
3.15
V
2.76
3.0
3.20
V
2.76
3.0
3.20
V
2.76
3.0
3.20
V
350
mV
80
65
150
0.22
mA
mA
mA
V/µs
15
pF
2
0
26
26
MHz
MHz
-0.3
+0.3VDD
V
0.7VDD
VDD+0.3
V
tp<400ns
Ripple Voltage on VCC
(Peak to Peak Value)
Card Supply Current
VCC(ripple)(p-p) fripple=20kHz~200MHz
ICC
Slew Rate
SR
Crystal oscillator (pins XTAL1 and XTAL2)
External Capacitance On Pins CXTAL1,
XTAL1 and XTAL2
CXTAL2
Crystal Frequency
fXTAL
Frequency Applied on Pin XTAL1
fXTAL1
LOW-Level Input Voltage On Pin
VIL
XTAL1
HIGH-Level Input Voltage On Pin
VIH
XTAL1
VCC=0~5V
VCC=0~3V
VCC Short-Circuit to GND
Slew Up or Down
Depends On Type of Crystal or
Resonator Used
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0.08
120
0.15
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UTDA8024

Preliminary
LINEAR INTEGRATED CIRCUIT
ELECTRICAL CHARACTERISTICS (Cont.)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Data lines (pins I/O, I/OUC, AUX1, AUX2, AUX1UC and AUX2UC)
I/O to I/OUC, I/OUC to I/O Falling
td(I/O-I/OUC),
200
ns
Edge Delay
td(I/OUC-I/O)
Active Pull-Up Pulse Width
tpu
100
ns
Maximum Frequency On Data
fI/O(max)
1
MHz
Lines
Input Capacitance On Data Lines
Ci
10
pF
Data lines to card reader (pins I/O, AUX1 and AUX2; with integrated 11kΩ pull-up resistors to VCC)
No Load
0
0.1
V
Output Voltage
Vo(inactive) Inactive Mode
0.3
V
Io(inactive)=1mA
Output Current
Io(inactive) Inactive Mode, Pin Grounded
-1
mA
IOL=1mA
0
0.3
V
LOW-Level Output Voltage
VOL
IOL≥15mA
VCC-0.4
VCC
V
No DC Load
0.9VCC
VCC+0.1
V
5 and 3V Cards, IOH<-40µA
0.75VCC
VCC+0.1
V
HIGH-Level Output Voltage
VOH
IOH ≥10mA
0
0.4
V
0.3
1.5
0.8
VCC+0.3
V
V
LOW-Level Input Voltage
HIGH-Level Input Voltage
VIL
VIH
LOW-Level Input Current
IIL
VIL=0V
600
µA
HIGH-Level Input Leakage Current
ILIH
VIH=VCC
10
µA
Data Input Transition Time
tt(DI)
1.2
µs
Data Output Transition Time
tt(DO)
VIL(max) to VIH(min)
Vo=0~VCC, CL≤80pF,
10% to 90%
Pull-Up Resistor to VCC
VOH=0.9VCC, C=80pF
0.1
µs
Integrated Pull-Up Resistor
Rpu
Current When Pull-Up Active
Ipu
-1
Data lines to microcontroller
(pins I/OUC, AUX1UC and AUX2UC; with integrated 11kΩ pull-up resistors to VDD)
LOW-Level Output Voltage
VOL
IOL=1mA
0
No DC Load
0.9VDD
HIGH-Level Output Voltage
VOH
0.75VDD
5 and 3V Cards, IOH<-40µA
LOW-Level Input Voltage
VIL
-0.3
HIGH-Level Input Voltage
VIH
0.7VDD
HIGH-Level Input Leakage Current
LOW-Level Input Current
kΩ
mA
0.3
VDD+0.1
VDD+0.1
+0.3VDD
VDD+0.3
V
V
V
V
V
ILIH
VIH=VDD
10
µA
IL
VIL=0V
600
µA
1.2
kΩ
µs
0.1
µs
Integrated Pull-Up Resistor
Data Input Transition Time
Rpu
tt(DI)
Data Output Transition Time
tt(DO)
Current When Pull-Up Active
Internal oscillator
Ipu
Frequency of Internal Oscillator
18
fOSC(int)
Pull-Up Resistor to VCC
VIL(max) to VIH(min)
Vo=0~VDD, CL<30pF,
10% to 90%
VOH=0.9VDD, C=30pF
18
-1
Inactive Mode
Active Mode
55
2.2
mA
140
2.7
200
3.2
kHz
MHz
0.1
0.3
-1
2
V
V
mA
µs
Reset output to card reader (pin RST)
Output Voltage
Output Current
RSTIN to RST Delay
Vo(inactive)
Io(inactive)
td(RSTIN-RST)
No Load
Io(inactive)=1mA
Inactive Mode, Pin Grounded
RST Enabled
Inactive Mode
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0
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UTDA8024

Preliminary
LINEAR INTEGRATED CIRCUIT
ELECTRICAL CHARACTERISTICS (Cont.)
PARAMETER
SYMBOL
LOW-Level Output Voltage
VOL
HIGH-Level Output Voltage
VOH
Rise Time
tr
Fall Time
tf
Clock output to card reader (pin CLK)
TEST CONDITIONS
IOL=200µA
IOL=20mA (Current Limit)
IOH=-200µA
IOH=-20mA (Current Limit)
CL=100pF, VCC=5 or 3V
CL=100pF, VCC=5 or 3V
MIN
0
VCC-0.4
0.9VCC
0
TYP
No Load
0
0
Io(inactive)=1mA
Output Current
Io(inactive) CLK Inactive, Pin Grounded
0
IOL=200µA
0
LOW-Level Output Voltage
VOL
IOL=70mA (Current Limit)
VCC-0.4
IOH=-200µA
0.9VCC
HIGH-Level Output Voltage
VOH
IOLH=-70mA (Current Limit)
0
Rise Time
tr
CL=30pF, Note 5
Fall Time
tf
CL=30pF, Note 5
Duty Factor (Except for fXTAL)
δ
CL=30pF, Note 5
45
Slew Rate
SR
Slew Up or Down, CL=30pF
0.2
Control inputs (pins CLKDIV1, CLKDIV2, CMDVCC, RSTIN and 5V/3V) (Note 6)
LOW-Level Input Voltage
VIL
-0.3
HIGH-Level Input Voltage
VIH
0.7VDD
Output Voltage
Vo(inactive)
Inactive Mode
MAX
0.2
VCC
VCC
0.4
0.1
0.1
UNIT
V
V
V
V
µs
µs
0.1
0.3
-1
0.3
VCC
VCC
0.4
16
16
55
V
V
mA
V
V
V
V
ns
ns
%
V/ns
+0.3VDD
VDD+0.3
V
V
LOW-Level Input Leakage Current
ILIL
0<VIL<VDD
1
µA
HIGH-Level Input Leakage Current
ILIH
0<VIH<VDD
1
µA
+0.3VDD
VDD+0.3
V
V
Card presence inputs (pins PRES and PRES) (Note 7)
LOW-Level Input Voltage
VIL
HIGH-Level Input Voltage
VIH
-0.3
0.7VDD
LOW-Level Input Leakage Current
ILIL
0<VIL<VDD
5
µA
HIGH-Level Input Leakage Current
ILIH
0<VIH<VDD
5
µA
0.3
Interrupt output (pin OFF; NMOS drain with integrated 20kΩ pull-up resistor to VDD)
LOW-Level Output Voltage
VOL
IOL=2mA
0
HIGH-Level Output Voltage
VOH
IOH=-15µA
0.75VDD
Integrated Pull-Up Resistor
Rpu
20kΩ Pull-Up Resistor to VDD
16
Protection and limitation
Shutdown and Limitation Current
ICC( sd)
pin VCC
Limitation Current Pins I/O, AUX1
II/O(lim)
-15
and AUX2
Limitation Current Pin CLK
ICLK(lim)
-70
Limitation Current Pin RST
IRST(lim)
-20
Shut-Down Temperature
Tsd
Timing
Activation Time
tact
see Fig.1
50
Deactivation Time
tde
see Fig.3
50
Start of the Window for Sending
t3
see Fig.1&2
50
CLK to the Card
End of the Window for Sending
t5
see Fig.1&2
140
CLK to the Card
Debounce Time Pins PRES
tdebounce see Fig.4
5
And PRES
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20
24
V
V
kΩ
130
150
mA
+15
mA
+70
+20
mA
mA
°C
220
100
µs
µs
130
µs
220
µs
11
ms
150
80
8
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
Preliminary
LINEAR INTEGRATED CIRCUIT
ELECTRICAL CHARACTERISTICS (Cont.)
Notes: 1. All parameters remain within limits but are tested only statistically for the temperature range. When a
parameter is specified as a function of VDD or VCC it means their actual value at the moment of
measurement.
2. If no external bridge is used then, to avoid any disturbance, it is recommended to connect pin 18 to
ground.
3. To meet these specifications, pin VCC should be decoupled to CGND using two ceramic multilayer
capacitors of low ESR both with values of 100nF, or one 100nF and one 220nF (see Fig. 6)
4. Permitted capacitor values are 100, or 100 + 100, or 220, or 220 + 100, or 330nF.
t
5. Transition time and duty factor definitions are shown in Fig.5, δ = 1
t1 + t 2
6. Pin CMDVCC is active LOW; pin RSTIN is active HIGH; for CLKDIV1 and CLKDIV2 functions see Table
1.
7. Pin PRES is active LOW; pin PRES is active HIGH; PRES has an integrated 1.25µA current source to
GND (PRES to VDD); the card is considered present if at least one of the inputs PRES or PRES is active.
CLKDIV1
Table 1 Clock frequency selection (Note)
CLKDIV2
0
0
0
1
1
1
fCLK
fXTAL
8
fXTAL
4
fXTAL
2
1
0
fXTAL
Note: The status of pins CLKDIV1 and CLKDIV2must not be changed simultaneously; a delay of 10ns minimum
between changes is needed; the minimum duration of any state of CLK is eight periods of XTAL1.
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QW-R113-014.a
UTDA8024

Preliminary
LINEAR INTEGRATED CIRCUIT
TIMING WAVEFORMS
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11 of 15
QW-R113-014.a
UTDA8024

Preliminary
LINEAR INTEGRATED CIRCUIT
TIMING WAVEFORMS (Cont.)
CMDVCC
RST
CLK
I/O
VCC
VUP
t12
tde
t10
t13
t14
t15
Fig.3 Deactivation Sequence
PRES
OFF
CMDVCC
debounce
debounce
VCC
deactivation caused by
cards withdrawal
deactivation caused by
short-circuit
Fig. 4 Behaviour of OFF, CMDVCC, PRES and VCC.
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
12 of 15
QW-R113-014.a
UTDA8024

Preliminary
LINEAR INTEGRATED CIRCUIT
TIMING WAVEFORMS (Cont.)
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
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QW-R113-014.a
UTDA8024

Preliminary
LINEAR INTEGRATED CIRCUIT
TYPICAL APPLICATION CIRCUIT
Notes: 1. These capacitors must be of the low ESR-type and be placed near the IC (within 100mm).
2. UTC UTDA8024 and the microcontroller must use the same VDD supply.
3. Make short, straight connections between CGND, C5 and the ground connection to the capacitor.
4. Mount one low ESR-type 100nF capacitor close to pin VCC.
5. Mount one low ESR-type 100 or 220nF capacitor close to C1 contact (less than 100mm from it).
6. The connection to C3 should be routed as far from C2, C7, C4 and C8 and, if possible, surrounded by
grounded tracks.
7. Optional resistor bridge for changing the threshold of VDD. If this bridge is not required pin 18 should be
connected to ground.
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
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QW-R113-014.a
UTDA8024
Preliminary
LINEAR INTEGRATED CIRCUIT
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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www.unisonic.com.tw
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QW-R113-014.a
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