Datasheet

UNISONIC TECHNOLOGIES CO., LTD
UTRS3082
Preliminary
CMOS IC
FAIL-SAFE, 115KBPS, RS-485 /
RS-422 TRANSCEIVERS WITH
±12KV ESD-PROTECTED

DESCRIPTION
The UTC UTRS3082 is a half-duplex transceiver designed for
RS-485 data bus network, which contains one transmitter and one
receiver. The UTC UTRS3082 features a fail-safe receiver, which
guarantees the receiver to output high when the receiver inputs are
open, short or idle.
The UTC UTRS3082 also features a hot-swap glitch free protection
circuits which guarantee outputs of both the transmitter and the
receiver in a high impedance state during the power up period. So that
the large short current from power to ground will be disable by glitch
free function, which will save the power and enhance the efficiency of
the power up.
The UTC UTRS3082 is optimized for signal rates up to 115Kbps
with differential voltage of 2.3V. The UTC UTRS3082 also has the
thermal shutdown function when the temperature is over 150℃ and
the protection of the current limitation in the transmitter to protect the
itself from the damage by the system-fault conditions during normal
operation.

SOP-8
FEATURES
* Meet the requirements of the EIA/TIA-485 standards.
* 5.0V single power supply.
* 1µA low-current shutdown mode.
* HBM ±12kV ESD protection.
* True fail-safe receiver while maintaining EIA/TIA-485 compatibility.
* Hot-swap glitch free protection on control inputs.
* Up to 256 transceivers on the bus.
* Maximum baud rate up to 115Kbps.
* Transmitter short circuit current limit.
* Thermal shutdown for overload protection.

ORDERING INFORMATION
Ordering Number
UTRS3082G-S08-R
Package
SOP-8
Packing
Tape Reel
UTRS3082G-S08-R
(1)Packing Type
(1) R: Tape Reel
(2)Package Type
(2) S08: SOP-8
(3)Green Package
(3) G: Halogen Free and Lead Free
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Copyright © 2016 Unisonic Technologies Co., Ltd
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Preliminary

MARKING

PIN CONFIGURATION
RO 1
8 VCC
REB 2
7 B
DE 3
6 A
DI 4

CMOS IC
5 GND
PIN DESCRIPTION
PIN NO.
1
PIN NAME
RO
2
REB
3
DE
4
DI
5
6
7
8
GND
A
B
VCC
DESCRIPTION
Receiver output.
Receiver output enable: REB is low to enable the Receiver; REB is high to disable the
Receiver.
Transmitter output enable: DE is high to enable the transmitter; DE is low to disable the
transmitter.
Transmitter input: When DE is high, a low on DI forces An output low and B output high.
Similarly, a high on DI forces An output high and B output low.
Ground pin. Must be connected to 0V.
Non-inverting receiver input and non-inverting transmitter output
Inverting receiver input and inverting transmitter output
Power supply input 5.0V.
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
Preliminary
CMOS IC
BLOCK DIAGRAM
RO 1
RX
8 VCC
REB 2
7
B
DE 3
6
A
DI 4
TX
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5 GND
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
Preliminary
CMOS IC
ABSOLUTE MAXIMUM RATING
PARAMETER
SYMBOL
RATINGS
UNIT
Power Supply VCC
VCC
-0.3 ~ 7.0
V
Control Input Voltage
REB, DE
-0.3 ~ (VCC+0.3)
V
Receiver Input Voltage
A, B
±12.5
V
Receiver Output Voltage
RO
-0.3 ~ (VCC+0.3)
V
Transmitter Output Voltage
A, B
±12.5
V
Transmitter Input
DI
-0.3 ~ (VCC+0.3)
V
Operating Temperature
TOP
-40 ~ +85
°C
Storage Temperature
TSTG
-65 ~ +150
°C
Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.

DC ELECTRICAL CHARACTERISTICS
(VCC=5.0V ±5% with TAMB= TMIN to TMAX, unless otherwise noted. Typical values are at VCC=5.0V and TA=25°C.)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP MAX UNIT
TRANSMITTER
Differential Transmitter Output
VOD1
No Load
5.0
V
Differential Transmitter Output
VOD2
Fig.1, RL=27Ω
1.5
V
Change in Magnitude of
∆VOD
Fig.1, RL=27Ω
0.2
V
Differential Output Voltage
Transmitter Common- Mode
VOC
Fig.1, RL=27Ω
3.0
V
Output Voltage
Change in Magnitude of
∆VOC
Fig.1, RL=27Ω
0.2
V
Common- Mode Voltage
Input High Voltage
VIH
DE, DI, REB
2.0
V
Input Low Voltage
VIL
DE, DI, REB
0.8
V
Input Current
IIN1
DI
±1.0
µA
Input Current
IIN2
DE, REB
±50
µA
DI Input Hysteresis
VHYS
100
mV
DE=GND,
VIN=12V
125
µA
Input Current (A and B)
IIN3
VCC=GND or 5.25V VIN=-7V
-75
µA
Transmitter Short-Circuit
-7V≤VOUT≤VCC
-250
mA
IOS
Output Current
0V≤VOUT≤12V
250
mA
RECEIVER
Receiver Differential Threshold
VTH
-7V≤VCM≤+12V
-300
300
mV
Voltage
Receiver Input Hysteresis
∆VTH
25
mV
Receiver Output High Voltage
VOH
IO=-4mA, VID=-50mV
V
VCC-1.5
Receiver Output Low Voltage
VOL
IO=4mA, VID=-200mV
0.5
V
Three- State Output Current at
IOZR
0.4V≤VCM≤2.4V
±1.0
µA
Receiver
Receiver Input Resistance
RIN
-7V≤VCM≤+12V
96
kΩ
Receiver Output Short-Circuit
IOSR
Fig.6 , 0V≤VRO≤VCC
±7
±95
mΑ
Current
SUPPLY CURRENT
No Load,
DE=VCC
420
900
µA
Supply Current
ICC
REB=GND,
DE=GND
320
600
µA
DI=VCC or GND.
Supply Current in Shutdown
ISHDN
REB=VCC, DE=GND
1.0
10
µA
Mode
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
Preliminary
CMOS IC
SWITCHING CHARACTERISTICS
(VCC=5.0V ±5% with TA= TMIN to TMAX, unless otherwise noted. Typical values are at VCC=5.0V and TAMB=25°C.)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP MAX UNIT
Transmitter Input to Output
tDPLH, tDPHL Fig.2 and 7, RDIFF=54Ω, CL1=CL2=100pF
980
2600
ns
Transmitter Output Skew
tDSKEW
Fig.2 and 7, RDIFF=54Ω, CL1=CL2=100pF
10
ns
| tDPLH - tDPHL |
Transmitter Rise or Fall Time
tDF, tDR Fig.2 and 7, RDIFF=54Ω, CL1=CL2=100pF
1500 2500
ns
Maximum Data Rate
fMAX
115
Kbps
Transmitter Enable to Output
tDZL
Fig.4 and 8, CDL=100pF, S1 Closed
3500
ns
Low
Transmitter Enable to Output
tDZH
Fig.4 and 8, CDL=100pF, S2 Closed
3500
ns
High
Transmitter Disable Time
tDLZ
Fig.4 and 8, CDL=15pF, S1 Closed
500
ns
from Low
Transmitter Disable Time
tDHZ
Fig.4 and 8, CDL=15pF, S2 Closed
500
ns
from High
Fig.5 and 9 , |VID|≥2.0V; Rise and Fall
200
ns
Receiver Input to Output
tRPLH, tRPHL
Time of VID≤15ns
Fig.5 and 9 , |VID|≥2.0V; Rise and Fall
| tRPLH – tRPHL | Different
tRSKD
100
ns
Receiver Skew
Time of VID≤15ns
Receiver Enable to Output
tRZL
Fig.3 and 10, CRL=100pF, S1 Closed
50
ns
Low
Receiver Enable to Output
tRZH
Fig.3 and 10, CRL=100pF, S2 Closed
50
ns
High
Receiver Disable Time from
tRLZ
Fig.3 and 10, CRL=100pF, S1 Closed
50
ns
Low
Receiver Disable Time from
tRHZ
Fig.3 and 10, CRL=100pF, S2 Closed
50
ns
High
Time to Shutdown
tSHDN
500
ns
Transmitter Enable from
tDZL(SHDN) Fig.4 and 8, CDL=15pF, S1 Closed
500
5500
ns
Shutdown to Output Low
Transmitter Enable from
tDZH(SHDN) Fig.4 and 8, CDL=15pF, S2 Closed
500
5500
ns
Shutdown to Output High
Receiver Enable from
tRZL(SHDN) Fig.3 and 10, CRL=100pF, S1 Closed
1500 4500
ns
Shutdown to Output Low
Receiver Enable from
tRZH(SHDN) Fig.3 and 10, CRL=100pF, S2 Closed
1500 4500
ns
Shutdown to Output High
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
Preliminary
CMOS IC
FUNCTION TABLE
TRANSMITTING
REB
X
X
0
1
INPUTS
DE
1
1
0
0
OUTPUTS
DI
0
1
X
X
A
0
1
High-Z
B
1
0
High-Z
Shutdown
RECEIVING
INPUTS
DE
X
X
X
1
0
REB
A-B
0
≥ -0.05V
0
≤ -0.2V
0
Open/Shorted
1
X
1
X = Don’t care
Shutdown mode, transmitter and receiver outputs high impedance
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OUTPUT
RO
1
0
1
High-Z
Shutdown
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Preliminary
CMOS IC
TEST CIRCUIT

A
1K
Rx
B
VCC
VCC
DE
S1
S1
CRL
CDL
1K
VDC
500
A
Tx
REB
S2
B
S2
Fig. 3 Receiver Enable/Disable Timing Test Circuit
VOH
RO
Fig. 4 Transmitter Enable/Disable Timing Test Circuit
1.5V
1.5V
REB
3V
0V
Output
VOL
1.5V
1.5V
tRZL
tRLZ
VCC
RO
tRPHL
tRPLH
A
Input
B -1V
Fig. 9 Receiver Propagation Delays
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RO
VOL
VOH
0
1.5V
Output Normally Low
VOL+0.5V
Output Normally High
1.5V
tRZH
VOH-0.5V
tRHZ
Fig. 10 Receiver Enable and Disable Times
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Preliminary
CMOS IC
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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