S72VS256RE0

S72VS-R MCP
256 Mb (16M x 16 bit), 1.8V
Burst Mode Flash DDR DRAM on Split Bus
Features
■
Power supply voltage of 1.7V to 1.95V
■
■
Burst Speeds
❐ Flash = 83 MHz or 108 MHz
❐ DDR DRAM = 166 MHz
Packages
❐ 8.0  8.0 mm, 133-ball MCP
■
Operating Temperature
❐ Wireless, –25 °C to +85 °C
❐ Industrial, –40 °C to +85 °C
General Description
This document contains information on the S72VS-R MCP stacked products. Refer to the S29VS/XS-R datasheet
(002-00833) for full electrical specifications of the Flash memory component.
The S72VS Series is a product line of stacked products (MCPs), and consists of:
 S29VS family Address-Data Multiplexed Flash memory die
 DDR DRAM
The products covered by this document are listed in the below tables below.
Flash Density
DRAM Density (256 Mb)
256 Mb
S72VS256RE0
DDR Specification Reference
Density
Reference Name
Document Identification Number
256 Mb
256 Mb (16M x 16 bit) DDR DRAM
SDM256D166D1R/D3R
Cypress Semiconductor Corporation
Document Number: 002-00773 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 22, 2016
S72VS-R MCP
Electronic Serial Number
For applicable devices, the Factory Secured Silicon Area contains a random, 128-bit ESN, stored in the address range 000000h000007h.
Product Block Diagram
F -R S T#
RS T#
F -V P P
V PP
F -C E #
F -O E #
F -W E #
F -A V D #
CE#
A DQ 1 5 - A DQ 0
A ma x - A 1 6
O E#
W E#
A V D#
NOR
FLASH
V S -R
(A D M )
CL K
RDY
V CC
V CCQ
V SS
A D Q 15-A D Q 0
A m ax -A 16
F -C LK
F -R D Y
F -V C C
F -V C C Q
VSS
V SSQ
D -R A S #
D -C A S #
D -B A 0
D -B A 1
D -C K E
D -W E #
D -C E #
D -A m ax - D -A 0
D -V C C
D -V C C Q
RA S #
CK
CA S #
BA 0
BA 1
CK E
W E#
CS #
A ma x - A 0
V DD
V DDQ
CK #
DDR
DRAM
M EM ORY
L DQ S
UDQ S
L DM
UDM
DQ 1 5 - DQ 0
V SS
D -C LK
D -C LK #
D -LD Q S
D -U D Q S
D -LD Q M
D -U D Q M
D -D Q 15 - D -D Q 0
VSS
V SSQ
Notes
1. Amax indicates highest address bit for memory component:
a. Amax = A23 for VS256R.
b. Amax = A12 for 256 Mb DDR DRAM.
Document Number: 002-00773 Rev. *F
Page 2 of 9
S72VS-R MCP
Connection Diagrams
Figure 1. 133-ball Fine-Pitch Ball Grid Array MCP
1
2
3
DNU
DNU
VSS
DNU
VSS
4
5
6
7
8
9
10
11
12
13
14
Legend
VSS
DNU
DNU
Index Location
A
D-VCCQ D-DQ9 D-DQ8
VSS
D-VCC D-VCC D-DQ5 D-DQ3
B
D-DQ13 D-UDQS D-DQ10
VSS
D-VCCQ D-VCCQ D-LDQM D-DQ6 D-DQ4 D-DQ1 D-VCCQ
DNU
Do Not Use
C
D-VCC D-DQ15 D-DQ14 D-DQ12 D-DQ11 D-UDQM
VSS
D-VCC
VSS
D-DQ7 D-LDQS D-DQ2 D-DQ0
VSS
Not Connected
D
RFU
NC
NC
RFU
A22
A23
INDEX
F-OE#
ADQ8
D-VCC
A17
ADQ9
ADQ1
ADQ0
A19
A18
VSS
ADQ3
ADQ2
F-CE#
RFU
F-WE#
F-VCCQ ADQ11 ADQ10
F-VPP
F-VCC
F-CLK
ADQ13 ADQ12
A16
VSS
NC
VSS
VSS
ADQ5
A21
F-AVD#
NC
NC
ADQ7
ADQ6
A20
F-RST# D-CE#
DRAM Only
E
F
Code Flash Only
G
Reserved for Future Use
H
VSS
ADQ4
J
K
L
F-VCCQ ADQ15 ADQ14
M
NC
RFU
D-A3
D-A6
D-A9
D-CKE
VSS
D-WE#
D-A10
D-A1
RFU
RFU
F-RDY
VSS
DNU
VSS
D-VCC
D-A5
D-A8
D-CAS# D-CLK# D-BA1
D-A11
D-A2
D-A12
RFU
F-VCC
DNU
DNU
DNU
NC
D-A4
D-A7
D-RAS# D-CLK D-VCC
D-BA0
D-A0
D-VCC
VSS
DNU
DNU
N
P
MCP
Flash Amax
DDR DRAM Density
D-Amax
S72VS256RE0
A23
256 Mb
D-A12
Document Number: 002-00773 Rev. *F
Page 3 of 9
S72VS-R MCP
Input/Output Description
Table 1. Input/Output Description
Symbol
Description
Flash
RAM
Amax – A16
Flash Address inputs
X
ADQ15 – ADQ0
Flash multiplexed Address and Data
X
F-CE#
Flash Chip-enable input.
X
F-OE#
Flash Output Enable input. Asynchronous relative to CLK for Burst mode.
X
F-WE#
Flash Write Enable input
X
F-VCC
Flash device power supply (1.7 V to 1.95 V)
X
F-VCCQ
Flash Input/Output Buffer power supply
X







VSS
Ground
X
X
F-RDY
Flash ready output. Indicates the status of the Burst read. VOL = data
invalid. VOH = data valid.
X

F-CLK
Flash Clock. The first rising edge of CLK in conjunction with AVD# low
latches the address input and activates burst mode operation. After the
initial word is output, subsequent rising edges of CLK increment the
internal address counter. CLK should remain low during asynchronous
access.
X

F-AVD#
Flash Address Valid input. Indicates to device that the valid address is
present on the address inputs. VIL = for asynchronous mode, indicates
valid address; for burst mode, causes starting address to be latched on
rising edge of CLK. VIH= device ignores address inputs
X

F-RST#
Flash hardware reset input. VIL= device resets and returns to reading
array data
X

F-VPP
Flash accelerated input. At VHH, accelerates programming; automatically
places device in unlock bypass mode. At VIL, disables all program and
erase functions. Should be at VIH for all other conditions.
X

D-Amax – D-A0
DRAM Address inputs.















X
D-DQ15 – D-DQ0
DRAM Data input/output
D-CLK
DRAM System Clock
D-CE#
DRAM Chip Select
D-CKE
DRAM Clock Enable
D-BA1 – BA0
DRAM Bank Select
D-RAS#
DRAM Row Address Strobe
D-CAS#
DRAM Column Address Strobe
D-UDQM – D-LDQM
DRAM Data Input Mask
D-WE#
DRAM Write Enable input
D-VCCQ
DRAM Input/Output Buffer power supply
D-VCC
DRAM device power supply
D-UDQS
DRAM Upper Data Strobe, output with read data and input with write data
D-LDQS
DRAM Lower Data Strobe, output with read data and input with write data
D-CLK#
DDR Clock for negative edge of CLK
Document Number: 002-00773 Rev. *F
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Page 4 of 9
S72VS-R MCP
Table 1. Input/Output Description (Continued)
Symbol
Description
Flash
RAM
RFU
Reserved for Future Use. No device internal signal is currently connected
to the package connector but there is potential future use for the
connector for a signal. It is recommended to not use RFU connectors for
PCB routing channels so that the PCB may take advantage of future
enhanced features in compatible footprint devices.


NC
Not Connected. No device internal signal is connected to the package
connector nor is there any future plan to use the connector for a signal.
The connection may safely be used for routing space for a signal on a
Printed Circuit Board (PCB).


DNU
Do Not Use. A device internal signal may be connected to the package
connector. The connection may be used by Spansion for test or other
purposes and is not intended for connection to any host system signal.
Any DNU signal related function will be inactive when the signal is at VIL.
The signal has an internal pull-down resistor and may be left
unconnected in the host system or may be tied to VSS. Do not use these
connections for PCB signal routing channels. Do not connect any host
system signal to these connections.


Document Number: 002-00773 Rev. *F
Page 5 of 9
S72VS-R MCP
Ordering Information
The order number (Valid Combination) is formed by the following:
S72VS
256
R
E0
AH
B
HE
3
PACKING TYPE
0 = Tray
3 = 13-inch Tape and Reel
MODEL NUMBER
See Valid Combinations table
PACKAGE MODIFIER
B = 133-ball, 8 x 8 mm, FBGA MCP
PACKAGE AND MATERIAL TYPE
AH = Thin profile Fine-pitch BGA Pb-free Low-Halogen MCP (0.5 mm pitch)
DDR DRAM AND DATA FLASH DENSITY
E0 = 256 Mb DDR, No Data Flash
PROCESS TECHNOLOGY
R = 65 nm, MirrorBit Technology
CODE FLASH DENSITY
256 = 256 Mb
PRODUCT FAMILY
S72VS Multi-Chip Product (MCP)
1.8V Address-Data Multiplexed, SRW, Burst Mode Flash and DDR DRAM on
Split Bus
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm
availability of specific valid combinations and to check on newly released combinations.
Base OPN
S72VS256RE0
Package
AHB
Model
Number
Packing
Type
Flash
Boot
H1
Top
J1
Bottom
HH
0, 3
[2]
JH
Top
Bottom
Temp
Range
Wireless
Industrial
Electronic
Serial
Number
Flash
Density
DDR
DRAM
Density
Flash
Speed
(MHz)
DRAM
Speed
(MHz)
Yes
No
Yes
DRAM
Specification
SDM256D166D
1R
256 Mb
Yes
256 Mb
108
166
SDM256D166D
3R
Package
8.0 x 8.0 mm
133-ball MCP
(RSC133)
Note
2. Packing Type 0 is standard. Specify other options as required.
3. BGA package marking omits leading “S” and packing type designator from ordering part number.
Document Number: 002-00773 Rev. *F
Page 6 of 9
S72VS-R MCP
Physical Dimensions
Figure 2. RSC133—133-ball Fine-Pitch Ball Grid Array (FBGA) 8.0 x 8.0 mm
Document Number: 002-00773 Rev. *F
Page 7 of 9
S72VS-R MCP
Revision History
Document History Page
Document Title: S72VS-R MCP, 256 Mb (16M x 16 bit), 1.8V Burst Mode Flash DDR DRAM on Split Bus
Document Number: 002-00773
Revision
**
*A
*B
*C
ECN




Orig. of
Change




Submission
Date
Description of Change
07/21/2010
Initial release
08/24/2010
Global: Added information for OPN S72VS256RE0AHBH1
12/10/2010
Global: Updated 256 Mb DRAM specification reference
03/18/2011
Global: Added OPN S72VS256RE0AHBJ1
*D


10/05/2011
*E


Ordering Information: Replaced Product Selector Guide section
Valid Combinations:
Made a separate section
Added OPNs: S72VS256RE0AHBHH/JH
04/17/2012
Ordering Information: Added ESN support for S72VS256RE0AHBH1
*F
5185100
TOCU
03/22/2016
Updated to Cypress template.
Removed any occurrence of 128 Mb and 8M in the document.
Document Number: 002-00773 Rev. *F
Page 8 of 9
S72VS-R MCP
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Document Number: 002-00773 Rev. *F
Revised March 22, 2016
Page 9 of 9