SiC789, SiC789A www.vishay.com Vishay Siliconix 60 A VRPower® Integrated Power Stage DESCRIPTION FEATURES The SiC789 and SiC789A are integrated power stage solutions optimized for synchronous buck applications to offer high current, high efficiency, and high power density performance. Packaged in Vishay’s proprietary 6 mm x 6 mm MLP package, SiC789 and SiC789A enable voltage regulator designs to deliver up to 60 A continuous current per phase. • Thermally enhanced PowerPAK® MLP66-40L package • Vishay’s Gen IV MOSFET technology and a low-side MOSFET with integrated Schottky diode • Delivers up to 60 A continuous current • 95 % peak efficiency • High frequency operation up to 1.5 MHz • Power MOSFETs optimized for 12 V input stage • 3.3 V (SiC789A) / 5 V (SiC789) PWM logic with tri-state and hold-off • SMOD# logic for light load efficiency improvement The internal power MOSFETs utilize Vishay’s state-of-the-art Gen IV TrenchFET technology that delivers industry benchmark performance to significantly reduce switching and conduction losses. The SiC789 and SiC789A incorporate an advanced MOSFET gate driver IC that features high current driving capability, adaptive dead-time control, an integrated bootstrap Schottky diode, a thermal warning (THWn) that alerts the system of excessive junction temperature, and skip mode (SMOD#) to improve light load efficiency. The drivers are also compatible with a wide range of PWM controllers and supports tri-state PWM, 3.3 V (SiC789A) / 5 V (SiC789) PWM logic. • Low PWM propagation delay (< 20 ns) • Thermal monitor flag • Faster enable / disable • Under voltage lockout for VCIN • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 APPLICATIONS • Multi-phase VRDs for CPU, GPU, and memory TYPICAL APPLICATION DIAGRAM 5V VIN V IN GH VDRV BOOT PHASE VCIN SMOD# PWM controller DSBL# PWM VSWH VOUT Gate driver THWn PGND GL C GND Fig. 1 - SiC789 and SiC789A Typical Application Diagram S14-2287-Rev. B, 08-Dec-14 Document Number: 62972 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC789, SiC789A www.vishay.com Vishay Siliconix 39 DSBL# 40 PWM 38 THWn 37 CGND 35 VSWH 36 GL 33 VSWH 34 VSWH 31 VSWH 32 VSWH 31 VSWH 32 VSWH 33 VSWH 34 VSWH 35 VSWH 36 GL 38 THWn 37 CGND 39 DSBL# 40 PWM PINOUT CONFIGURATION 30 VSWH VSWH 30 29 VSWH VSWH 29 28 PGND PGND 28 27 PGND PGND 27 26 PGND PGND 26 25 PGND PGND 25 24 PGND PGND 24 23 PGND PGND 23 VIN 9 22 PGND PGND 22 9 VIN VIN 10 21 PGND PGND 21 10 VIN 7 PHASE 42 VIN Top view 8 VIN VIN 11 PGND 20 PGND 19 PGND 18 PGND 17 PGND 16 VSWH 15 VIN 14 VIN 13 VIN 11 VIN 12 42 VIN VIN 8 6 GH VIN 12 PHASE 7 5 CGND 43 VSWH VIN 13 GH 6 VIN 14 43 VSWH PGND 16 CGND 5 3 VDRV 4 BOOT VSWH 15 BOOT 4 PGND 17 VDRV 3 2 VCIN 41 CGND PGND 18 41 CGND 1 SMOD# PGND 19 VCIN 2 PGND 20 SMOD# 1 Bottom view Fig. 2 - SiC789 and SiC789A Pin Configuration PIN DESCRIPTION PIN NUMBER NAME 1 SMOD# Low-side gate turn-off logic. Active low FUNCTION 2 VCIN Supply voltage for internal logic circuitry 3 VDRV Supply voltage for internal gate driver 4 BOOT High-side driver bootstrap voltage 5, 37, 41 CGND Analog ground for the driver IC 6 GH 7 PHASE High-side gate signal Return path of high-side gate driver 8 to 14, 42 VIN 15, 29 to 35, 43 VSWH Switch node of the power stage 16 to 28 PGND Power ground 36 GL 38 THWn 39 DSBL# 40 PWM Power stage input voltage. Drain of high-side MOSFET Low-side gate signal Thermal warning open drain output Disable pin. Active low PWM control input ORDERING INFORMATION PART NUMBER SiC789ACD-T1-GE3 SiC789CD-T1-GE3 SiC789ADB and SiC789DB S14-2287-Rev. B, 08-Dec-14 PACKAGE PowerPAK® MLP66-40L MARKING CODE OPTION SiC789A 3.3 V PWM optimized SiC789 5 V PWM optimized Reference board Document Number: 62972 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC789, SiC789A www.vishay.com Vishay Siliconix ABSOLUTE MAXIMUM RATINGS ELECTRICAL PARAMETER CONDITIONS LIMIT VIN -0.3 to +25 Control Logic Supply Voltage VCIN -0.3 to +7 Drive Supply Voltage VDRV -0.3 to +7 Input Voltage Switch Node (DC voltage) Switch Node (AC BOOT Voltage (DC voltage) BOOT Voltage (AC voltage) -0.3 to +25 VSWH voltage) (1) -8 to +30 BOOT to PHASE (DC voltage) 38 -0.3 to +7 VBOOT- PHASE BOOT to PHASE (AC voltage) (3) -0.3 to +8 All Logic Inputs and Outputs (PWM, DSBL#, and THWn) -0.3 to VCIN + 0.3 fS = 300 kHz, VIN = 12 V, VOUT = 1.8 V 60 fS = 1 MHz, VIN = 12 V, VOUT = 1.8 V 50 TJ 150 Ambient Temperature TA -40 to +125 Storage Temperature Tstg -65 to +150 Human body model, JESD22-A114 5000 Charged device model, JESD22-C101 1000 Output Current, IOUT(AV) (4) Max. Operating Junction Temperature Electrostatic Discharge Protection V 32 VBOOT (2) UNIT A °C V Note (1) The specification values indicated “AC” is V SWH to PGND, -8 V (< 20 ns, 10 μJ), min. and 30 V (< 50 ns), max. (2) The specification value indicates “AC voltage” is V BOOT to PGND, 36 V (< 50 ns) max. (3) The specification value indicates “AC voltage” is V BOOT to VPHASE, 8 V (< 20 ns) max. (4) Output current rated with testing evaluation board at T = 25 °C with natural convection cooling. The rating is limited by the peak evaluation A board temperature, TJ = 150 °C, and varies depending on the operating conditions and PCB layout. This rating may be changed with different application settings. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING RANGE ELECTRICAL PARAMETER Input Voltage (VIN) MINIMUM TYPICAL MAXIMUM 4.5 - 18 Drive Supply Voltage (VDRV) 4.5 5 5.5 Control Logic Supply Voltage (VCIN) 4.5 5 5.5 BOOT to PHASE (VBOOT-PHASE, DC voltage) 4 4.5 5.5 Thermal Resistance from Junction to PAD - 1 - Thermal Resistance from Junction to Case - 2.5 - S14-2287-Rev. B, 08-Dec-14 UNIT V °C/W Document Number: 62972 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC789, SiC789A www.vishay.com Vishay Siliconix ELECTRICAL SPECIFICATIONS (DSBL# = SMOD# = 5 V, VIN = 12 V, VDRV and VCIN = 5 V, TA = 25 °C) PARAMETER SYMBOL TEST CONDITION VDSBL# = 0 V, no switching, VPWM = FLOAT IVCIN VDSBL# = 5 V, no switching, VPWM = FLOAT LIMITS MIN. TYP. MAX. - 85 - - 290 - VDSBL# = 5 V, fS = 300 kHz, D = 0.1 - 295 - fS = 300 kHz, D = 0.1 - 16 25 fS = 1 MHz, D = 0.1 - 50 - VDSBL# = 0 V, no switching - 35 - VDSBL# = 5 V, no switching - 60 - UNIT POWER SUPPLY Control Logic Supply Current Drive Supply Current IVDRV μA mA μA BOOTSTRAP SUPPLY Bootstrap Diode Forward Voltage VF IF = 2 mA 0.4 V PWM CONTROL INPUT (SiC789) Rising Threshold VTH_PWM_R 3.4 3.7 4.0 Falling Threshold VTH_PWM_F 0.72 0.9 1.1 Tri-state Voltage VTRI - 2.3 - VPWM = FLOAT Tri-state Rising Threshold VTRI_TH_R 0.9 1.15 1.38 Tri-state Falling Threshold VTRI_TH_F 3.1 3.35 3.6 Tri-state Rising Threshold Hysteresis VHYS_TRI_R - 225 - Tri-state Falling Threshold Hysteresis VHYS_TRI_F - 325 - VPWM = 5 V - - 350 VPWM = 0 V - - -350 PWM Input Current V mV IPWM μA PWM CONTROL INPUT (SiC789A) Rising Threshold VTH_PWM_R 2.2 2.45 2.7 Falling Threshold VTH_PWM_F 0.72 0.9 1.1 Tri-state Voltage VTRI - 1.8 - Tri-state Rising Threshold VTRI_TH_R 0.9 1.15 1.38 Tri-state Falling Threshold VTRI_TH_F 1.95 2.2 2.45 Tri-state Rising Threshold Hysteresis VHYS_TRI_R - 225 - Tri-state Falling Threshold Hysteresis VHYS_TRI_F - 275 - PWM Input Current VPWM = FLOAT V mV VPWM = 3.3 V - - 225 VPWM = 0 V - - -225 tPD_TRI_R - 30 - IPWM μA TIMING SPECIFICATIONS Tri-State to GH/GL Rising Propagation Delay tTSHO - 130 - GH - Turn Off Propagation Delay Tri-state Hold-Off Time tPD_OFF_GH - 18 - GH - Turn On Propagation Delay (Dead time rising) tPD_ON_GH - 10 - GL - Turn Off Propagation Delay tPD_OFF_GL - 12 - GL - Turn On Propagation Delay (Dead time falling) tPD_ON_GL - 10 - No load, see fig. 4 DSBL# Low to GH/GL Falling Propagation Delay tPD_DSBL#_F Fig. 5 - 15 - DSBL# High to GH/GL Rising Propagation Delay tPD_DSBL#_R Fig. 5 - 20 - PWM Minimum On-Time tPWM_ON_MIN 30 - - S14-2287-Rev. B, 08-Dec-14 ns Document Number: 62972 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC789, SiC789A www.vishay.com Vishay Siliconix ELECTRICAL SPECIFICATIONS (DSBL# = SMOD# = 5 V, VIN = 12 V, VDRV and VCIN = 5 V, TA = 25 °C) PARAMETER SYMBOL TEST CONDITION VIH_DSBL# VIL_DSBL# LIMITS MIN. TYP. MAX. Input logic high 2 - - Input logic low - - 0.8 VIH_SMOD# Input logic high 2 - - VIL_SMOD# Input logic low - - 0.8 VCIN rising, on threshold - 3.7 4.1 VCIN falling, off threshold 2.7 3.1 - UNIT DSBL# SMOD# INPUT DSBL# Logic Input Voltage SMOD# Logic Input Voltage V PROTECTION Under Voltage Lockout VUVLO Under Voltage Lockout Hysteresis VUVLO_HYST - 575 - THWn Flag Set (2) TTHWn_SET - 160 - THWn Flag Clear (2) TTHWn_CLEAR - 135 - THWn Flag Hysteresis (2) TTHWn_HYST - 25 - - 0.02 - THWn Output Low VOL_THWn ITHWn = 2 mA V mV °C V Notes (1) Typical limits are established by characterization and are not production tested. (2) Guaranteed by design. DETAILED OPERATIONAL DESCRIPTION PWM Input with Tri-state Function Pre-Charger Function The PWM input receives the PWM control signal from the VR controller IC. The PWM input is designed to be compatible with standard controllers using two state logic (H and L) and advanced controllers that incorporate tri-state logic (H, L and tri-state) on the PWM output. For two state logic, the PWM input operates as follows. When PWM is driven above VPWM_TH_R the low-side is turned OFF and the high-side is turned ON. When PWM input is driven below VPWM_TH_F the high-side is turned OFF and the low-side is turned ON. For tri-state logic, the PWM input operates as previously stated for driving the MOSFETs when PWM is logic high and logic low. However, there is a third state that is entered as the PWM output of tri-state compatible controller enters its high impedance state during shut-down. The high impedance state of the controller’s PWM output allows the SiC789 and SiC789A to pull the PWM input into the tri-state region (see definition of PWM logic and Tri-State, fig. 4). If the PWM input stays in this region for the Tri-state Hold-Off Period, tTSHO, both high-side and low-side MOSFETs are turned OFF. The function allows the VR phase to be disabled without negative output voltage swing caused by inductor ringing and saves a Schottky diode clamp. The PWM and tri-state regions are separated by hysteresis to prevent false triggering. The SiC789A incorporates PWM voltage thresholds that are compatible with 3.3 V logic and the SiC789 thresholds are compatible with 5 V logic. When DSBL# is driven from below VIL_DSBL# to above VIH_DSBL# the low-side is turned ON for a short duration (60 ns typical) to refresh the BOOT capacitor in case it has been discharged due to the driver being in standby for a long period of time. Disable (DSBL#) In the low state, the DSBL# pin shuts down the driver IC and disables both high-side and low-side MOSFETs. In this state, standby current is minimized. If DSBL# is left unconnected, an internal pull-down resistor will pull the pin to CGND and shut down the IC. S14-2287-Rev. B, 08-Dec-14 Diode Emulation Mode (SMOD#) When SMOD# is logic low diode emulation mode is enabled and the low-side is turned OFF. This is a non-synchronous conversion mode that improves light load efficiency by reducing switching losses. Conducted losses that occur in synchronous buck regulators when inductor current is negative can also be reduced. Circuitry in the external controller IC detects when inductor current crosses zero and drives SMOD# below VIL_SMOD# turning the low-side MOSFET OFF. The function can be also be used for a pre-biased output voltage. If SMOD# is left unconnected, an internal pull up resistor will pull the pin to VCIN (logic high) to disable the SMOD# function. Thermal Shutdown Warning (THWn) The THWn pin is an open drain signal that flags the presence of excessive junction temperature. Connect, with a maximum of 20 kΩ, to VCIN. An internal temperature sensor detects the junction temperature. The temperature threshold is 160 °C. When this junction temperature is exceeded the THWn flag is set. When the junction temperature drops below 135 °C the device will clear the THWn signal. The SiC789 and SiC789A do not stop operation when the flag is set. The decision to shutdown must be made by an external thermal control function. Document Number: 62972 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC789, SiC789A www.vishay.com Vishay Siliconix Voltage Input (VIN) Bootstrap Circuit (BOOT) This is the power input to the drain of the high-side power MOSFET. This pin is connected to the high power intermediate BUS rail. The internal bootstrap diode and an external bootstrap capacitor form a charge pump that supplies voltage to the BOOT pin. An integrated bootstrap diode is incorporated so that only an external capacitor is necessary to complete the bootstrap circuit. Connect a boot strap capacitor with one leg tied to BOOT pin and the other tied to PHASE pin. Switch Node (VSWH and PHASE) The switch node, VSWH, is the circuit power stage output. This is the output applied to the power inductor and output filter to deliver the output for the buck converter. The PHASE pin is internally connected to the switch node, VSWH. This pin is to be used exclusively as the return pin for the BOOT capacitor. A 20 kΩ resistor is connected between GH and PHASE to provide a discharge path for the HS MOSFET in the event that VCIN goes to zero while VIN is still applied. Shoot-Through Protection and Adaptive Dead Time The SiC789 and SiC789A have an internal adaptive logic to avoid shoot through and optimize dead time. The shoot through protection ensures that both high-side and low-side MOSFETs are not turned ON at the same time. The adaptive dead time control operates as follows. The high-side and low-side gate voltages are monitored to prevent the MOSFET turning ON from tuning ON until the other MOSFET's gate voltage is sufficiently low (< 1 V). Built in delays also ensure that one power MOSFET is completely OFF, before the other can be turned ON. This feature helps to adjust dead time as gate transitions change with respect to output current and temperature. Ground Connections (CGND and PGND) PGND (power ground) should be externally connected to CGND (control signal ground). The layout of the printed circuit board should be such that the inductance separating CGND and PGND is minimized. Transient differences due to inductance effects between these two pins should not exceed 0.5 V Under Voltage Lockout (UVLO) Control and Drive Supply Voltage Input (VDRV, VCIN) During the start up cycle, the UVLO disables the gate drive, holding high-side and low-side MOSFET gates low, until the supply voltage rail has reached a point at which the logic circuitry can be safely activated. The SiC789 and SiC789A also incorporate logic to clamp the gate drive signals to zero when the UVLO falling edge triggers the shutdown of the device. As an added precaution, a 20 kΩ resistor is connected between GH and PHASE to provide a discharge path for the HS MOSFET. VCIN is the bias supply for the gate drive control IC. VDRV is the bias supply for the gate drivers. It is recommended to separate these pins through a resistor. This creates a low pass filtering effect to avoid coupling of high frequency gate drive noise into the IC. FUNCTIONAL BLOCK DIAGRAM THWn BOOT GH V IN VDRV Thermal monitor & warning V CIN UVLO DSBL# VCIN PWM PWM logic control & state machine Anti-cross conduction control logic + GL 20K PHASE Vref = 1 V VSWH + Vref = 1 V VDRV C GND SMOD# GL PGND Fig. 3 - SiC789 and SiC789A Functional Block Diagram S14-2287-Rev. B, 08-Dec-14 Document Number: 62972 6 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC789, SiC789A www.vishay.com Vishay Siliconix DEVICE TRUTH TABLE DSBL# SMOD# PWM GH GL Open X X L L L X X L L H L L L L H L H H L H L Tri-state L L H H L L H H H H H L H H Tri-state L L PWM TIMING DIAGRAM VTH_PWM_R VTH_TRI_F VTH_TRI_R VTH_PWM_F PWM t PD_OFF_GL t TSHO GL t PD_ON_GL t PD_TRI_R t TSHO t PD_ON_GH t PD_OFF_GH t PD_TRI_R GH Fig. 4 - Definition of PWM Logic and Tri-State S14-2287-Rev. B, 08-Dec-14 Document Number: 62972 7 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC789, SiC789A www.vishay.com Vishay Siliconix OPERATION TIMING DIAGRAM: DSBL# PWM PWM Enable DSBL # DSBL # GH GH GL GL t t DSBL# High to GH Rising Propagation Delay DSBL# High to GL Rising Propagation Delay PWM PWM Disable DSBL # DSBL # GH GH GL GL t t DSBL# Low to GH Falling Propagation Delay DSBL# Low to GL Falling Propagation Delay Fig. 5 - DSBL# Propagation Delay S14-2287-Rev. B, 08-Dec-14 Document Number: 62972 8 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC789, SiC789A www.vishay.com Vishay Siliconix ELECTRICAL CHARACTERISTICS Test condition: VIN = 12 V, VDRV = VCIN = 5 V, DSBL# = SMOD# = 5 V, VOUT = 1 V, LOUT = 270 nH (DCR = 0.32 mΩ), TA = 25 °C (All power loss and normalized power loss curves show SiC789 and SiC789A losses only unless otherwise stated) 12.0 94 300 kHz 90 10.5 500 kHz 9.0 86 Power Loss, PL (W) Efficiency (%) 1 MHz 82 800 kHz 78 74 66 7.5 6.0 800 kHz 4.5 300 kHz Complete converter efficiency PIN = [(VIN x IIN) + 5 V x (IVDRV + IVCIN)] POUT = VOUT x IOUT, measured at output capacitor 70 1 MHz 3.0 1.5 500 kHz 0.0 62 0 5 10 15 20 25 30 35 40 45 50 0 55 5 10 15 Output Current, IOUT (A) 25 30 35 40 45 50 55 Fig. 9 - Power Loss vs. Output Current Fig. 6 - Efficiency vs. Output Current 12.0 94 VOUT = 1.0V 90 10.5 VOUT = 0.9V 86 fS = 500 kHz 9.0 VOUT = 0.7V Power Loss, PL (W) Efficiency (%) 20 Output Current, IOUT (A) 82 VOUT = 0.8V 78 74 VOUT = 0.7 V VOUT = 0.8 V VOUT = 0.9 V VOUT = 1.0 V 7.5 6.0 4.5 3.0 70 fS = 500kHz 1.5 66 0.0 62 0 5 10 15 20 25 30 35 40 Output Current, IOUT (A) 45 50 0 55 10 15 20 25 30 35 40 45 50 55 Output Current, IOUT (A) Fig. 7 - Efficiency vs. Output Current Fig. 10 - Power Loss vs. Output Current 8.0 64 7.0 56 fS = 300 kHz 300 kHz Output Current, IOUT (A) 6.0 Power Loss, PL (W) 5 5.0 VOUT = 0.7 V VOUT = 0.8 V VOUT = 0.9 V VOUT = 1.0 V 4.0 3.0 2.0 1.0 48 1 MHz 40 32 24 16 8 0.0 0 0 5 10 15 20 25 30 35 40 45 50 Output Current, IOUT (A) Fig. 8 - Power Loss vs. Output Current S14-2287-Rev. B, 08-Dec-14 55 0 15 30 45 60 75 90 105 120 135 150 PCB Temperature, TPCB (°C) Fig. 11 - Safe Operating Area Document Number: 62972 9 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC789, SiC789A Vishay Siliconix 1.80 1.20 1.65 1.16 Normalized Driver Supply Current Normalized Power Loss www.vishay.com 1.50 1.35 1.20 1.05 0.90 0.75 1.04 1.00 0 4.0 0.35 BOOT Diode Forward Voltage, VF (V) 0.40 VUVLO_RISING 3.8 3.6 3.4 3.2 3.0 VUVLO_FALLING 2.8 10 15 20 25 30 35 40 Output Current, IOUT (A) 45 50 55 IF = 2 mA 0.30 0.25 0.20 0.15 0.10 0.05 0.00 2.6 -60 -40 -20 0 20 40 60 80 Temperature (°C) -60 -40 -20 100 120 140 0 20 40 60 80 100 120 140 Temperature (°C) Fig. 13 - UVLO Threshold vs. Temperature Fig. 16 - BOOT Diode Forward Voltage vs. Temperature 3.2 3.4 PWM Threshold Voltage, VPWM (V) 3.0 2.2 5 Fig. 15 - Driver Supply Current vs. Output Current 4.2 2.6 1 MHz 0.96 0.88 Fig. 12 - Power Loss vs. Switching Frequency Control Logic Supply Voltage, VCIN (V) 300 kHz 1.08 0.92 0.60 200 300 400 500 600 700 800 900 1000 1100 1200 Switching Frequency, fS (kHz) PWM Threshold Voltage, VPWM (V) 1.12 VTH_PWM_R VTRI_TH_F 1.8 VTRI 1.4 VTRI_TH_R 1.0 VTH_PWM_F 0.6 2.8 VTH_PWM_R 2.4 VTRI_TH_F 2.0 VTRI 1.6 VTRI_TH_R 1.2 0.8 VTH_PWM_F 0.4 0.0 0.2 -60 -40 -20 0 20 40 60 80 Temperature (°C) 100 120 140 Fig. 14 - PWM Threshold vs. Temperature (SiC789A) S14-2287-Rev. B, 08-Dec-14 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 Driver Supply Voltage, VCIN (V) 5.4 5.5 Fig. 17 - PWM Threshold vs. Driver Supply Voltage (SiC789A) Document Number: 62972 10 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC789, SiC789A www.vishay.com Vishay Siliconix 4.8 PWM Threshold Voltage, VPWM (V) 4.2 VTH_PWM_R 3.6 VTRI_TH_F 3.0 2.4 VTRI 1.8 VTRI_TH_R 1.2 0.6 PWM Threshold Voltage, VPWM (V) 4.8 VTRI_TH_F 3.0 2.4 VTRI 1.8 VTRI_TH_R 1.2 VTH_PWM_F 0.0 -60 -40 -20 0 20 40 60 80 4.5 100 120 140 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 Temperature (°C) Driver Supply Voltage, VCIN (V) Fig. 18 - PWM Threshold vs. Temperature (SiC789) Fig. 21 - PWM Threshold vs. Driver Supply Voltage (SiC789) 2.2 2.2 2.0 2.0 DSBL# Threshold Voltage, VDSBL# (V) DSBL# Threshold Voltage, VDSBL# (V) 3.6 0.6 VTH_PWM_F 0.0 1.8 VIH_DSBL# 1.6 1.4 1.2 1.0 VIL_DSBL# 0.8 0.6 1.8 VIH_DSBL# 1.6 1.4 VIL_DSBL# 1.2 1.0 0.8 0.6 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) 4.5 4.7 4.8 4.9 5.0 5.1 5.2 5.3 Driver Supply Voltage, VCIN (V) Fig. 19 - DSBL# Threshold vs. Temperature Fig. 22 - DSBL# Threshold vs. Driver Supply Voltage 2.2 2.2 2.0 2.0 SMOD# Threshold Voltage, VSMOD# (V) SMOD# Threshold Voltage, VSMOD# (V) VTH_PWM_R 4.2 1.8 VIH_SMOD# 1.6 1.4 1.2 1.0 VIL_SMOD# 0.8 4.6 5.4 5.5 1.8 VIH_SMOD# 1.6 1.4 VIL_SMOD# 1.2 1.0 0.8 0.6 0.6 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) Fig. 20 - SMOD# Threshold vs. Temperature S14-2287-Rev. B, 08-Dec-14 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 Driver Supply Voltage, VCIN (V) Fig. 23 - SMOD# Threshold vs. Driver Supply Voltage Document Number: 62972 11 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC789, SiC789A Vishay Siliconix 12.0 -8.0 11.5 -8.5 SMOD# Pull-Up Current, ISMOD# (uA) DSBL# Pull-Down Current, IDSBL# (uA) www.vishay.com 11.0 10.5 10.0 9.5 9.0 8.5 VSMOD# = 0 V -9.0 -9.5 -10.0 -10.5 -11.0 -11.5 -12.0 8.0 -60 -40 -20 0 20 40 60 80 Temperature (°C) -60 -40 -20 100 120 140 Fig. 24 - DSBL# Pull-down Current vs. Temperature 20 40 60 80 Temperature (°C) 100 120 140 Fig. 26 - SMOD# Pull-up Current vs. Temperature 200 430 180 410 VDSBL# = 0 V 160 140 120 100 80 60 40 Driver Supply Current, IVDVR & IVCIN (V) Driver Supply Current, IVDVR & IVCIN (V) 0 VPWM = FLOAT 390 370 350 330 310 290 270 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) Fig. 25 - Driver Shutdown Current vs. Temperature S14-2287-Rev. B, 08-Dec-14 -60 -40 -20 0 20 40 60 80 Temperature (°C) 100 120 140 Fig. 27 - Driver Quiescent Current vs. Temperature Document Number: 62972 12 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC789, SiC789A www.vishay.com Vishay Siliconix PCB LAYOUT RECOMMENDATIONS Step 1: VIN / PGND Planes and Decoupling Step 3: VCIN / VDRV Input Filter V IN Plane Vias for ground connection PGND V IN CGND Cvdrv CGND Cvcin V SWH PGND Plane 1. Layout VIN and PGND planes as shown above 2. Ceramic capacitors should be placed directly between VIN and PGND, and as close as possible to IC for best decoupling effect 3. Different ceramic capacitor values and packages should be used to cover entire decoupling spectrum, e.g. 1210, 0805, 0603, and 0402 4. Smaller capacitance values, placed closer to the IC’s VIN pin(s), result in better high frequency noise absorbing 1. VCIN / VDRV input filter ceramic capacitors should be placed as close as possible to IC. It is recommended to connect two capacitors separately 2. VCIN capacitor should be placed between pin 2 and pin 37 (CGND of driver IC) to achieve best noise filtering 3. VDRV capacitor should be placed between pin 3 and PGND to provide maximum instantaneous driver current for low-side MOSFET during switching cycle. PGND can be connected to inner ground plane through vias, as shown above 4. Pin 5 and pin 37 should be connected with CGND pad, as shown above Step 2: VSWH Plane 5. For connecting VCIN to CGND, it is recommended to use a large plane to reduce parasitic inductance Step 4: BOOT Resistor and Capacitor Placement CGND Snubber V SWH PGND Plane 1. Connect output inductor to IC with large plane to lower resistance 2. VSWH plane also serves as a heat-sink for low-side MOSFET. Please make the plane wide and short to achieve best thermal path 3. If a snubber network is required, place components as shown above 1. The components need to be placed as close as possible to IC, directly between PHASE (pin 7) and BOOT (pin 4) 2. To reduce parasitic inductance, 0402 package size can be used S14-2287-Rev. B, 08-Dec-14 Document Number: 62972 13 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC789, SiC789A www.vishay.com Vishay Siliconix Step 5: Signal Routing Step 7: Ground Connection CGND CGND CGND GND Plane PGND 1. Route the PWM, SMOD#, DSBL#, and THWn signal traces out of the top right corner, next to pin 1 1. It is recommended to make the entire first inner layer (below top layer) the ground plane 2. The PWM signal is a very important signal, both signal and return traces should not cross any power nodes on any layer 2. The ground plane provides analog ground and power ground connections 3. It is best to “shield” these traces from power switching nodes, e.g. VSWH, with a GND island to improve signal integrity 3. The ground plane provides shielding between noise source on top layer and signal traces on bottom layer Step 6: Adding Thermal Relief Vias V IN Plane V IN CGND V SWH PGND Plane 1. Thermal relief vias can be added to the VIN and CGND pads to utilize inner layers for high-current and thermal dissipation 2. To achieve better thermal performance, additional vias can be added to VIN and PGND planes 3. The VSWH pad is a noise source and it is not recommended to place vias on this pad 4. 8 mil drill for pads and 10 mils drill for planes are the optional via sizes. Vias on pad may drain solder during assembly and cause assembly issues. Please consult with the assembly house for guidelines S14-2287-Rev. B, 08-Dec-14 Document Number: 62972 14 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC789, SiC789A www.vishay.com Vishay Siliconix RECOMMENDED LAND PATTERN PowerPAK® MLP66-40L in millimeters 2.200 2.200 0.100 0.100 0.200 0.276 0.100 1 0.025 1 40 40 0.100 0.100 0.310 0.320 0.100 1.700 2.600 0.100 0.100 0.025 0.600 0.276 4.600 S14-2287-Rev. B, 08-Dec-14 0.100 0.100 Document Number: 62972 15 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC789, SiC789A www.vishay.com Vishay Siliconix PACKAGE OUTLINE DRAWING MLP66-40L 2x 5 6 Pin 1 dot by marking 0.10 C A D A A 0.08 C K1 A1 K2 0.41 A2 Pin #1 dent D2-1 31 40 2x 30 1 21 10 E2-3 E2-1 4 E 0.10 M C A B MLP66-40L (6 mm x 6 mm) (Nd-1)X e ref. E2-2 e 0.10 C B B 20 D2-2 D2-3 11 C Top view (Nd-1)X e ref. Side view Bottom view DIM. MILLIMETERS INCHES MIN. NOM. MAX. MIN. NOM. A 0.70 0.75 0.80 0.027 0.029 0.031 A1 0.00 - 0.05 0.000 - 0.002 A2 b 0.20 ref. 0.20 0.25 0.008 ref. 0.30 0.078 0.098 D 6.00 BSC 0.236 BSC e 0.50 BSC 0.019 BSC E 6.00 BSC 0.236 BSC L 0.35 0.40 MAX. 0.45 0.013 0.015 N 40 40 Nd 10 10 Ne 10 10 0.011 0.017 D2-1 1.45 1.50 1.55 0.057 0.059 0.061 D2-2 1.45 1.50 1.55 0.057 0.059 0.061 D2-3 2.35 2.40 2.45 0.095 0.094 0.096 E2-1 4.35 4.40 4.45 0.171 0.173 0.175 E2-2 1.95 2.00 2.05 0.076 0.078 0.080 E2-3 1.95 2.00 2.05 0.076 0.078 0.080 K1 0.73 BSC 0.028 BSC K2 0.21 BSC 0.008 BSC Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?62972. S14-2287-Rev. B, 08-Dec-14 Document Number: 62972 16 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix PowerPAK® MLP66-40 Case Outline 2x 5 6 Pin 1 dot by marking K1 0.08 C A 0.10 C A D A K2 A1 D2-1 0.41 A2 31 40 2x 30 1 21 10 E2-3 E2-1 4 E 0.10 M C A B MLP66-40 (6 mm x 6 mm) (Nd-1)X e ref. E2-2 e 0.10 C B B 20 D2-2 D2-3 11 C (Nd-1)X e ref. Top View DIM. Bottom View Side View MILLIMETERS INCHES MIN. NOM. MAX. MIN. NOM. A (8) 0.70 0.75 0.80 0.027 0.029 0.031 A1 0.00 - 0.05 0.000 - 0.002 0.30 0.078 A2 b (4) 0.20 ref. 0.20 0.25 0.008 ref. 0.098 D 6.00 BSC 0.236 BSC e 0.50 BSC 0.019 BSC E 6.00 BSC 0.236 BSC L 0.35 0.40 MAX. 0.45 0.013 0.015 N (3) 40 40 Nd (3) 10 10 Ne (3) 10 0.011 0.017 10 D2-1 1.45 1.50 1.55 0.057 0.059 0.061 D2-2 1.45 1.50 1.55 0.057 0.059 0.061 D2-3 2.35 2.40 2.45 0.095 0.094 0.096 E2-1 4.35 4.40 4.45 0.171 0.173 0.175 E2-2 1.95 2.00 2.05 0.076 0.078 0.080 E2-3 1.95 2.00 2.05 0.076 0.078 0.080 K1 0.73 BSC 0.028 BSC K2 0.21 BSC 0.008 BSC ECN: T14-0826-Rev. B, 12-Jan-15 DWG: 5986 Notes 1. Use millimeters as the primary measurement 2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994 3. N is the number of terminals. Nd is the number of terminals in X-direction and Ne is the number of terminals in Y-direction 4. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip 5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body 6. Exact shape and size of this feature is optional 7. Package warpage max. 0.08 mm 8. Applied only for terminals Document Number: 64846 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Revision: 12-Jan-15 PAD Pattern www.vishay.com Vishay Siliconix Recommended Land Pattern PowerPAK® MLP66-40L 2.200 0.100 0.100 0.200 0.276 0.025 0.025 0.100 1 1 40 40 0.100 0.100 0.310 0.320 0.100 1.700 2.600 0.100 0.100 0.600 0.276 2.200 0.100 4.600 0.100 All Dimensions are in milimeters Revision: 28-Feb-14 Document Number: 67964 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. 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