[ /Title (CD2240 2) /Subject (Sync Generator for TV Applications and Video Process- CT T ODU CEMEN 7 R P E A 74 T L 7 E OL REP 00-442OBS ENDED 8 1 m s.co MM ions ECO pplicat p@harri R O N ral A centap Sync Cent : Call or email Semiconductor CD22402 Generator for TV Applications and Video Processing Systems May 1999 Features Description • Interlaced Composite Sync Output The Harris CD22402 (Note) is a CMOS LSI sync generator that produces all the timing signals required to drive a fully 2-to-1 interlaced 525-line 30-frame/second, or 625-line 25-frame/second TV camera or video processing system. A complete sync waveform is produced which begins each field with six serrated vertical sync pulses, preceded and followed by six half-width double frequency equalizing pulses. The sync output is gated by the master clock to preserve horizontal phase continuity during the vertical interval. • Automatic Genlock Capability • Crystal Oscillator Operation • 525 or 625 Line Operation • Vertical Reset Option • Wide Power Supply Operating Voltage . . . . . 4V to 15V Applications The CD22402 can be operated either in “genlock” mode, in which it is synchronized with a reference sync pulse train from another TV camera, or in “stand-alone” mode, in which it is synchronized with a local on-chip crystal oscillator (the crystal and two passive components are off chip). Also, the circuit can sense the presence or absence of a reference sync pulse train and automatically select the “genlock” or “stand-alone” mode. • Cameras • Monitors and Displays • CATV • Teletext • Video Games • Sync Restorer • Video Service Instruments Part Number Information PART NUMBER TEMP. RANGE (oC) PKG. NO. PACKAGE CD22402D -55 to 125 24 Ld SBDIP D24.6 CD22402E -40 to 85 24 Ld PDIP E24.6 A frame sync pulse is produced at the beginning of every odd field. The vertical counter can be reset to either the first equalizing pulse or the first vertical sync pulse of the vertical interval. The interlaced sync provided by the CD22402 differs from RS-170 by having slightly narrower sync and equalizing pulses. The clock frequency of 32 times horizontal rate allows for approximately 4µs horizontal pulse widths and 2µs equalizing pulses. Otherwise operation can be phase locked to a color sub-carrier for a full interlaced operating system. The CD22402 is operable with a single supply over a voltage range of 4V to 15V. Pinout CD22402 (PDIP, SBDIP) TOP VIEW DELAY, GENLOCK TO CRYSTAL OSCILLATOR 1 24 RESISTOR CONNECTION FOR GENLOCK OSCILLATOR CRYSTAL OSCILLATOR FEEDBACK TAP 2 23 MASTER FREQUENCY INPUT VSS 3 22 R-C CONNECTION FOR GENLOCK OSCILLATOR HORIZONTAL DRIVE OUTPUT 4 21 DELAY, GENLOCK TO CRYSTAL OSCILLATOR MIXED SYNC OUTPUT 5 20 GENLOCK INPUT (COMPOSITE SYNC) GENLOCK OSCILLATOR CAPACITOR CONNECTION 6 19 VDD MIXED BEAM BLANKING OUTPUT 7 18 525 LINE TO 625 LINE OPERATION SWITCH VERTICAL COUNTER RESET TO FIRST EQUALIZING PULSE 8 17 VERTICAL PROCESSING BLANKING OUTPUT VERTICAL DRIVE OUTPUT 9 16 SHORT VERTICAL DRIVE OUTPUT VERTICAL RESET TO FIRST VERTICAL SYNC PULSE 10 15 FRAME SYNC OUTPUT (ODD FIELD) HORIZONTAL CLAMP OUTPUT 11 14 HORIZONTAL PROCESSING BLANKING OUTPUT VSS 12 13 MIXED PROCESSING BLANKING OUTPUT CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1999 8-40 File Number 1686.5 CD22402 Pin Descriptions PIN NO. SYMBOL DESCRIPTION 1 XRC Delay, Genlock to Crystal Oscillator. Resistor, diode and capacitor connection for delay that automatically turns on the crystal oscillator when the genlock input is removed. When the signal on Terminal 1 is high the crystal oscillator is inhibited. Typical values for R and C are 1MΩ and 0.001µF. For operation as a crystal controlled stand alone sync generator without genlock, Terminal 1 should be hardwired to VSS. 2 XTP Crystal Oscillator Feedback Tap. Feedback connection (tap) for crystal oscillator. When a crystal (shunted by a 1MΩ resistor) is connected between this terminal and Terminal 23, and a 100pF capacitor is connected from this terminal to VSS, the sync generator creates its own master frequency. For a 525-line, 30-frame/second raster, the crystal frequency is 504.000kHz (Note 1); and for a 625-line, 25-frame/second raster, the crystal frequency is 500.000kHz (Note 1). 3 VSS Negative Power Supply Voltage. This terminal must be hardwired to Terminal 12 (VSS). 4 HD Horizontal Drive Output 5 MS Mixed Sync Output 6 C 7 MBB Mixed Beam Blanking Output 8 VRE Vertical Counter Reset to First Equalizing Pulse. A low level signal on this terminal resets the vertical counter to the first equalizing pulse of a field. When not in use this terminal should be connected to VDD. 9 VD 10 VRV 11 HC Horizontal Clamp Output 12 VSS Negative Power Supply Voltage 13 MPB Mixed Processing Blanking Output 14 HPB Horizontal Processing Blanking Output 15 FS2 Frame Sync Output (Odd Field). A pulse coinciding with the first equalizing pulse is produced at the beginning of every odd field. 16 SVD Short Vertical Drive Output 17 VPB Vertical Processing Blanking Output 18 SW Operation Switch for 525-Line or 625-Line Raster. A high level signal on Terminal 18 causes the sync generator to generate a 625-line raster. An internal pulldown resistor is connected to Terminal 18, so in the absence of an applied input to this terminal, a 525-line raster is produced. 19 VDD Positive Power Supply Voltage. VDD can be any voltage between +4 and +15 relative to VSS . 20 GEN Genlock Input Composite Sync. A negative going reference mixed sync waveform applied to Terminal 20 disables the crystal oscillator and locks the R-C genlock oscillator to the horizontal pulses of the reference sync waveform. Vertical sync detection is achieved by an R-C integrator connected from Terminal 20 to Terminal 10 (vertical reset to first vertical sync pulse). An internal pull-up resistor is connected to Terminal 20 so that in the absence of an applied input the crystal oscillator is enabled and the R-C genlock oscillator is disabled. 21 XR Delay, Genlock to Crystal Oscillator, Resistor and Diode Connection for Delay, Genlock to Crystal Oscillator. Automatically turns on the crystal oscillator when the input to Terminal 20 is removed. 22 RC Resistor and Capacitor Connection for Genlock Oscillator. If the genlock oscillator is not used this terminal should be connected to VSS. C should be 100pF, and R should be a 10kΩ potentiometer. 23 XIN Master Frequency Input. 24 R Capacitor Connection for R-C Genlock Oscillator Vertical Drive Output Vertical Counter Reset to First Vertical Sync Pulse. A low level signal on this terminal resets the sync generator to the first vertical sync pulse of a field. For genlock operation, Terminal 10 is used as a resistor and capacitor connection for an integrator network that detects vertical sync pulses in a master sync waveform to which the sync generator is to be genlocked. R is 22kΩ, and C is 0.001µF. When not in use this terminal should be connected to VDD. Resistor Connection for Genlock Oscillator. NOTE: 32 times horizontal frequency. 8-41 CD22402 Block Diagram CD22402 MONOCHROME TV SYNC GENERATOR WITH AUTOMATIC GENLOCK VRV R RC C VRE SW 24 22 6 8 18 10 GEN 20 XR 21 XRC 1 VERTICAL COUNTER ÷525/625 HORIZONTAL COUNTER ÷16 R-C GENLOCK OSCILLATOR ÷2 FIELD DECODER LINE DECODER AUTOMATIC GENLOCK CONTROL COMPOSITE DECODER XIN 23 XTP 2 CRYSTAL OSCILLATOR VSS = PINS 3 AND 12 VDD = PIN 19 FRAME SYNC DECODER 14 11 4 5 HPB HC HD MS 8-42 13 7 MPB MBB 15 16 FS2 SVD 9 17 VD VPB CD22402 Absolute Maximum Ratings Thermal Information DC Supply Voltage (Referenced to VSS Terminal) . . . . . . . . . . . 15V Input Voltage Range, All Inputs (Notes 2, 3) . . . . . . VSS ≤ VI ≤ VDD DC Input Current, Any One Input (Note 2) . . . . . . . . . . . . . . ±10mA Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W) SBDIP Package . . . . . . . . . . . . . . . . . . 50 10 PDIP Package . . . . . . . . . . . . . . . . . . . 50 N/A Maximum Junction Temperature (SBDIP Package) . . . . . . . . 175oC Maximum Junction Temperature (PDIP Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range CD22402D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC CD22402E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured with the component mounted on an evaluation PC board in free air. 2. To prevent damage to the input protection circuit, input signals should never be greater than VDD nor less than VSS. Input currents must not exceed 10mA even when the power is off. 3. A connection must be provided at every input terminal. All unused inputs must be connected to VDD or VSS, whichever is appropriate. Electrical Specifications Values at -55oC, 25oC, 125oC Apply to D Package Values at -40oC, 25oC, 85oC Apply to E Package TEST CONDITIONS PARAMETER SYMBOL 25oC VO (V) VDD (V) -55oC -40oC 85oC 125oC MIN TYP MAX UNITS - 5 - - - - 0.5 0.75 1 mA - 10 - - - - 1.5 2 2.5 mA - 15 - - - - 3 4 5 mA 0.5 5 100 96 66 56 80 160 - µA 5 5 1200 1155 787 672 960 1920 - µA 0.5 10 248 239 164 140 200 400 - µA 10 10 3000 2868 1968 1680 2400 4800 - µA 4.5 5 -100 -96 -66 -56 -80 -160 - µA 0 5 -1200 -1155 -787 -672 -960 -1920 - µA 9.5 10 -248 -239 -164 -140 -200 -400 - µA 0 10 -3000 -2868 -1968 -1680 -2400 -4800 - µA - 5 0.15 0.15 0.15 0.15 - - 0.15 V - 10 0.15 0.15 0.15 0.15 - - 0.15 V - 5 4.85 4.85 4.85 4.85 4.85 - - V - 10 9.85 9.85 9.85 9.85 9.85 - - V 0.5, 4.5 5 1.5 1.5 1.4 1.4 - 2.25 1.5 V 1, 9 10 3 3 2.9 2.9 - 4.5 3 V 0.5, 4.5 5 3.6 3.6 3.5 3.5 3.5 2.25 - V 1, 9 10 7.1 7.1 7 7 7 4.5 - V - - - - - - - 10 - pA DC ELECTRICAL SPECIFICATIONS Quiescent Device Current Output Low (Sink) Current Output High (Source) Current Output Voltage Low Level Output Voltage High Level Input Low Voltage Input High Voltage Input Current IDD (Max) IOL (Min) IOH (Min) VOL (Max) VOH (Min) VIL (Max) VIH (Min) IIN (Max) Refer to the CD4000B Series data book 250.5 for general operating and application considerations. 8-43 CD22402 Switching Electrical Specifications TA = 25oC and CL = 15pF. Typical Temperature Coefficient for All Values of VDD = 0.3%/oC TEST CONDITIONS SYMBOL VDD (V) MIN TYP MAX UNITS Low-to-High Level tPLH 5 - 40 80 ns High-to-Low Level tPHL 10 - 20 40 ns Low-to-High tTLH 5 - 45 90 ns High-to-Low tTHL 10 - 30 60 ns CI - - 5 - pF PARAMETER (NOTE 4) Output State Propagation Delay Time (50% to 50%) Output State Transition Time (10% to 90%) Input Capacitance (Per Input) NOTE: 4. The characteristics given are defined for unbuffered gate in the CMOS process of the CD22402. Logic Diagram VERTICAL DRIVE (VERT. RESET TO FIRST VERT. PULSE) 51pF 22 INTEGRATOR 10 + 20 GENLOCK SYNC HOR. DR R Q S Q 10K 10K 24 6 GENLOCK OSC. S Q R Q (NOTE 5) 21 1M 1N914 1 0.001µF (NOTE 6) 23 CRYSTAL 32 TIMES HORIZ. 503.496kHz 1M 2 HOR. PROCESS BLANKING 100pF NOTES: 5. Pin 21 high when pin 20 is high (or open). 6. Pin 1 high inhibits clock. FIGURE 1. DETAIL OF THE OSCILLATOR/GENLOCK PORTION OF THE CD22402 8-44 CLOCK TO COUNTERS CD22402 Timing Waveforms 0 MICROSECONDS 504kHz OSC. PIN 2 OR 6 1.98 3.97 5.95 7.94 9.92 11.90 27.78 31.75 33.73 11.9µs MIXED BLANKING PIN 13 3.97µs HORIZ. DRIVE PIN 4 MIXED BEAM (CATHODE) BLANKING PIN 7 7.94µs 1.98µs HORIZ. CLAMP PIN 11 3.97µs H. SYNC 1.98µs MIXED SYNC PIN 5 1.98µs EQUALIZING PULSE 25.8µs V. SYNC 3.97µs FIGURE 2. SYNC GENERATOR TIMING - 525/60Hz, HORIZONTAL TIMING WAVEFORMS VERTICAL RESET TO FIRST VERTICAL PULSE TO FIRST EQUALIZING PULSE 0 LINE NO MIXED SYNC PIN 5 1 2 3 4 5 6 7 8 9 0.57ms VERT. DRIVE PIN 9 VERTICAL PROCESSING BLANKING PIN 17 1.33ms WIDE BLANKING PIN 13 0.19ms SHORT VERTICAL DRIVE PIN 16 MIXED BEAM (CATHODE) BLANKING PIN 7 FRAME SYNC PIN 15 (ON ALTERNATE FIELDS) 1.98µs (NOT TO SCALE) FIGURE 3. SYNC GENERATOR TIMING - 525/60Hz, VERTICAL TIMING WAVEFORMS 8-45 10 21 CD22402 Timing Waveforms (Continued) 0 MICROSECONDS 500kHz OSC. PIN 2 OR 6 2 4 6 8 10 12 28 32 12µs MIXED BLANKING PIN 13 4µs HORIZ. DRIVE PIN 4 CATHODE BLANKING PIN 7 8µs 2µs HORIZ. CLAMP PIN 11 4µs H. SYNC 2µs MIXED SYNC PIN 5 2µs EQUALIZING PULSE 26µs V. SYNC 4µs FIGURE 4. SYNC GENERATOR TIMING - 625/50Hz, HORIZONTAL TIMING WAVEFORMS VERTICAL RESET TO FIRST VERTICAL PULSE VERTICAL RESET TO FIRST EQUALIZING PULSE LINE NO MIXED SYNC PIN 5 0 1 2 3 4 5 6 7 8 9 0.57ms VERT. DRIVE PIN 9 VERTICAL PROCESSING BLANKING PIN 17 1.36ms WIDE BLANKING PIN 13 0.194ms SHORT VERTICAL DRIVE PIN 16 CATHODE BLANKING PIN 7 FRAME SYNC PIN 15 (ON ALTERNATE FIELDS) 2µs (NOT TO SCALE) FIGURE 5. SYNC GENERATOR TIMING - 625/50Hz, VERTICAL TIMING WAVEFORMS 8-46 10 21 CD22402 Timing Waveforms FIELD NO. 1 (Continued) LINE 0 LINE 9 FIRST EQUALIZING PULSE PIN 5 2 CLKS 1 CLK PIN 9 2 CLKS 2 CLKS FIELD NO. 2 LINE 271 (321) LINE 262-1/2 (312-1/2) PIN 5 1 CLK 1 CLK PIN 9 14 CLKS 2 CLKS SEE NOTES 1, 2 FIGURE 6. EXPANDED VERTICAL-TIMING WAVEFORM DETAIL OF SYNC GENERATOR TIMING (VERTICAL DRIVE - PIN 9) FIELD NO. 1 LINE 0 LINE 21 FIRST EQUALIZING PULSE PIN 5 2 CLKS 1 CLK PIN 17 2 CLKS 2 CLKS FIELD NO. 2 LINE 283 (333) LINE 262-1/2 (312-1/2) PIN 5 1 CLK 2 CLKS PIN 17 14 CLKS 2 CLKS SEE NOTES 1, 2 FIGURE 7. EXPANDED VERTICAL-TIMING WAVEFORM DETAIL OF SYNC GENERATOR TIMING (VERTICAL PROCESSING BLANKING - PIN 17) 8-47 CD22402 Timing Waveforms FIELD NO. 1 (Continued) LINE 0 LINE 21 FIRST EQUALIZING PULSE PIN 5 1 CLK 2 CLKS 1 CLK PIN 13 1 CLK 2 CLKS FIELD NO. 2 6 CLKS LINE 283 (333) LINE 262-1/2 (312-1/2) PIN 5 PIN 13 1 CLK 2 CLKS 14 CLKS 2 CLKS SEE NOTES 1, 2 FIGURE 8. EXPANDED VERTICAL-TIMING WAVEFORM DETAIL OF SYNC GENERATOR TIMING (MIXED PROCESSING BLANKING - PIN 13) FIELD NO. 1 LINE 6 LINE 3 PIN 5 1 CLK 2 CLKS 2 CLKS PIN 16 FIELD NO. 2 LINE 265-1/2 (315-1/2) LINE 268-1/2 (318-1/2) PIN 5 PIN 16 2 CLKS 2 CLKS SEE NOTES 1, 2 FIGURE 9. EXPANDED VERTICAL-TIMING WAVEFORM DETAIL OF SYNC GENERATOR TIMING (SHORT VERTICAL DRIVE - PIN 16) 8-48 CD22402 Timing Waveforms (Continued) LINE 2 LINE 6 LINE 3 LINE 7 PIN 5 15 CLKS 1 CLK PIN 7 4 CLKS LINE 265 (315) 2 CLKS LINE 265-1/2 (315-1/2) 2 CLKS 4 CLKS LINE 268-1/2 (318-1/2) LINE 269 (319) PIN 5 1 CLK PIN 7 15 CLKS 4 CLKS 2 CLKS 2 CLKS 16 CLKS SEE NOTES 7, 8 NOTES: 7. Waveforms shown are for 525 line/60Hz, line number in parenthesis are for (625 line/50Hz). 8. Timing widths by clock count; for 525 line, 1 CLK = 1.98µs; for 625 line, 1 CLK = 2µs; 1 horizontal period = 32 CLKS. FIGURE 10. EXPANDED VERTICAL-TIMING WAVEFORM DETAIL OF SYNC GENERATOR TIMING (MIXED BEAM BLANKING - PIN 7) Typical Applications (Refer to Application Note AN8742, for more information) VDD HORIZ. PHASE ADJ. HORIZ. MIXED SYNC. OR COMPOSITE VIDEO INPUT φ SYNC RESTORER VERT. VERTICAL SYNC (OPTIONAL) FROM SHORT VERTICAL DRIVE FROM POWER LINE FOR LINE-LOCK OPERATION ZERO CROSSING DETECTOR 20 19 10 8 6 4 11 7 13 14 HORIZONTAL DRIVE HORIZONTAL CLAMP MIXED BEAM (CATHODE) BLANKING MIXED PROCESSING BLANKING HORIZONTAL PROCESSING BLANKING 100pF 22 GEN LOCK OSC. 10kΩ 9 VERTICAL DRIVE 24 16 SHORT VERTICAL DRIVE PLL 1 AUTO GEN LOCK CONTROL 5 MIXED SYNC 1MΩ 21 23 1MΩ CRYSTAL OSC. 100pF 2 15 17 FRAME SYNC OUTPUT (ODD FIELD) VERTICAL PROCESSING BLANKING OUTPUT 3, 12 18 OPERATION SWITCH FOR 525-LINE OR 625-LINE RASTER FIGURE 11. TYPICAL APPLICATION IN A TV CAMERA 8-49 CD22402 13 100kΩ 3.3µF 10kΩ 75Ω 12 4 14 + NEG. HORIZ. SYNC OUT (TO PIN 20 - CD22402) 1kΩ 2 3 1 0.1µF 1 + 5 100kΩ 0.0022µF 0.5 TO 2VP-P VIDEO SIGNAL IN 6 + 2 7 - POS. HORIZ. SYNC OUT 10kΩ 1N914 2MΩ 0.0022µF VSS VDD 10kΩ 9 - 0.0022µF 2kΩ VCC = +5 10µF 2kΩ 10µF 10 3 + 8 NEG. VERTICAL SYNC OUT (TO PIN 10 - CD22402) CA5470 BIMOS-E QUAD OP AMP PIN 4 TO +5V (VDD) PIN 11 TO GND (VSS) GND NOTE: The genlock input to pins 10 and 20 of the CD22402 are direct coupled to the output from Pins 8 and 14 of the CA5470. Refer to Application Note AN-8742 for additional information. FIGURE 12. SUGGESTED SYNC-SEPARATOR CIRCUIT USING THE CA5470 BIMOS-E QUAD OP AMP IN THE VDD RANGE OF 4V TO 12V 8-50