RFD16N05L, RFD16N05LSM Data Sheet 16A, 50V, 0.047 Ohm, Logic Level, N-Channel Power MOSFETs These are N-Channel logic level power MOSFETs manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use with logic level (5V) driving sources in applications such as programmable controllers, automotive switching, switching regulators, switching converters, motor relay drivers and emitter switches for bipolar transistors. This performance is accomplished through a special gate oxide design which provides full rated conductance at gate biases in the 3V to 5V range, thereby facilitating true on-off power control directly from logic circuit supply voltages. April 1999 File Number 2269.2 Features • 16A, 50V • rDS(ON) = 0.047Ω • UIS SOA Rating Curve (Single Pulse) • Design Optimized for 5V Gate Drives • Can be Driven Directly from CMOS, NMOS, TTL Circuits • Compatible with Automotive Drive Requirements • SOA is Power Dissipation Limited • Nanosecond Switching Speeds • Linear Transfer Characteristics • High Input Impedance Formerly developmental type TA09871. • Majority Carrier Device Ordering Information • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” PART NUMBER PACKAGE BRAND RFD16N05L TO-251AA RFD16N05L RFD16N05LSM TO-252AA RFD16N05LSM Symbol D NOTE: When ordering, include the entire part number. Add the suffix 9A to obtain the TO-252AA variant in tape and reel, i.e. RFD16N05LSM9A G S Packaging JEDEC TO-251AA JEDEC TO-252AA SOURCE DRAIN GATE DRAIN (FLANGE) DRAIN (FLANGE) GATE SOURCE 6-163 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 RFD16N05L, RFD16N05LSM Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg RFD16N05L, RFD16N05LSM 50 50 16 45 ±10 60 0.48 -55 to 150 UNITS V V A A V W W/oC oC 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BVDSS ID = 250mA, VGS = 0V, Figure 10 50 - - V Gate to Threshold Voltage VGS(TH) VGS = VDS, ID = 250mA, Figure 9 1 - 2 V VDS = 40V, VGS = 0V TC = 150oC - - 1 µA - - 50 µA VGS = ±10V, VDS = 0V - - 100 nA ID = 16A, VGS = 5V - - 0.047 Ω ID = 16A, VGS = 4V - - 0.056 Ω VDD = 25V, ID = 8A, VGS = 5V, RGS = 12.5Ω Figures 15, 16 - - 60 ns - 14 - ns tr - 30 - ns td(OFF) - 42 - ns tf - 14 - ns t(OFF) - - 100 ns - - 80 nC - - 45 nC - - 3 nC Zero Gate Voltage Drain Current IDSS Gate to Source Leakage Current Drain to Source On Resistance (Note 2) IGSS rDS(ON) Turn-On Time t(ON) Turn-On Delay Time td(ON) Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Qg(TOT) VGS = 0V to 10V Gate Charge at 5V Qg(5) VGS = 0V to 5V Qg(TH) VGS = 0V to 1V Threshold Gate Charge VDD = 40V, ID = 16A, RL = 2.5Ω Figures 17, 18 Thermal Resistance Junction to Case RθJC - - 2.083 oC/W Thermal Resistance Junction to Ambient RθJA - - 100 oC/W MIN TYP MAX UNITS ISD = 16A - - 1.5 V ISD = 16A, dISD/dt = 100A/µs - - 125 ns Source to Drain Diode Specifications PARAMETER SYMBOL Source to Drain Diode Voltage VSD Diode Reverse Recovery Time trr TEST CONDITIONS NOTES: 2. Pulse Test: Pulse Width ≤ 300ms, Duty Cycle ≤ 2%. 3. Repetitive Rating: Pulse Width limited by max junction temperature. 6-164 RFD16N05L, RFD16N05LSM Typical Performance Curves Unless Otherwise Specified POWER DISSIPATION MULTIPLIER 1.2 20 ID, DRAIN CURRENT (A) 1.0 0.8 0.6 0.4 15 10 5 0.2 0 0 0 25 50 75 100 TC , CASE TEMPERATURE (oC) 125 150 25 FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE ID MAX CONTINUOUS 10 OPERATION IN THIS AREA LIMITED BY rDS(ON) DC 1 0.1 IDS, DRAIN TO SOURCE CURRENT (A) VGS = 4V TC = 25oC PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX. VGS = 5V 30 VGS = 3V 15 VGS = 2V 0 0 6.0 1.5 3.0 4.5 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 5. SATURATION CHARACTERISTICS 6-165 STARTING TJ = 25oC STARTING TJ = 150oC 10 If R = 0 tAV = (L)(IAS)/(1.3 RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3 RATED BVDSS - VDD) +1] 0.10 1 tAV, TIME IN AVALANCHE (ms) 10 FIGURE 4. UNCLAMPED INDUCTIVE SWITCHING SOA (SINGLE PULSE UIS SOA) 7.5 IDS(ON), DRAIN TO SOURCE ON CURRENT (A) FIGURE 3. FORWARD BIAS SAFE OPERATING AREA 45 Idm 1 0.01 102 10 VDS, DRAIN TO SOURCE VOLTAGE (V) VGS = 10V 150 102 TC = 25oC TJ = MAX RATED 1 75 100 125 TC , CASE TEMPERATURE (oC) FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) 102 50 45 VDS = 15V PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 30 15 0 0 1.5 3.0 4.5 VGS, GATE TO SOURCE VOLTAGE (V) FIGURE 6. TRANSFER CHARACTERISTICS 6.0 RFD16N05L, RFD16N05LSM Typical Performance Curves Unless Otherwise Specified (Continued) 2.5 ID = 16V VDS = 15V 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 4 5 6 VGS, GATE TO SOURCE VOLTAGE (V) 0.5 1.0 0.9 0.8 0.7 0 50 100 150 1.0 0.8 0.6 0 -50 200 VGS = 0V f = 1MHz 1600 CISS 1200 CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGD 800 COSS 400 CRSS 5 10 15 20 200 150 50 37.5 25 10 RL = 3.125Ω, VGS = 5V IG(REF) = 0.60mA PLATEAU VOLTAGES IN DESCENDING ORDER: VDD = BVDSS V = 0.75 BV VDD = BVDSS VDD = 0.50 BVDSS VDD = BVDSS DD DSS VDD = 0.25 BVDSS GATE SOURCE VOLTAGE 25 FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 8 6 4 12.5 2 DRAIN SOURCE VOLTAGE 0 VDS, DRAIN TO SOURCE VOLTAGE (V) 6-166 100 FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE VDS , DRAIN TO SOURCE VOLTAGE (V) 2000 50 0 TJ, JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED GATE THRESHOLD vs JUNCTION TEMPERATURE C, CAPACITANCE (pF) 200 150 1.2 TJ, JUNCTION TEMPERATURE (oC) 0 100 ID = 250µA 1.1 0 50 0 FIGURE 8. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE NORMALIZED GATE THRESHOLD VOLTAGE 1.0 1.4 1.2 0.6 -50 1.5 TJ, JUNCTION TEMPERATURE (oC) ID = 250µA VGS = VDS 1.3 2.0 0 -50 7 FIGURE 7. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 1.4 ID = 16A PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX. 0 I G ( REF ) 20 ------------------------I G ( ACT ) t, TIME (µs) I G ( REF ) 80 ------------------------I G ( ACT ) FIGURE 12. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT VGS , GATE TO SOURCE VOLTAGE (V) 1.3 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX. NORMALIZED DRAIN TO SOURCE ON RESISTANCE NORMALIZED DRAIN TO SOURCE ON RESISTANCE 1.4 RFD16N05L, RFD16N05LSM Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN + RG REQUIRED PEAK IAS VDS IAS VDD VDD - VGS DUT tP 0V IAS 0 0.01Ω tAV FIGURE 13. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 14. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(ON) td(OFF) tf tr RL VDS 90% 90% + RG - VDD 10% 10% 0 DUT 90% VGS VGS 0 FIGURE 15. SWITCHING TIME TEST CIRCUIT 0.2µF 50% PULSE WIDTH 10% FIGURE 16. RESISTIVE SWITCHING WAVEFORMS VDS (ISOLATED SUPPLY) CURRENT REGULATOR 12V BATTERY 50% VDD Qg(TOT) SAME TYPE AS DUT 50kΩ Qgd 0.3µF VGS Qgs D VDS DUT G 0 IG(REF) S 0 IG CURRENT SAMPLING RESISTOR VDS ID CURRENT SAMPLING RESISTOR FIGURE 17. GATE CHARGE TEST CIRCUIT 6-167 IG(REF) 0 FIGURE 18. GATE CHARGE WAVEFORMS RFD16N05L, RFD16N05LSM Spice Model (RFD16N05L) .SUBCKT RFD16N05L 2 1 3; rev 04/08/92 *Nominal Temperature = 25oC .MODEL MOSMOD NMOS (VTO=2.054 KP=24.73 IS=1e-30 N=10 TOX=1 L=1u W=1u) Vto 21 6 0.448 Rsource 8 7 RDSMOD 0.614E-3 Rdrain 5 16 RDSMOD 27.38E-3 .MODEL RDSMOD RES (TC1=3.66E-3 TC2=1.46E-5) .MODEL RVTOMOD RES (TC1=-1.81E3 TC2=1.41E-6) Ebreak 11 7 17 18 70.9 .MODEL RBKMOD RES (TC1=1.01E-3 TC2=5.21E-8) .MODEL DBKMOD D (RS=8.82E-2 TRS1=-2.01E-3 TRS2=7.32E-10) .MODEL DBDMOD D (IS=1.34E-13 RS=1.21E-2 TRS1=1.64E-3 TRS2=2.59E-6 +CJO=1.13E-9 Cin 6 8 1.21E-9 Ca 12 8 3.33E-9 .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4.25 VOFF=-2.25) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.25 VOFF=-4.25) .MODEL DPLCAPMOD D (CJO=5.22E-10 IS=1e-30 N=10) Cb 15 14 3.11E-9 .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.65 VOFF=4.35) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=4.35 VOFF=-0.65) Rgate 9 20 2.98 Lgate 1 9 1.38E-9 Ldrain 2 5 1.0E-12 Lsource 3 7 1.0E-9 Dbody 7 5 DBDMOD Dbreak 5 11 DBKMOD Dplcap 10 5 DPLCAPMOD Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evto 20 6 18 8 1 It 8 17 1 MOS1 16 6 8 8 MOSMOD M=0.99 MOS2 16 21 8 8 MOSMOD M=0.01 Rbreak 17 18 RBKMOD 1 Rin 6 8 1e9 Rvto 18 19 RVTOMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 8 19 DC 1 .ENDS TT=4.14E-8) x All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 6-168