TI SN65LVDS116DGG

SN65LVDS116
16-PORT LVDS REPEATER
SLLS370A – SEPTEMBER 1999 – REVISED SEPTEMBER 1999
D
D
D
D
D
D
D
D
D
D
D
DGG PACKAGE
(TOP VIEW)
One Receiver and Sixteen Line Drivers
Meet or Exceed the Requirements of ANSI
EIA/TIA-644 Standard
Designed for Signaling Rates Up to
622 Mbps
Enabling Logic Allows Separate Control of
Each Bank of Four Channels or 2-Bit
Selection of Any One of the Four Banks
Low-Voltage Differential Signaling With
Typical Output Voltage of 350 mV and a
100 Ω Load
Electrically Compatible With LVDS, PECL,
LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT,
SSTL, or HSTL Outputs With External
Termination Networks
Propagation Delay Times <4.7 ns
Output Skew is < 300 ps and Part-to-Part
Skew <1.5 ns
Total Power Dissipation Typically 470 mW
With All Ports Enabled and at 200 MHz
Driver Outputs or Receiver Input is High
Impedance when Disabled or With
VCC <1.5 V
Bus-Pin ESD Protection Exceeds 12 kV
Packaged in Thin Shrink Small-Outline
Package With 20 Mil Terminal Pitch
GND
VCC
VCC
GND
ENA
ENA
NC
NC
NC
ENB
ENB
NC
NC
NC
GND
VCC
VCC
GND
A
B
NC
ENC
ENC
S0
S1
SM
END
END
GND
VCC
VCC
GND
description
1
64
2
63
3
62
4
61
5
60
6
59
7
58
8
57
9
56
10
55
11
54
12
53
13
52
14
51
15
50
16
49
17
48
18
47
19
46
20
45
21
44
22
43
23
42
24
41
25
40
26
39
27
38
28
A1Y
A1Z
A2Y
A2Z
A3Y
A3Z
A4Y
A4Z
B1Y
B1Z
B2Y
B2Z
B3Y
B3Z
B4Y
B4Z
C1Y
C1Z
C2Y
C2Z
C3Y
C3Z
C4Y
C4Z
D1Y
D1Z
D2Y
D2Z
D3Y
D3Z
D4Y
D4Z
37
The SN65LVDS116 is one differential line reciever
29
36
connected to sixteen differential line drivers that
30
35
implement the electrical characteristics of
31
34
low-voltage differential signaling (LVDS). LVDS,
32
33
as specified in EIA/TIA-644, is a data signaling
technique that offers the low-power, low-noise
coupling, and switching speeds to transmit data at speeds up to 622 Mbps and relatively long distances. (Note:
The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media,
the noise coupling to the environment, and other system characteristics.)
The intended application of this device and signaling technique is for point-to-point or multidrop baseband data
transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed
circuit board traces, backplanes, or cables. The large number of drivers integrated into the same substrate along
with the low pulse skew of balanced signaling, allows extremely precise timing alignment of the signals repeated
from the input. This is particularly advantageous in system clock distribution.
The SN65LVDS116 is characterised for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
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1
SN65LVDS116
16-PORT LVDS REPEATER
SLLS370A – SEPTEMBER 1999 – REVISED SEPTEMBER 1999
logic diagram (positive logic)
A1Y
A1Z
A2Y
S0
S1
SM
A2Z
A3Y
ENA
A3Z
ENA
A4Y
A4Z
B1Y
B1Z
B2Y
B2Z
B3Y
ENB
B3Z
ENB
B4Y
B4Z
A
B
C1Y
C1Z
C2Y
C2Z
C3Y
ENC
C3Z
ENC
C4Y
C4Z
D1Y
D1Z
D2Y
D2Z
D3Y
END
D3Z
END
D4Y
D4Z
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN65LVDS116
16-PORT LVDS REPEATER
SLLS370A – SEPTEMBER 1999 – REVISED SEPTEMBER 1999
FUNCTION TABLE
OUTPUT
INPUT
VID = VA - VB
X
SM
EN
EN
S1
S0
AY
AZ
BY
BZ
CY
CZ
DY
DZ
VID ≥100 mV
–100 mV < VID < 100 mV
H
L
X
X
H
H
L
X
X
Z
X
H
Z
Z
L
H
Z
Z
L
H
Z
Z
Z
L
H
H
H
L
X
X
?
?
?
?
L
?
?
?
?
VID ≤ –100 mV
X
H
H
H
X
L
X
H
X
X
L
X
Z
H
L
Z
Z
H
L
H
L
H
Z
Z
Z
Z
Z
VID ≥ 100 mV
–100 mV < VID < 100 mV
L
X
L
X
X
X
L
L
L
L
H
L
?
?
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
VID ≤ –100 mV
VID ≥ 100 mV
L
X
X
L
L
L
Z
H
Z
Z
Z
Z
Z
Z
–100 mV < VID < 100 mV
L
L
X
X
X
X
L
H
L
H
Z
Z
H
L
Z
Z
Z
Z
Z
Z
?
?
Z
Z
Z
VID ≤ –100 mV
VID ≥ 100 mV
L
X
X
L
Z
H
Z
Z
L
H
Z
Z
Z
Z
–100 mV < VID < 100 mV
L
L
X
X
X
X
H
L
Z
Z
Z
Z
H
L
Z
Z
H
L
Z
Z
Z
Z
?
?
Z
Z
VID ≤ –100 mV
VID ≥ 100 mV
L
X
X
L
X
X
H
L
Z
Z
Z
Z
L
H
Z
Z
H
H
Z
Z
Z
Z
Z
Z
H
–100 mV < VID < 100 mV
L
X
X
L
H
H
Z
Z
Z
Z
Z
Z
?
?
VID ≤ –100 mV
L
X
X
H
H
Z
H = high level, L = low level, Z = high impedance, ? = indeterminate
Z
Z
Z
Z
Z
L
H
equivalent input and output schematic diagrams
VCC
VCC
VCC
300 kΩ
(EN and SM Only)
300 kΩ
300 kΩ
Enable
Inputs
A Input
B Input
50 Ω
10 kΩ
7V
5Ω
Y or Z
Output
7V
300 kΩ
7V
7V
(EN, S0, and S1 Only)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN65LVDS116
16-PORT LVDS REPEATER
SLLS370A – SEPTEMBER 1999 – REVISED SEPTEMBER 1999
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
Input voltage range, Enable inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
A, B, Y or Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
Electrostatic discharge, Y, Z, and GND (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A:12 kV, B: 500 V
All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A: 4 kV, B: 400 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
2. Tested in accordance with MIL-STD-883C Method 3015.7.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR‡
ABOVE TA = 25°C
TA = 85°C
POWER RATING
DGG
2094 mW
16.7 mW/°C
1089 mW
‡ This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-k)
with no air flow.
recommended operating conditions
MIN
NOM
Supply voltage, VCC
3
3.3
High-level input voltage, VIH
2
Low-level input voltage, VIL
Magnitude of differential input voltage, VID
0.1
V
Ť
Common–mode input voltage, VIC
Operating free-air temperature, TA
4
ID
2
• DALLAS, TEXAS 75265
UNIT
3.6
V
V
0.8
V
3.6
V
V
Ť
–40
POST OFFICE BOX 655303
MAX
Ť
2.4 –
ID
2
Ť
VCC – 0.8
85
V
V
°C
SN65LVDS116
16-PORT LVDS REPEATER
SLLS370A – SEPTEMBER 1999 – REVISED SEPTEMBER 1999
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VITH+
VITH–
Positive-going differential input voltage threshold
VOD
Differential output voltage magnitude
∆VOD
Change in differential output voltage magnitude
between logic states
VOC(SS)
Steady-state common-mode output voltage
∆VOC(SS)
Change in steady-state common-mode output
voltage between logic states
VOC(PP)
Peak-to-peak common-mode output voltage
ICC
Supply current
II
Input current (A or B inputs)‡
VI = 0 V
VI = 2.4 V
II(OFF)
Power-off Input current (A or B inputs)
VCC= 1.5 V,
IIH
High level input current
High-level
IIL
Low level input current
Low-level
IOS
Short circuit output current
Short-circuit
IOZ
IO(OFF)
High-impedance output current
Negative-going differential input voltage threshold
See Figure 1 and Table 1
RL= 100Ω,
100Ω
VID= ±100 mV,
mV
See Figure 1 and Figure 2
See Figure 3
Enabled,
MIN
ENx, SM
ENx, S0, S1
ENx, SM
–100
247
340
50
1.125
1.375
–50
50
RL = 100Ω
50
150
84
115
3.2
6
–2
–20
–1.2
VI= 2.4 V
20
20
VIH = 2 V
–20
10
VIL = 0
0.8
8V
–10
±24
±12
VO = 0 V or VCC
VCC = 1.5 V,
VO = 3.6 V
VI = 0.4 sin (4E6πt) + 0.5 V
CIN
UNIT
mV
454
–50
VOY or VOZ = 0 V
VOD = 0 V
Power-off output current
MAX
100
Disabled
ENx, S0, S1
TYP†
mV
V
mV
mA
µA
µA
µA
µA
mA
±1
µA
±1
µA
Input capacitance (A or B inputs)
5
pF
CO
Output capacitance (Y or Z outputs)
VI = 0.4 sin (4E6πt) + 0.5 V
9.4
† All typical values are at 25°C and with a 3.3 V supply.
‡ The non-algebraic convention, where the more positive (least negative) limit is designated minimum, is used in this data sheet for the input current
(II) only.
switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
tPLH
tPHL
Propagation delay time, low-to-high-level output
2.2
3.1
4.7
Propagation delay time, high-to-low-level output
2.2
3.1
4.7
tr
tf
Differential output signal rise time
0.3
0.8
1.2
0.3
0.8
1.2
tsk(p)
tsk(o)
tsk(pp)
tPZH
tPZL
tPHZ
RL = 100 Ω,
CL = 10 pF,
See Figure 4
Differential output signal fall time
Pulse skew (|tPHL - tPLH|)‡
140
500
Output skew, channel-to-channel§
Part-to-part skew¶
100
300
Propagation delay time, high-impedance-to-high-level output
5.7
15
Propagation delay time, high-impedance-to-low-level output
7.7
15
3.2
15
1.5
Propagation delay time, high-level-to-high-impedance output
See Figure 5
UNIT
ns
ns
ps
ns
ns
tPLZ
Propagation delay time, low-level-to-high-impedance output
3.2
15
ns
† All typical values are at 25°C and with a 3.3 V supply.
‡ tsk(p) is the magnitude of the time difference between the tPLH and tPHL of any output of a single device.
§ tsk(o) is the magnitude of the time difference between the tPLH or tPHL measured at any two outputs.
¶ tsk(pp) is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN65LVDS116
16-PORT LVDS REPEATER
SLLS370A – SEPTEMBER 1999 – REVISED SEPTEMBER 1999
PARAMETER MEASUREMENT INFORMATION
IIA
IIB
VID
IOY
A
Y
B
Z
IOZ
VOD
VOY
GND
VIA
VOC
VOZ
VIB
(VOY + VOZ)/2
Figure 1. Voltage and Current Definitions
Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages
APPLIED VOLTAGES
RESULTING DIFFERENTIAL
INPUT VOLTAGE
RESULTING COMMONMODE INPUT VOLTAGE
VIA
1.25 V
VIB
1.15 V
VID
100 mV
VIC
1.2 V
1.15 V
1.25 V
-100 mV
1.2 V
2.4 V
2.3 V
100 mV
2.35 V
2.3 V
2.4 V
-100 mV
2.35 V
0.1 V
0V
100 mV
0.05 V
0V
0.1 V
-100 mV
0.05 V
1.5 V
0.9 V
600 mV
1.2 V
0.9 V
1.5 V
-600 mV
1.2 V
2.4 V
1.8 V
600 mV
2.1 V
1.8 V
2.4 V
-600 mV
2.1 V
0.6 V
0V
600 mV
0.3 V
0V
0.6 V
-600 mV
0.3 V
3.75 kΩ
Y
VOD
Input
Z
100 Ω
3.75 kΩ
±
Figure 2. VOD Test Circuit
6
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• DALLAS, TEXAS 75265
0 V ≤ VTEST ≤ 2.4 V
SN65LVDS116
16-PORT LVDS REPEATER
SLLS370A – SEPTEMBER 1999 – REVISED SEPTEMBER 1999
PARAMETER MEASUREMENT INFORMATION
Y
49.9 Ω ± 1% (2 Places)
Input
Input
VI
1.4 V
VI
1V
Z
50 pF
VOC(PP)
VOC
VOC(SS)
VO
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
Pulsewidth = 500 ±10 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. The measurement of VOC(PP)
is made on test equipment with a –3 dB bandwidth of at least 300 MHz.
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
A
Y
B
Z
Input
1.4 V
1.2 V
1V
VIB
Input
VIA
tPLH
VOD
tPHL
100 Ω ± 1 %
VOD(H)
Output
CL = 10 pF
(2 Places)
100%
80%
0V
VOD(L)
20%
0%
tf
tr
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
Pulsewidth = 10 ±0.2 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
Figure 4. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SN65LVDS116
16-PORT LVDS REPEATER
SLLS370A – SEPTEMBER 1999 – REVISED SEPTEMBER 1999
PARAMETER MEASUREMENT INFORMATION
49.9 Ω ± 1% (2 Places)
Y
1 V or 1.4 V
Z
1.4 V or 1 V
+
EN
EN
S0
S1
SM
Inputs
CL = 10 pF
(2 Places)
VOY
VOZ
2V
1.4 V
0.8 V
Input
VOY
or
VOZ
1.2 V
–
tPZH
tPHZ
100%, ≅ 1.4 V
1.3 V
0%, 1.2 V
tPZL
tPLZ
100%, 1.2 V
VOZ
1.1 V
or
0%, ≅ 1 V
VOY
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
Pulsewidth = 500 ±10 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
Figure 5. Enable and Disable Time Circuit and Definitions
8
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SN65LVDS116
16-PORT LVDS REPEATER
SLLS370A – SEPTEMBER 1999 – REVISED SEPTEMBER 1999
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
SWITCHING FREQUENCY
LOW-TO-HIGH PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
180
VCC = 3.6 V
160
VCC = 3.3 V
140
VCC = 3 V
120
100
All Outputs Loaded
and Enabled
0
50
100
150
200
250
300
350
3.7
3.6
3.5
VCC = 3.3 V
3.4
VCC = 3 V
VCC = 3.6 V
3.3
3.2
3.1
–50
400
–25
0
25
50
75
100
TA – Free–Air Temperature – °C
f – Frequency – MHz
Figure 6
Figure 7
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
t PHL – High-To-Low Propagation Delay Time – ns
I CC – Supply Current – mA
200
80
3.8
t PLH – Low-To-High Propagation Delay Time – ns
220
3.7
3.6
3.5
3.4
3.3
VCC = 3.3 V
VCC = 3.6 V
VCC = 3 V
3.2
3.1
3.0
2.9
–50
–25
0
25
50
75
100
TA – Free–Air Temperature – °C
Figure 8
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SN65LVDS116
16-PORT LVDS REPEATER
SLLS370A – SEPTEMBER 1999 – REVISED SEPTEMBER 1999
TYPICAL CHARACTERISTICS
Figure 9. Typical Differential Eye Pattern at 400 Mbps
PEAK-TO-PEAK OUTPUT JITTER
vs
SIGNALING RATE
800
VID = 600 mV, VIC = 0.3 V
VID = 100 mV, VIC = 0.05 V
VID = 400 mV, VIC = 1.4 V
Peak-To-Peak Output Jitter – ps
700
600
500
400
300
200
100
VID = 600 mV, VIC = 2.1 V
VID = 100 mV, VIC = 2.35 V
0
0
50 100 150 200 250 300 350 400 450 500
Signaling Rate – Mbps
Figure 10. Typical Peak-To-Peak Output Jitter vs VID and VIC
10
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SN65LVDS116
16-PORT LVDS REPEATER
SLLS370A – SEPTEMBER 1999 – REVISED SEPTEMBER 1999
APPLICATION INFORMATION
An LVDS receiver can be used to receive various other types of logic signals. Figure 11 through Figure 19 show the
termination circuits for SSTL, HSTL, GTL, BTL, LVPECL, PECL, CMOS, and TTL.
VDD
25 Ω
50 Ω
A
50 Ω
B
1/2 VDD
0.1 µF
LVDS Receiver
Figure 11. Stub-Series Terminated (SSTL) or High-Speed Transceiver Logic (HSTL)
VDD
50 Ω
A
50 Ω
B
1.35 V < VTT < 1.65 V
0.1 µF
LVDS Receiver
Figure 12. Center-Tap Termination (CTT)
1.14 V < VTT < 1.26 V
VDD
1 kΩ
50 Ω
50 Ω
A
B
2 kΩ
0.1 µF
LVDS Receiver
Figure 13. Gunning Transceiver Logic (GTL)
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11
SN65LVDS116
16-PORT LVDS REPEATER
SLLS370A – SEPTEMBER 1999 – REVISED SEPTEMBER 1999
APPLICATION INFORMATION
Z0
Z0
A
B
1.47 V < VTT < 1.62 V
0.1 µF
LVDS Receiver
Figure 14. Backplane Transceiver Logic (BTL)
3.3 V
3.3 V
50 Ω
ECL
120 Ω
120 Ω
33 Ω
33 Ω
A
50 Ω
B
51 Ω
51 Ω
LVDS Receiver
Figure 15. Low-Voltage Positive Emitter-Coupled Logic (LVPECL)
12
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SN65LVDS116
16-PORT LVDS REPEATER
SLLS370A – SEPTEMBER 1999 – REVISED SEPTEMBER 1999
APPLICATION INFORMATION
5V
5V
50 Ω
ECL
82 Ω
82 Ω
100 Ω
100 Ω
A
50 Ω
B
33 Ω
33 Ω
LVDS Receiver
Figure 16. Positive Emitter-Coupled Logic (PECL)
3.3 V
3.3 V
7.5 kΩ
A
B
7.5 kΩ
0.1 µF
LVDS Receiver
Figure 17. 3.3-V CMOS
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13
SN65LVDS116
16-PORT LVDS REPEATER
SLLS370A – SEPTEMBER 1999 – REVISED SEPTEMBER 1999
APPLICATION INFORMATION
5V
5V
10 kΩ
560 Ω
A
B
560 Ω
3.3 kΩ
0.1 µF
LVDS Receiver
Figure 18. 5-V CMOS
5V
5V
10 kΩ
470 Ω
A
B
3.3 V
4 kΩ
0.1 µF
Figure 19. TTL
14
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LVDS Receiver
SN65LVDS116
16-PORT LVDS REPEATER
SLLS370A – SEPTEMBER 1999 – REVISED SEPTEMBER 1999
MECHANICAL DATA
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: B.
C.
D.
E.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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