ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com ..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008 14/12-Bit, 250/210 MSPS ADCs With DDR LVDS and Parallel CMOS Outputs FEATURES 1 • • • • • • • • • • • Maximum Sample Rate: 250 MSPS 14-Bit Resolution – ADS614X 12-Bit Resolution – ADS612X 687 mW Total Power Dissipation at 250 MSPS Double Data Rate (DDR) LVDS and Parallel CMOS Output Options Programmable Fine Gain up to 6dB for SNR/SFDR Trade-Off DC Offset Correction Supports Input Clock Amplitude Down to 400 mVPP Differential Internal and External Reference Support 48-QFN Package (7mm × 7mm) Pin Compatible with ADS5547 Family APPLICATIONS • • • • • • • • • Multicarrier, Wide Band-Width Communications Wireless Multi-carrier Communications Infrastructure Software Defined Radio Power Amplifier Linearization 802.16d/e Test and Measurement Instrumentation High Definition Video Medical Imaging Radar Systems DESCRIPTION ADS614X (ADS612X) is a family of 14-bit (12-bit) A/D converters with sampling rates up to 250 MSPS. It combines high dynamic performance and low power consumption in a compact 48 QFN package. This makes it well-suited for multicarrier, wide band-width communications applications. ADS614X/2X has fine gain options that can be used to improve SFDR performance at lower full-scale input ranges. It includes a dc offset correction loop that can be used to cancel the ADC offset. Both DDR LVDS (Double Data Rate) and parallel CMOS digital output interfaces are available. At lower sampling rates, the ADC automatically operates at scaled down power with no loss in performance. It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C). 250 MSPS 210 MSPS ADS614X 14-Bit Family ADS6149 ADS6148 ADS612X 12-Bit Family ADS6129 ADS6128 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ..................................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DRGND DRVDD AGND AVDD ADS614X BLOCK DIAGRAM DDR LVDS Interface CLKP CLKOUTP CLOCKGEN CLKM CLKOUTM D0_D1_P D0_D1_M D2_D3_P D2_D3_M D4_D5_P D4_D5_M INP INM Sample and Hold DDR Serializer 14-Bit ADC D6_D7_P D6_D7_M D8_D9_P D8_D9_M D10_D11_P D10_D11_M VCM Control Interface Reference D12_D13_P D12_D13_M OVR_SDOUT DFS MODE SDATA SEN SCLK RESET ADS6149/48 B0095-06 2 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com ..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008 DRGND DRVDD AGND AVDD ADS612X BLOCK DIAGRAM DDR LVDS Interface CLKP CLKOUTP CLOCKGEN CLKM CLKOUTM D0_D1_P D0_D1_M D2_D3_P D2_D3_M D4_D5_P D4_D5_M INP INM Sample and Hold DDR Serializer 12-Bit ADC D6_D7_P D6_D7_M D8_D9_P D8_D9_M D10_D11_P D10_D11_M VCM Control Interface Reference OVR_SDOUT DFS MODE SDATA SEN SCLK RESET ADS6129/28 B0095-07 Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 3 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ..................................................................................................................................................... www.ti.com PACKAGE/ORDERING INFORMATION (1) (2) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE LEAD/BALL FINISH PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ADS614x ADS6149 AZ6149 QFN-48 RGZ –40°C to 85°C Cu NiPdAu ADS6148 AZ6148 ADS6149IRGZR ADS6149IRGZT ADS6148IRGZR Tape and reel ADS6148IRGZT ADS612x ADS6129 AZ6129 QFN-48 RGZ –40°C to 85°C ADS6128 (1) (2) Cu NiPdAu AZ6128 ADS6129IRGZR ADS6129IRGZT ADS6128IRGZR Tape and reel ADS6128IRGZT For thermal pad size on the package, see the mechanical drawings at the end of this data sheet. θJA = 25.41° C/W (0LFM air flow), θJC = 16.5°C/W when used with 2oz. copper trace and pad soldered directly to a JEDEC standard four layer 3 in x 3 in (7.62 cm x 7.62 cm) PCB. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) VALUE UNIT Supply voltage range, AVDD –0.3 V to 3.9 V Supply voltage range, DRVDD –0.3 V to 2.2 V –0.3 to 0.3 V Voltage between AVDD to DRVDD (when AVDD leads DRVDD) 0 to 3.3 V Voltage between DRVDD to AVDD (when DRVDD leads AVDD) –1.5 to 1.8 V Voltage applied to external pin, VCM (in external reference mode) –0.3 to 2.0 V –0.3V to minimum ( 3.6, AVDD + 0.3V ) V –0.3V to AVDD + 0.3V V Voltage between AGND and DRGND VI Voltage applied to analog input pins - INP, INM Voltage applied to input pins - CLKP, CLKM (2), RESET, SCLK, SDATA, SEN, DFS and MODE TA Operating free-air temperature range –40 to 85 °C TJ Operating junction temperature range 125 °C Tstg Storage temperature range –65 to 150 °C (1) (2) 4 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. When AVDD is turned off, it is recommended to switch off the input clock (or ensure the voltage on CLKP, CLKM is < |0.3V|. This prevents the ESD protection diodes at the clock input pins from turning on. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com ..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN TYP MAX UNIT 3 3.3 3.6 V 1.7 1.8 1.9 V SUPPLIES AVDD Analog supply voltage DRVDD Digital supply voltage ANALOG INPUTS Differential input voltage range 2 Input common-mode voltage Vpp 1.5 ±0.1 Voltage applied on CM in external reference mode V 1.5 ± 0.05 V Maximum analog input frequency with 2 VPP input amplitude (1) 500 MHz Maximum analog input frequency with 1 VPP input amplitude (1) 800 MHz CLOCK INPUT Input clock sample rate ADS6149 / ADS6129 1 250 ADS6148 / ADS6128 1 210 Sine wave, ac-coupled Input Clock amplitude differential (VCLKP–VCLKM) 0.3 1.5 LVPECL, ac-coupled 1.6 LVDS, ac-coupled 0.7 LVCMOS, single-ended, ac-coupled Vpp 3.3 Input clock duty cycle 40% MSPS 50% V 60% DIGITAL OUTPUTS CL Maximum external load capacitance from each output pin to DRGND RL Differential load resistance between the LVDS output pairs (LVDS mode) TA Operating free-air temperature (1) 5 pF Ω 100 –40 85 °C See the Theory of Operation in the application section. Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 5 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ..................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS – ADS614X and ADS612X Typical values are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode unless otherwise noted. Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3 V, DRVDD = 1.8 V PARAMETER ADS6149/ADS6129 250 MSPS MIN TYP MAX ADS6148/ADS6128 210 MSPS MIN TYP UNIT MAX ANALOG INPUT Differential input voltage range Differential input resistance (at dc), See Figure 97 2 2 VPP >1 >1 MΩ Differential input capacitance, See Figure 98 3.5 3.5 pF Analog Input Bandwidth 700 700 MHz 2 2 VCM Common mode output voltage 1.5 1.5 V VCM output current capability ±4 ±4 mA Analog Input common mode current (per input pin) µA/MSPS DC ACCURACY Offset error –15 Temperature coefficient of offset error Variation of offset error with supply EGREF Gain error due to internal reference inaccuracy alone EGCHAN Gain error of channel alone Temperature coefficient of EGCHAN –1.25 ±2 15 –15 ±2 0.005 0.005 0.3 0.3 ±0.2 1.25 –1.25 ±0.2 15 mV mV/°C mV/V 1.25 %FS 0.2 0.2 %FS .001 .001 Δ%/°C POWER SUPPLY IAVDD IDRVDD Analog supply current 170 155 mA Output buffer supply current, LVDS interface with 100 Ω external termination 70 65 mA Output buffer supply current, CMOS interface Fin = 3 MHz (1), 10-pF external load capacitance 56 48 mA Analog power 561 630 510 570 mW Digital power LVDS interface 126 160 118 153 mW Digital power CMOS interface, Fin = 3 MHz (2), 10-pF external load capacitance 101 Global power down 20 Standby (1) (2) 6 87 50 120 20 120 mW 50 mW mW In CMOS mode, the DRVDD current scales with the sampling frequency, the load capacitance on output pins, input frequency and the supply voltage (see Figure 91 and CMOS interface power dissipation in application section). The maximum DRVDD current with CMOS interface depends on the actual load capacitance on the digital output lines. Note that the maximum recommended load capacitance on each digital output line is 10 pF. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com ..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ELECTRICAL CHARACTERISTICS – ADS6149 and ADS6148 Typical values are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode unless otherwise noted. Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3 V, DRVDD = 1.8 V ADS6149 250 MSPS PARAMETER MIN SNR Signal to noise ratio, LVDS MIN 73.4 73.4 72.7 72.7 Fin = 100 MHz 72.3 72.3 69 71.3 69.7 69 Fin = 20 MHz 73.2 73.3 Fin = 80 MHz 72.4 72.4 Fin = 100 MHz 71.9 68 Fin = 300 MHz 71.8 70.6 68.7 68 Fin = 170 MHz 11 11.4 DNL Differential non-linearity –0.95 ±0.4 INL Integrated non-linearity –5 ±2 dBFS 71.2 69 Fin = 170 MHz UNIT TYP MAX Fin = 80 MHz Fin = 300 MHz ENOB Effective number of bits TYP MAX Fin = 20 MHz Fin = 170 MHz SINAD Signal to noise and distortion ratio, LVDS ADS6148 210 MSPS dBFS 70.9 68.2 11.1 11.5 LSB 2 –0.95 ±0.4 2 LSB 5 –5 ±2 5 LSB ELECTRICAL CHARACTERISTICS – ADS6129 and ADS6128 Typical values are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode unless otherwise noted. Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3 V, DRVDD = 1.8 V PARAMETER ADS6129 250 MSPS MIN SNR, Signal to noise ratio, LVDS TYP 70.7 70.9 70.5 70.5 Fin = 100 MHz 70.1 70.1 67.5 69.5 67.7 67.8 67.9 Fin = 20 MHz 70.6 70.8 Fin = 80 MHz 70.4 70.4 Fin = 100 MHz 69.8 66.5 Fin = 170 MHz 66.7 67.2 11.2 DNL Differential non-linearity –0.5 ±0.2 INL Integrated non-linearity –2.5 ±1 dBFS 69.8 69.2 10.8 UNIT MAX 69.5 Fin = 300 MHz Fin = 300 MHz Copyright © 2008, Texas Instruments Incorporated MIN Fin = 80 MHz Fin = 170 MHz ENOB, Effective number of bits TYP MAX Fin = 20 MHz Fin = 170 MHz SINAD Signal to noise and distortion ratio, LVDS ADS6128 210 MSPS dBFS 69.3 67.3 10.8 11.2 LSB 1 –0.5 ±0.2 1.0 LSB 2.5 –2.5 ±1 2.5 LSB Submit Documentation Feedback Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 7 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ..................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS – ADS614x and ADS612x Typical values are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode unless otherwise noted. Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3 V, DRVDD = 1.8 V PARAMETER ADS6149/ADS6129 250 MSPS MIN SFDR Spurious Free Dynamic Range 92 92 86 82 Fin = 100 MHz 85 81 IMD 2-Tone inter-modulation distortion 74 76 89 88.5 Fin = 20 MHz 83 80 Fin = 80 MHz 82 71 79 79 71 73 73 Fin = 20 MHz 94 94 Fin = 80 MHz 90 88 Fin = 100 MHz 88 88 84 74 76 76 Fin = 20 MHz 93 92 Fin = 80 MHz 86 82 Fin = 100 MHz 85 82 81 74 dBc dBc 84 Fin = 300 MHz 74 dBc 80 Fin = 300 MHz 74 UNIT MAX 83 Fin = 10 MHz dBc 83 Fin = 300 MHz 76 76 Fin = 20 MHz 96 96 Fin = 80 MHz 94 94 Fin = 100 MHz 94 94 Fin = 170 MHz 92 92 Fin = 300 MHz 90 90 F1 = 46 MHz, F2 = 50 MHz, Each tone at –7 dBFS 94 95 F1 = 185 MHz, F2 = 190 MHz, Each tone at –7 dBFS 90 90 1 1 clock cycles 25 25 dB Input overload recovery Recovery to within 1% (of final value) for 6-dB overload with sine wave input PSRR AC power supply rejection ratio For 100 mVPP signal on AVDD supply 8 82 76 Fin = 170 MHz Worst Spur Other than second, third harmonics 74 Fin = 300 MHz Fin = 170 MHz HD3 Third Harmonic Distortion TYP Fin = 80 MHz Fin = 170 MHz HD2, Second Harmonic Distortion MIN Fin = 20 MHz Fin = 170 MHz THD Total Harmonic Distortion TYP MAX ADS6148/ADS6128 210 MSPS Submit Documentation Feedback dBc dBFS Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com ..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008 DIGITAL CHARACTERISTICS – ADS614x and ADS612x The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1. AVDD = 3.3 V, DRVDD = 1.8 V PARAMETER ADS6149/ADS6148/ ADS6129/ADS6128 TEST CONDITIONS MIN TYP UNIT MAX DIGITAL INPUTS – RESET, SCLK, SDATA, SEN (1) High-level input voltage All digital inputs support 1.8V and 3.3V CMOS logic levels Low-level input voltage High-level input current Low-level input current 1.3 V 0.4 SDATA, SCLK (2) VHIGH = 3.3V 16 SEN (3) VHIGH = 3.3V 10 SDATA, SCLK VLOW = 0V 0 SEN VLOW = 0V –20 Input capacitance V µA µA 4 pF High-level output voltage DRVDD V Low-level output voltage 0 V Output capacitance (internal to device) 2 pF DIGITAL OUTPUTS – CMOS INTERFACE (Pins D0 to D13 and OVR_SDOUT) DIGITAL OUTPUTS – LVDS INTERFACE (Pins D0_D1_P/M to D12_D13_P/M) (4) VODH, High-level output voltage (5) VODL, Low-level output voltage (5) 275 350 425 mV –425 –350 –275 mV 1 1.2 1.3 VOCM, Output common-mode voltage Capacitance inside the device, from either output to ground Output capacitance (1) (2) (3) (4) (5) 2 V pF SCLK, SDATA, SEN function as digital input pins in serial configuration mode. SDATA, SCLK have internal 200 kΩ pull-down resistor SEN has internal 100 kΩ pull-up resistor to AVDD. Since the pull-up is weak, SEN can also be driven by 1.8V or 3.3V CMOS buffers. OVR_SDOUT has CMOS output logic levels, determined by DRVDD voltage. With external 100 Ω termination Dn_Dn+1_P Dn_Dn+1_P Logic 1 Logic 0 VODL = –350 mV (1) VODH = 350 mV (1) Dn_Dn+1_M Dn_Dn+1_M V V OCM OCM GND GND T0399-01 Figure 1. LVDS Voltage Levels Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 9 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ..................................................................................................................................................... www.ti.com TIMING REQUIREMENTS – LVDS AND CMOS MODES (1) Typical values are at 25°C, AVDD = 3.3V, DRVDD = 1.8V, sampling frequency = 250 MSPS, sine wave input clock, CLOAD = 5pF (2), RLOAD = 100Ω (3), LOW SPEED mode disabled, unless otherwise noted. Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3V, DRVDD = 1.7V to 1.9V. PARAMETER ta Aperture delay tj Aperture jitter TEST CONDITIONS The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs TYP MAX 0.7 1.2 1.7 170 Wake-up time ADC Latency (4) DDR LVDS MODE MIN UNIT ns fs rms Time to valid data after coming out of STANDBY mode 0.3 1 Time to valid data after coming out of PDN GLOBAL mode 25 100 Time to valid data after stopping and restarting the input clock 10 clock cycles Default, after reset 18 clock cycles 0.8 1.2 ns 0.25 0.6 ns µs (5) (6) tsu Data setup time Data valid th Data hold time Zero-crossing of CLKOUT to data becoming invalid (6) tPDI Clock propagation delay Input clock rising edge cross-over to output clock rising edge cross-over 100 MSPS ≤ Sampling frequency ≤ 250 MSPS tdelay to zero-crossing of CLKOUTP 0.2 × ts + tdelay 5.0 6.2 ns 7.5 ns LVDS bit clock duty cycle Duty cycle of differential clock, (CLKOUTP–CLKOUTM) 100 MSPS ≤ Sampling frequency ≤ 250 MSPS tRISE, tFALL Data rise time, Data fall time Rise time measured from –100 mV to 100 mV Fall time measured from 100 mV to –100 mV 1 MSPS ≤ Sampling frequency ≤ 250 MSPS 0.08 0.14 0.2 ns tCLKRISE, tCLKFALL Output clock rise time, Output clock fall time Rise time measured from –100 mV to 100 mV Fall time measured from 100 mV to –100 mV 1 MSPS ≤ Sampling frequency ≤ 250 MSPS 0.08 0.14 0.2 ns tOE Output enable (OE) to data delay Time to valid data after OE becomes active 52% 40 ns PARALLEL CMOS MODE (7) tSTART Input clock to data delay Input clock rising edge cross-over to start of data valid (8) tDV Data valid time Time interval of valid data (8) 0.7 tPDI Clock propagation delay Input clock rising edge cross-over to output clock rising edge cross-over 100 MSPS ≤ Sampling frequency ≤ 150 MSPS 0.78 × ts + tdelay tdelay 3.2 5 1.5 6.5 ns ns 8 ns Output clock duty cycle Duty cycle of differential clock, (CLKOUT) 100 MSPS ≤ Sampling frequency ≤ 150 MSPS tRISE, tFALL Data rise time, Data fall time Rise time measured from 20% to 80% of DRVDD, Fall time measured from 80% to 20% of DRVDD, 1 MSPS ≤ Sampling frequency ≤ 250 MSPS 0.7 1.2 2 ns tCLKRISE, tCLKFALL Output clock rise time, Output clock fall time Rise time measured from 20% to 80% of DRVDD, Fall time measured from 80% to 20% of DRVDD, 1 MSPS ≤ Sampling frequency ≤ 150 MSPS 0.5 1 1.5 ns tOE Output enable (OE) to data delay Time to valid data after OE becomes active (1) (2) (3) (4) (5) (6) (7) (8) 10 50% 20 ns Timing parameters are specified by design and characterization and not tested in production. CLOAD is the effective external single-ended load capacitance between each output pin and ground RLOAD is the differential load resistance between the LVDS output pair. At higher frequencies, tPDI is greater than one clock period and overall latency = ADC latency + 1. Measurements are done with a transmission line of 100Ω characteristic impedance between the device and the load. Setup and hold time specifications take into account the effect of jitter on the output data and clock. Data valid refers to LOGIC HIGH of +100mV and LOGIC LOW of –100mV. For Fs> 150 MSPS, it is recommended to use external clock for data capture and NOT the device output clock signal (CLKOUT). Data valid refers to LOGIC HIGH of 1.26V and LOGIC LOW of 0.54V. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com ..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008 LVDS Timings at Lower Sampling Frequencies SAMPLING FREQUENCY, MSPS SETUP TIME, ns HOLD TIME, ns MIN TYP MIN TYP 210 1.0 1.4 MAX 0.4 0.8 190 1.1 1.5 0.5 0.9 170 1.3 1.7 0.7 1.1 150 1.6 1.9 0.9 1.2 125 1.9 2.2 1.1 1.4 <100 Enable LOW SPEED mode 2.5 MAX 2.0 tPDI, ns 1 ≤ Fs ≤ 100, Enable LOW SPEED mode MIN (1) TYP MAX 8.2 (1) Ts = 1/Sampling frequency CMOS Timings at Lower Sampling Frequencies Timings specified with respect to input clock SAMPLING FREQUENCY, MSPS tSTART, ns MIN TYP DATA VALID TIME, ns MAX MIN TYP 210 1.7 1.6 2.4 190 0.4 2.2 3.0 170 5.1 2.4 3.6 150 4.8 3.0 4.3 MAX Timings specified with respect to CLKOUT SAMPLING FREQUENCY, MSPS SETUP TIME, ns MIN TYP 150 2.0 125 2.9 <100 Enable LOW SPEED mode 5.0 HOLD TIME, ns MAX MIN TYP 3.2 1.5 2.2 4 2.2 2.7 MAX 3.8 tPDI, ns 1 ≤ Fs ≤ 100 Enable LOW SPEED mode MIN (1) TYP MAX 14 (1) Ts = 1/Sampling frequency Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 11 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ..................................................................................................................................................... www.ti.com N+4 N+3 N+2 N+1 Sample N N+20 N+19 N+18 Input Signal ta Input Clock CLKP CLKM CLKOUTM CLKOUTP tsu Output Data DXP, DXM E E – Even Bits D0,D2,D4,... O – Odd Bits D1,D3,D5, ... O E O N–18 E O N–17 E O N–16 E tPDI th 18 Clock Cycles* DDR LVDS O E O E O E N–15 O N E E O O N+2 N+1 tPDI CLKOUT tsu Parallel CMOS 18 Clock Cycles* Output Data N–18 N–17 N–16 N–15 th N–14 N–1 N N+1 N+2 Then, overall latency = ADC latency + 1. ADC latency is 14 clock cycles in low-latency mode. T0105-09 Figure 2. Latency Diagram 12 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com ..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008 Input Clock CLKP CLKM tPDI Output Clock CLKOUTP CLKOUTM tsu th tsu Output Data Pair (1) (2) Dn Dn_Dn+1_P, Dn_Dn+1_M th Dn (1) Dn+1 (2) – Bits D0, D2, D4,... Dn+1 – Bits D1, D3, D5, ... T0106-07 Figure 3. LVDS Mode Timing Input Clock CLKM CLKP tPDI Output Clock CLKOUT th tsu Output Data Input Clock Dn Dn* CLKM CLKP tSTART tDV Output Data Dn Dn* *Dn – Bits D0, D1, D2, ... T0107-05 Figure 4. CMOS Mode Timing Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 13 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ..................................................................................................................................................... www.ti.com DEVICE CONFIGURATION ADS614X/2X can be configured independently using either parallel interface control or serial interface programming. PARALLEL CONFIGURATION ONLY To put the device in parallel configuration mode, keep RESET tied to HIGH (DRVDD). Now, pins DFS, MODE, SEN and SDATA can be used to directly control certain modes of the ADC. The device can be easily configured by connecting the parallel pins to the correct voltage levels (as described in Table 3 to Table 6. There is no need to apply reset. In this mode, SEN and SDATA function as parallel interface control pins. Frequently used functions can be controlled in this mode – standby, selection between LVDS/CMOS output format, internal/external reference, two’s complement/straight binary output format and position of the output clock edge. Table 1 briefly describes the modes controlled by the parallel pins. Table 1. Parallel Pin Functions PIN TYPE OF CONTROL CONTROLS MODES DFS Analog Data format and LVDS/CMOS output interface. MODE (1) Analog Internal or external reference, low speed mode enable SEN Analog CLKOUT edge programmability. SDATA Digital Global power-down (ADC, internal references and output buffers are powered down) (1) In the next generation pin-compatible ADC family, MODE will be converted to a digital control pin for certain reserved functions. So, the selection of internal or external reference and low speed functions will not be supported using MODE. In the system board using ADS61x9/x8, the MODE pin can be routed to a digital controller. This will avoid board modification while migrating to the next generation ADC. SERIAL INTERFACE CONFIGURATION ONLY To exercise this mode, first the serial registers have to be reset to their default values and RESET pin has to be kept LOW. SEN, SDATA and SCLK function as serial interface pins in this mode and can be used to access the internal registers of the ADC. The registers can be reset either by applying a pulse on RESET pin or by setting HIGH the <RESET> bit (D7 in register 0x00). The serial interface section describes the register programming and register reset in more detail. Since the parallel pins DFS and MODE are not to be used in this mode, they have to be tied to ground. 14 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com ..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008 CONFIGURATION USING BOTH THE SERIAL INTERFACE AND PARALLEL CONTROLS For increased flexibility, an additional configuration mode is supported wherein a combination of serial interface registers and parallel pin controls (DFS, MODE) can be used to configure the device. To exercise this mode, the serial registers have to be reset to their default values and RESET pin has to be kept LOW. SEN, SDATA and SCLK function as serial interface pins in this mode and can be used to access the internal registers of ADC. The registers can be reset either by applying a pulse on RESET pin or by setting HIGH the <RESET> bit (D7 in register 0x00). The serial interface section describes the register programming and register reset in more detail. The parallel interface control pins DFS and MODE can be used and their function is determined by the appropriate voltage levels as described in Table 3. The voltage levels can be easily derived, by using a resistor string as illustrated with an example as shown in Figure 5. Since some functions can be controlled using both the parallel pins and serial registers, the priority between the two is determined by a Priority Table as shown in Table 2. Table 2. Priority Between Parallel Pins and Serial Registers FUNCTION PRIORITY Internal/External reference MODE pin controls this selection ONLY if the register bits <REF> = 00, otherwise <REF> controls the selection Data format selection LVDS or CMOS interface selection DFS pin controls this selection ONLY if the register bits <DATA FORMAT> = 00, otherwise <DATA FORMAT> controls the selection DFS pin controls this selection ONLY if the register bits <LVDS CMOS> = 00, otherwise <LVDS CMOS> controls the selection DESCRIPTION OF PARALLEL PINS Table 3. SDATA – DIGITAL CONTROL PIN SDATA 0 AVDD DESCRIPTION Normal operation (default) Global power-down. ADC, internal references and the output buffers are powered down. Table 4. SEN – ANALOG CONTROL PIN (1) SEN 0 (3/8)AVDD LVDS: Setup time decreases by (4xTs/26), Hold time increases by (4xTs/26) CMOS: Setup time increases by (9xTs/26), Hold time reduces by (9xTs/26) (5/8)AVDD LVDS: Setup time increases by (4xTs/26), Hold time reduces by (4xTs/26) CMOS: Setup time increases by (3xTs/26), Hold time reduces by (3xTs/26) AVDD (1) DESCRIPTION – Output Clock Edge Programmability LVDS: Data and output clock transitions are aligned CMOS: Setup time increases by (6xTs/26), Hold time reduces by (6xTs/26) Default output clock position (Setup/hold timings of output data with respect to this clock position is specified in the timing characteristics table). Ts = 1/Sampling frequency Table 5. DFS – ANALOG CONTROL PIN DFS 0 DESCRIPTION 2s complement data and DDR LVDS output (3/8)AVDD 2s complement data and parallel CMOS output (5/8)AVDD Offset binary data and parallel CMOS output AVDD Offset binary data and DDR LVDS output Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 15 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ..................................................................................................................................................... www.ti.com Table 6. MODE – ANALOG CONTROL PIN MODE DESCRIPTION 0 Internal reference, LOW SPEED mode disabled (for Fs > 100 MSPS) (3/8)AVDD External reference, LOW SPEED mode disabled (for Fs > 100 MSPS) (5/8)AVDD External reference, LOW SPEED mode enabled (for Fs ≤ 100 MSPS) AVDD Internal reference, LOW SPEED mode enabled (for Fs ≤ 100 MSPS) AVDD (5/8) AVDD 3R (5/8) AVDD GND AVDD 2R (3/8) AVDD (3/8) AVDD 3R To Parallel Pin GND S0321-01 Figure 5. Simple Scheme to Configure Parallel Pins SEN and SCLK SERIAL INTERFACE The ADC has a set of internal registers, which can be accessed by the serial interface formed by pins SEN (Serial interface Enable), SCLK (Serial Interface Clock) and SDATA (Serial Interface Data). Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edge of SCLK when SEN is active (low). The serial data is loaded into the register at every 16th SCLK falling edge when SEN is low. In case the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be loaded in multiple of 16-bit words within a single active SEN pulse. The first 8 bits form the register address and the remaining 8 bits are the register data. The interface can work with SCLK frequency from 20 MHz down to low speeds (few Hertz) and also with non-50% SCLK duty cycle. Register Initialization After power-up, the internal registers MUST be initialized to their default values. This can be done in one of two ways: 1. Either through hardware reset by applying a high-going pulse on RESET pin (of width greater than 10ns) as shown in Figure 6. OR 2. By applying software reset. Using the serial interface, set the <RESET> bit (D7 in register 0x00) to HIGH. This initializes internal registers to their default values and then self-resets the <RESET> bit to LOW. In this case the RESET pin is kept LOW. 16 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com ..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008 Register Data Register Address SDATA A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 t(SCLK) D5 D4 D3 D2 D1 D0 t(DH) t(DSU) SCLK t(SLOADH) t(SLOADS) SEN RESET T0109-01 Figure 6. Serial Interface Timing SERIAL INTERFACE TIMING CHARACTERISTICS Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3V, DRVDD = 1.8V, unless otherwise noted. PARAMETER MIN > DC TYP MAX UNIT 20 MHz fSCLK SCLK frequency (= 1/ tSCLK) tSLOADS SEN to SCLK setup time 25 ns tSLOADH SCLK to SEN hold time 25 ns tDS SDATA setup time 25 ns tDH SDATA hold time 25 ns SERIAL REGISTER READOUT The device includes an option where the contents of the internal registers can be read back. This may be useful as a diagnostic check to verify the serial interface communication between the external controller and the ADC. a. First, set register bit <SERIAL READOUT> = 1. This also disables any further writes into the registers (EXCEPT register bit <SERIAL READOUT> itself). b. Initiate a serial interface cycle specifying the address of the register (A7-A0) whose content has to be read. c. The device outputs the contents (D7-D0) of the selected register on OVR_SDOUT pin. d. The external controller can latch the contents at the falling edge of SCLK. e. To enable register writes, reset register bit <SERIAL READOUT> = 0. Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 17 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ..................................................................................................................................................... www.ti.com A) Enable serial readout (<SERIAL READOUT> = 1) Register Data (D7:D0) = 0x01 Register Address (A7:A0) = 0x00 SDATA 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 SCLK SEN Pin OVR_SDOUT functions as OVR (<SERIAL READOUT> = 0) OVR_SDOUT B) Read contents of register 0x3F. This register has been initialized with 0x04 (device is put in global power down mode) Register Data (D7:D0) = XX (Don't Care) Register Address (A7:A0) = 0x3F SDATA A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 1 0 0 SCLK SEN OVR_SDOUT Pin OVR_SDOUT functions as serial readout (<SERIAL READOUT> = 1) T0386-01 Figure 7. Serial Readout 18 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com ..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008 RESET TIMING Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C, unless otherwise noted. PARAMETER t1 t2 Power-on delay Reset pulse width t3 TEST CONDITIONS MIN TYP Delay from power-up of AVDD and DRVDD to RESET pulse active MAX UNIT 1 ms 10 Pulse width of active RESET signal that will reset the serial registers ns µs 1 Delay from RESET disable to SEN active 100 ns Power Supply AVDD, DRVDD t1 RESET t2 t3 SEN T0108-01 Figure 8. Reset Timing Diagram SERIAL REGISTER MAP Table 7. Summary of Functions Supported by Serial Interface (1) REGISTER ADDRESS REGISTER FUNCTIONS A7–A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0 00 <RESET> Software Reset 0 0 0 0 0 0 <SERIAL READOUT> 20 0 0 0 0 0 <ENABLE LOW SPEED MODE> 0 0 3F 0 0 0 <PDN GLOBAL> <STANDBY> <PDN OBUF> 0 0 0 0 0 0 0 REF> Internal or external reference <LVDS CMOS> Output interface 41 <CLKOUT POSN> Output clock position control 44 50 0 0 52 0 0 53 0 ENABLE OFFSET CORR> 51 0 0 0 <DATA FORMAT> 2s complement or offset binary 0 <CUSTOM PATTERN LOW> 55 (1) 0 CUSTOM PATTERN HIGH> 0 0 0 <FINE GAIN > 62 0 0 63 0 0 0 0 0 <OFFSET CORR TIME CONSTANT> Offset correction time constant 0 0 0 TEST PATTERNS> PROGRAM OFFSET PEDESTAL > Multiple functions in a register can be programmed in a single write operation. Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 19 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ..................................................................................................................................................... www.ti.com DESCRIPTION OF SERIAL REGISTERS A) A7–A0 IN HEX D7 <RESET> Software Reset 00 D7 D6 D5 0 D4 0 D3 0 0 D2 0 D1 D0 0 <SERIA L READO UT> <RESET> 1 Software reset applied – resets all internal registers and self-clears to 0. D0 <SERIAL READOUT> 0 Serial readout disabled 1 Serial readout enabled, Pin OVR_SDOUT functions as serial data readout. A) A7–A0 IN HEX D7 20 D2 D6 0 D5 0 D4 0 0 D3 D2 D1 D0 0 <ENABLE LOW SPEED MODE> 0 0 D3 D2 D1 D0 0 <PDN GLOBAL> <STANDBY> <PDN OBUF> <ENABLE LOW SPEED MODE> 0 LOW SPEED mode disabled. Use for sampling frequency > 100 MSPS 1 Enable LOW SPEED mode for sampling frequencies ≤ 100 MSPS. B) A7–A0 IN HEX 3F D0 D7 D6 0 D5 D4 <REF> 0 <PDN OBUF> Power down output buffer 0 Output buffer enabled 1 Output buffer powered down D1 <STANDBY> 0 Normal operation 1 ADC alone powered down. Internal references, output buffers are active. Quick wake-up time D2 <PDN GLOBAL> 0 Normal operation 1 Total power down – ADC, internal references and output buffers are powered down. Slow wake-up time. D6,D5 <REF> Internal or external reference selection 00 MODE pin controls reference selection 01 Internal reference enabled 11 External reference enabled C) A7–A0 IN HEX 41 D7,D6 20 D7 D6 <LVDS CMOS> D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 <LVDS CMOS> 00 DFS pin controls LVDS or CMOS interface selection 10 DDR LVDS interface 11 Parallel CMOS interface Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com ..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008 D) A7–A0 IN HEX D7 D6 44 D5 D4 D3 D2 <CLKOUT POSN> Output clock position control D1 D0 0 0 LVDS Interface D7-D5 <CLKOUT POSN> Output clock rising edge position 000 Default output clock position (refer to timing specification table) 100 Default output clock position (refer to timing specification table) 101 Rising edge shifted by + (4/26)Ts 110 Rising edge aligned with data transition 111 Rising edge shifted by - (4/26)Ts D4-D2 <CLKOUT POSN> Output clock falling edge position 000 Default output clock position (refer to timing specification table) 100 Default output clock position (refer to timing specification table) 101 Falling edge shifted by + (4/26)Ts 110 Falling edge aligned with data transition 111 Falling edge shifted by - (4/26)Ts CMOS Interface D7-D5 <CLKOUT POSN> Output clock rising edge position 000 Default output clock position (refer to timing specification table) 100 Default output clock position (refer to timing specification table) 101 Rising edge shifted by + (4/26)Ts 110 Rising edge shifted by + (6/26)Ts 111 Rising edge aligned with data transition D4-D2 <CLKOUT POSN> Output clock falling edge position 000 Default output clock position (refer to timing specification table) 100 Default output clock position (refer to timing specification table) 101 Falling edge shifted by + (4/26)Ts 110 Falling edge shifted by + (6/26)Ts 111 Falling edge aligned with data transition Ts = 1/Sampling Frequency E) A7–A0 IN HEX D7 D6 D5 D4 D3 50 0 0 0 0 0 D2,D1 D2 D1 <DATA FORMAT> 2s complement or offset binary D0 0 <DATA FORMAT> 00 DFS pin controls data format selection 10 2's complement 11 Offset binary F) A7–A0 IN HEX D7 D6 51 D5 D4 D3 D2 D1 D0 <Custom Pattern> 52 0 Copyright © 2008, Texas Instruments Incorporated 0 <Custom Pattern> Submit Documentation Feedback Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 21 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ..................................................................................................................................................... www.ti.com D7–D0 <CUSTOM LOW> 8 lower bits of custom pattern available at the output instead of ADC data. D5–D0 <CUSTOM HIGH> 6 upper bits of custom pattern available at the output instead of ADC data G) A7–A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0 53 0 <ENABLE OFFSET CORR> Offset correction enable 0 0 0 0 0 0 D6 <ENABLE OFFSET CORR> 0 Offset correction disabled 1 Offset correction enabled H) A7–A0 IN HEX D7 55 D3–D0 D6 D5 <FINE GAIN> D4 D3 D2 D1 D0 <OFFSET CORR TC> Offset correction time constant <OFFSET CORR TC> Time constant of correction loop in number of clock cycles. See "Offset Correction" in application section. 0000 256 k 0001 512 k 0010 1M 0011 2M 0100 4M 0101 8M 0110 16 M 0111 32 M 1000 64 M 1001 128 M 1010 256 M 1011 512 M 1100 to 1111 RESERVED D7–D4 22 <FINE GAIN> Gain programmability in 0.5 dB steps 0000 0 dB gain, default after reset 0001 0.5 dB gain 0010 1.0 dB gain 0011 1.5 dB gain 0100 2.0 dB gain 0101 2.5 dB gain 0110 3.0 dB gain 0111 3.5 dB gain 1000 4.0 dB gain 1001 4.5 dB gain 1010 5.0 dB gain 1011 5.5 dB gain 1100 6.0 dB gain Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com ..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008 I) D2–D0 A7–A0 IN HEX D7 D6 D5 D4 D3 62 0 0 0 0 0 D2 D1 D0 <TEST PATTERNS> <TEST PATTERNS> Test Patterns to verify data capture 000 Normal operation 001 Outputs all zeros 010 Outputs all ones 011 Outputs toggle pattern ADS6149/8: Output data <D13:D0> alternates between 10101010101010 and 01010101010101 every clock cycle. ADS6129/8: Output data <D11:D0> alternates between 101010101010 and 010101010101 every clock cycle. 100 Outputs digital ramp ADS6149/8: Output data increments by one LSB (14-bit) every clock cycle from code 0 to code 16383 ADS6129/8: Output data increments by one LSB (124-bit) every 4th clock cycle from code 0 to code 4095 101 Outputs custom pattern as specified in registers 0x51 and 0x52. 110 Unused 111 Unused J) A7–A0 IN HEX D7 63 D5–D0 D6 D5 D4 D3 D2 D1 D0 <OFFSET PEDESTAL> <OFFSET PEDESTAL> When the offset correction is enabled, the final converged value after the offset is corrected will be the ADC mid-code value. A pedestal can be added to the final converged value by programming these bits. For example, See "Offset Correction" in application section. 011111 Mid-code + 31 LSB 011110 Mid-code + 30 LSB 011101 Mid-code + 29 LSB .... 000000 Mid-code 111111 Mid-code - 1 LSB 111110 Mid-code - 2 LSB .... 100000 Mid-code - 32 LSB Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 23 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ..................................................................................................................................................... www.ti.com D12_D13_M D10_D11_P D10_D11_M D8_D9_P D8_D9_M D6_D7_P D6_D7_M D4_D5_P D4_D5_M D2_D3_P D2_D3_M 47 45 44 43 42 41 40 39 38 37 1 46 DRGND 48 D12_D13_P DEVICE INFORMATION Pad is connected to DRGND 36 DRGND 35 DRVDD DRVDD 2 OVR_SDOUT 3 34 D0_D1_P CLKOUTM 4 33 D0_D1_M CLKOUTP 5 32 NC DFS 6 31 NC Thermal Pad 22 23 24 AVDD MODE AVDD 21 NC AGND 20 AVDD 25 AVDD 26 12 18 11 19 CLKM AGND AVDD SEN AGND 27 17 10 AGND CLKP 16 SDATA INM SCLK 28 14 29 9 15 AVDD AGND INP RESET AGND 30 8 13 7 VCM OE P0023-12 D10_D11_M D8_D9_P D8_D9_M D6_D7_P D6_D7_M D4_D5_P D4_D5_M D2_D3_P D2_D3_M D0_D1_P D0_D1_M 47 45 44 43 42 41 40 39 38 37 1 46 DRGND 48 D10_D11_P Figure 9. PIN CONFIGURATION (LVDS MODE) — ADS6149/48 Pad is connected to DRGND 36 DRGND 35 DRVDD DRVDD 2 OVR_SDOUT 3 34 NC CLKOUTM 4 33 NC CLKOUTP 5 32 NC DFS 6 31 NC Thermal Pad OE 7 30 RESET 22 23 24 AVDD AVDD 21 NC MODE 20 AVDD AGND 18 AGND 19 AVDD 25 AVDD 26 12 AGND 11 17 CLKM AGND SEN 16 27 INM 10 14 CLKP 15 SDATA INP SCLK 28 AGND 29 9 13 8 VCM AVDD AGND P0023-13 Figure 10. PIN CONFIGURATION (LVDS MODE) — ADS6129/28 24 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com ..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008 Table 8. PIN ASSIGNMENTS (LVDS MODE) — ADS6149/48 and ADS6129/28 PIN NAME NO. I/O NO. of PINS DESCRIPTION AVDD 8, 18, 20, 22, 24, 26 I 6 3.3-V Analog power supply AGND 9, 12, 14, 17, 19, 25 I 6 Analog ground CLKP, CLKM 10, 11 I 2 Differential clock input INP, INM 15, 16 I 2 Differential analog input 13 IO 1 Internal reference mode – Common-mode voltage output. VCM External reference mode – Reference input. The voltage forced on this pin sets the internal references Serial interface RESET input. RESET 30 I 1 SCLK 29 I 1 When using the serial interface mode, the user MUST initialize internal registers through hardware RESET by applying a high-going pulse on this pin or by using software reset option. Refer to SERIAL INTERFACE section. In parallel interface mode, the user has to tie RESET pin permanently HIGH. (SDATA and SEN are used as parallel pin controls in this mode) The pin has an internal 100 kΩ pull-down resistor. Serial interface clock input. The pin has an internal 100 kΩ pull-down resistor. This pin functions as serial interface data input when RESET is LOW. It functions as power down control pin when RESET is tied high. SDATA 28 I 1 See Table 3 for detailed information. The pin has an internal 100 kΩ pull-down resistor. This pin functions as serial interface enable input when RESET is low. It functions as output clock edge control when RESET is tied high. See Table 4 for detailed information. The pin has an internal 100 kΩ pull-up resistor to AVDD. SEN 27 I 1 OE 7 I 1 Output buffer enable input, active high. The pin has an internal 100 kΩ pull-up resistor to AVDD. DFS 6 I 1 Data Format Select input. This pin sets the DATA FORMAT (2s complement or Offset binary) and the LVDS/CMOS output interface type. See Table 5 for detailed information. 23 I 1 Internal or external reference selection and low speed mode control. control. See Table 6 for detailed information. CLKOUTP 5 O 1 Differential output clock, true CLKOUTM 4 O 1 Differential output clock, complement D0_D1_P O 1 Differential output data D0 and D1 multiplexed, true D0_D1_M O 1 Differential output data D0 and D1 multiplexed, complement D2_D3_P O 1 Differential output data D2 and D3 multiplexed, true D2_D3_M O 1 Differential output data D2 and D3 multiplexed, complement D4_D5_P O 1 Differential output data D4 and D5 multiplexed, true D4_D5_M O 1 Differential output data D4 and D5 multiplexed, complement O 1 Differential output data D6 and D7 multiplexed, true O 1 Differential output data D6 and D7 multiplexed, complement O 1 Differential output data D8 and D9 multiplexed, true D8_D9_M O 1 Differential output data D8 and D9 multiplexed, complement D10_D11_P O 1 Differential output data D10 and D11 multiplexed, true D10_D11_M O 1 Differential output data D10 and D11 multiplexed, complement D12_D13_P O 1 Differential output data D12 and D13 multiplexed, true D12_D13_M O 1 Differential output data D12 and D13 multiplexed, complement O 1 It is a CMOS output with logic levels determined by DRVDD supply. It functions as out-of-range indicator after reset and when register bit <SERIAL READOUT> = 0. It functions as serial register readout pin when register bit <SERIAL READOUT> = 1. MODE (1) D6_D7_P D6_D7_M D8_D9_P OVR_SDOUT (1) See Figure 9 and Figure 10 3 In the next generation pin-compatible ADC family, MODE will be converted to a digital control pin for certain reserved functions. So, the selection of internal or external reference and low speed functions will not be supported using MODE. In the system board using ADS61x9/x8, the MODE pin can be routed to a digital controller. This will avoid board modification while migrating to the next generation ADC. Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 25 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ..................................................................................................................................................... www.ti.com Table 8. PIN ASSIGNMENTS (LVDS MODE) — ADS6149/48 and ADS6129/28 (continued) PIN NAME NO. I/O NO. of PINS DESCRIPTION DRVDD 2, 35 I 2 1.8 V Digital and output buffer supply DRGND 1, 36, PAD I 2 Digital and output buffer ground NC 26 See Figure 9 and Figure 10 Do not connect Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 46 45 44 43 42 41 40 39 38 37 D13 1 48 DRGND 47 www.ti.com ..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008 Pad is connected to DRGND 36 DRGND 35 DRVDD DRVDD 2 OVR_SDOUT 3 34 D1 UNUSED 4 33 D0 CLKOUT 5 32 NC DFS 6 31 NC Thermal Pad 22 23 24 MODE AVDD AGND AVDD 25 21 12 NC AGND 20 AVDD AVDD SEN 26 18 27 11 19 CLKP CLKM AVDD SDATA AGND 28 10 17 9 AGND AGND 16 SCLK INM 29 15 8 INP AVDD 13 RESET 14 30 VCM 7 AGND OE P0023-14 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 46 45 44 43 42 41 40 39 38 37 D11 1 48 DRGND 47 Figure 11. PIN CONFIGURATION (CMOS MODE) – ADS6149/48 Pad is connected to DRGND 36 DRGND DRVDD 2 35 DRVDD OVR_SDOUT 3 34 NC UNUSED 4 33 NC CLKOUT 5 32 NC DFS 6 31 NC Thermal Pad 23 24 MODE AVDD AGND 22 25 AVDD 12 21 AGND NC AVDD 20 26 AVDD 11 18 CLKM 19 SEN AVDD 27 AGND 10 17 CLKP AGND SDATA 16 28 INM 9 15 AGND INP SCLK 13 RESET 29 14 30 8 VCM 7 AGND OE AVDD P0023-15 Figure 12. PIN CONFIGURATION (CMOS MODE) – ADS6129/28 Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 27 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ..................................................................................................................................................... www.ti.com PIN ASSIGNMENTS (CMOS MODE) – ADS6149/48 and ADS6129/28 PIN NAME NO. I/O NO. of PINS DESCRIPTION AVDD 8, 18, 20, 22, 24, 26 I 6 AGND 9, 12, 14, 17, 19, 25 I 6 CLKP, CLKM 10, 11 I 2 Differential clock input INP, INM 15, 16 I 2 Differential analog input 13 IO 1 Internal reference mode – Common-mode voltage output. External reference mode – Reference input. The voltage forced on this pin sets the internal references VCM 3.3-V Analog power supply Analog ground RESET 30 I 1 Serial interface RESET input. When using the serial interface mode, the user MUST initialize internal registers through hardware RESET by applying a high-going pulse on this pin or by using software reset option. Refer to SERIAL INTERFACE section. In parallel interface mode, the user has to tie RESET pin permanently HIGH. (SDATA and SEN are used as parallel pin controls in this mode) The pin has an internal 100 kΩ pull-down resistor. SCLK 29 I 1 Serial interface clock input. The pin has an internal 100 kΩ pull-down resistor. 1 This pin functions as serial interface data input when RESET is LOW. It functions as power down control pin when RESET is tied high. See Table 3 for detailed information. The pin has an internal 100 kΩ pull-down resistor. SDATA 28 I SEN 27 I 1 This pin functions as serial interface enable input when RESET is low. It functions as output clock edge control when RESET is tied high. See Table 4 for detailed information. The pin has an internal 100 kΩ pull-up resistor to AVDD. DFS 6 I 1 Data Format Select input. This pin sets the DATA FORMAT (2s complement or Offset binary) and the LVDS/CMOS output interface type. See Table 5 for detailed information. MODE 23 I 1 Internal or external reference selection control and low speed mode control. See Table 6 for detailed information. CLKOUT 5 O 1 CMOS output clock OE 7 I 1 Output buffer enable input, active high. The pin has an internal 100 kΩ pull-up resistor to AVDD. CLKOUTM 4 O 1 Differential output clock, complement See Figure 11 and Figure 12 O 14/12 3 O 1 It is a CMOS output with logic levels determined by DRVDD supply. It functions as out-of-range indicator after reset and when register bit <SERIAL READOUT> = 0. It functions as serial register readout pin when <SERIAL READOUT> = 1. DRVDD 2, 35 I 2 1.8 V Digital and output buffer supply DRGND 1, 36, PAD I 2 Digital and output buffer ground UNUSED 4 1 Unused pin in CMOS mode D0–D13 OVR_SDOUT NC 28 See Figure 11 and Figure 12 14 bit/12 bit CMOS output data Do not connect Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com ..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008 TYPICAL CHARACTERISTICS - ADS6149 All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, LVDS output interface, 32K point FFT (unless otherwise noted) FFT for 20 MHz INPUT SIGNAL FFT for 60 MHz INPUT SIGNAL 0 0 SFDR = 94.6 dBc SINAD = 73.3 dBFS SNR = 73.4 dBFS THD = 90.2 dBc −20 −40 Amplitude − dB Amplitude − dB −40 SFDR = 87.7 dBc SINAD = 72.7 dBFS SNR = 73 dBFS THD = 84 dBc −20 −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 25 50 75 100 f − Frequency − MHz 125 0 25 50 G001 Figure 13. FFT for 170 MHz INPUT SIGNAL 125 G002 FFT for 300 MHz INPUT SIGNAL 0 SFDR = 81.8 dBc SINAD = 70.8 dBFS SNR = 71.3 dBFS THD = 79.7 dBc −20 SFDR = 76.3 dBc SINAD = 68.1 dBFS SNR = 69.1 dBFS THD = 73.8 dBc −20 −40 Amplitude − dB −40 Amplitude − dB 100 Figure 14. 0 −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 25 50 75 100 f − Frequency − MHz 125 0 25 50 G003 G004 fIN1 = 185.1 MHz, –36 dBFS fIN2 = 190.1 MHz, –36 dBFS 2-Tone IMD = –105 dBFS SFDR = –103 dBFS −20 −40 Amplitude − dB −40 125 FFT for 2-TONE INPUT SIGNAL (IMD) 0 fIN1 = 185.1 MHz, –7 dBFS fIN2 = 190.1 MHz, –7 dBFS 2-Tone IMD = –90.6 dBFS SFDR = –91 dBFS −20 100 Figure 16. FFT for 2-TONE INPUT SIGNAL (IMD) 0 75 f − Frequency − MHz Figure 15. Amplitude − dB 75 f − Frequency − MHz −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 25 50 75 f − Frequency − MHz 100 125 G005 0 25 50 Figure 17. Copyright © 2008, Texas Instruments Incorporated 75 100 f − Frequency − MHz 125 G006 Figure 18. Submit Documentation Feedback Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 29 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ..................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS - ADS6149 (continued) All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, LVDS output interface, 32K point FFT (unless otherwise noted) SFDR vs INPUT FREQUENCY SNR vs INPUT FREQUENCY 100 74 95 73 LVDS 72 85 SNR − dBFS SFDR − dBc 90 80 75 70 CMOS LVDS 70 69 68 65 67 60 66 55 65 50 CMOS 64 0 50 100 150 200 250 300 350 400 450 500 fIN − Input Frequency − MHz 0 50 100 150 200 250 300 350 400 450 500 fIN − Input Frequency − MHz G007 Figure 19. Figure 20. SFDR vs GAIN SINAD vs GAIN 100 90 SINAD − dBFS 5 dB 80 75 6 dB 70 2 dB 60 0 dB 69 67 65 3 dB 63 4 dB 5 dB 61 6 dB 59 1 dB 55 1 dB 71 4 dB 85 2 dB 73 3 dB 65 57 0 dB 50 Input adjusted to get −1dBFS input 55 0 50 100 150 200 250 300 350 400 450 500 fIN − Input Frequency − MHz G009 0 50 100 150 200 250 300 350 400 450 500 fIN − Input Frequency − MHz Figure 21. 30 G008 75 Input adjusted to get −1dBFS input 95 SFDR − dBc 71 Submit Documentation Feedback G010 Figure 22. Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com ..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008 TYPICAL CHARACTERISTICS - ADS6149 (continued) All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, LVDS output interface, 32K point FFT (unless otherwise noted) PERFORMANCE vs INPUT AMPLITUDE PERFORMANCE vs INPUT COMMON-MODE VOLTAGE 110 78 75 70 74 SNR (dBFS) 60 73 50 72 −40 fIN = 60 MHz −30 −20 −10 SNR 84 73 72 80 1.35 70 1.40 1.45 1.50 1.55 1.60 Figure 24. PERFORMANCE vs AVDD SUPPLY PERFORMANCE vs DRVDD SUPPLY 78 fIN = 60.1 MHz DRVDD = 1.8 V 92 90 92 78 fIN = 60.1 MHz AVDD = 3.3 V 90 76 88 76 86 75 75 74 86 G012 77 SFDR 88 71 1.65 VCM − Common-Mode Voltage of Analog Inputs − V G011 Figure 23. 96 SFDR − dBc 74 82 0 Input Amplitude − dBFS 94 86 73 77 SFDR 84 74 SNR 82 73 SNR − dBFS −50 75 71 SFDR (dBc) SFDR − dBc 30 −60 88 SNR − dBFS 80 SFDR − dBc 76 SFDR SNR − dBFS 90 40 76 77 SNR − dBFS SFDR − dBc, dBFS 100 90 fIN = 60 MHz SFDR (dBFS) SNR 84 72 80 72 82 71 78 71 80 2.9 3.0 3.1 3.2 3.3 3.4 3.5 AVDD − Supply Voltage − V 3.6 70 3.7 76 1.6 G013 1.7 1.8 70 2.0 DRVDD − Supply Voltage − V Figure 25. Copyright © 2008, Texas Instruments Incorporated 1.9 G014 Figure 26. Submit Documentation Feedback Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 31 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ..................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS - ADS6149 (continued) All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, LVDS output interface, 32K point FFT (unless otherwise noted) PERFORMANCE vs TEMPERATURE PERFORMANCE vs INPUT CLOCK AMPLITUDE 77 94 fIN = 60 MHz 92 76 77 74 84 73 SFDR − dBc 86 SNR 82 72 80 −40 71 −20 0 20 40 60 88 75 86 74 SNR 84 73 82 72 80 71 78 0.20 80 T − Temperature − °C 76 SFDR 75 SFDR SNR − dBFS SFDR − dBc 90 88 70 0.70 1.20 1.70 2.20 Figure 28. PERFORMANCE vs INPUT CLOCK DUTY CYCLE PERFORMANCE vs VCM VOLTAGE 76 fIN = 60 MHz External Reference Mode 76 88 74 SNR 80 73 76 72 72 35 40 45 50 55 60 65 74 84 73 82 80 1.30 70 Input Clock Duty Cycle − % 86 SNR 71 30 SFDR − dBc 84 SNR − dBFS SFDR − dBc 75 75 SFDR SFDR 88 G016 90 77 fIN = 5 MHz 92 2.70 Input Clock Amplitude − VPP G015 Figure 27. 96 SNR − dBFS 90 78 fIN = 60 MHz SNR − dBFS 92 72 1.35 G017 1.40 1.45 1.50 1.55 VVCM − VCM Voltage − V Figure 29. 1.60 1.65 71 1.70 G018 Figure 30. OUTPUT NOISE HISTOGRAM 40 RMS (LSB) = 0.995 35 Occurence − % 30 25 20 15 10 5 0 8203 8204 8205 8206 8207 8208 8209 8210 8211 8212 Output Code G019 Figure 31. 32 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com ..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008 TYPICAL CHARACTERISTICS - ADS6148 All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 DBFS differential analog input, internal reference mode, 0 dB gain, LVDS output interface (unless otherwise noted) FFT for 20 MHz INPUT SIGNAL FFT for 60 MHz INPUT SIGNAL 0 0 SFDR = 90.75 dBc SINAD = 73.13 dBFS SNR = 73.25 dBFS THD = 87.76 dBc −20 −40 Amplitude − dB Amplitude − dB −40 SFDR = 92.3 dBc SINAD = 72.9 dBFS SNR = 73 dBFS THD = 89 dBc −20 −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 20 40 60 80 100 f − Frequency − MHz 0 20 40 G020 Figure 32. FFT for 170 MHz INPUT SIGNAL 100 G021 FFT for 300 MHz INPUT SIGNAL 0 SFDR = 82.44 dBc SINAD = 70.81 dBFS SNR = 71.17 dBFS THD = 80.89 dBc −20 SFDR = 76.3 dBc SINAD = 68.5 dBFS SNR = 69.3 dBFS THD = 75.1 dBc −20 −40 Amplitude − dB −40 Amplitude − dB 80 Figure 33. 0 −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 20 40 60 80 100 f − Frequency − MHz 0 20 40 60 80 100 f − Frequency − MHz G022 Figure 34. G023 Figure 35. FFT for 2-TONE INPUT SIGNAL (IMD) FFT for 2-TONE INPUT SIGNAL (IMD) 0 0 fIN1 = 185.1 MHz, –7 dBFS fIN2 = 190.1 MHz, –7 dBFS 2-Tone IMD = –90 dBFS SFDR = –88 dBFS −20 fIN1 = 185.1 MHz, –36 dBFS fIN2 = 190.1 MHz, –36 dBFS 2-Tone IMD = –101 dBFS SFDR = –97 dBFS −20 −40 Amplitude − dB −40 Amplitude − dB 60 f − Frequency − MHz −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 20 40 60 f − Frequency − MHz 80 100 0 G024 20 40 Figure 36. Copyright © 2008, Texas Instruments Incorporated 60 80 100 f − Frequency − MHz G025 Figure 37. Submit Documentation Feedback Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 33 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ..................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS - ADS6148 (continued) All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 DBFS differential analog input, internal reference mode, 0 dB gain, LVDS output interface (unless otherwise noted) SFDR vs INPUT FREQUENCY 100 74 95 73 90 72 LVDS 85 SNR − dBFS SFDR − dBc SNR vs INPUT FREQUENCY 80 CMOS 75 70 69 CMOS 68 67 60 66 55 65 64 0 50 100 150 200 250 300 350 400 450 500 fIN − Input Frequency − MHz 0 50 100 150 200 250 300 350 400 450 500 fIN − Input Frequency − MHz G026 Figure 38. Figure 39. SFDR vs GAIN SINAD vs GAIN 100 SINAD − dBFS 80 5 dB 75 6 dB 70 2 dB 65 3 dB 71 4 dB 85 2 dB 73 3 dB 90 69 67 65 4 dB 63 5 dB 61 60 6 dB 59 1 dB 55 1 dB 57 0 dB 50 Input adjusted to get −1dBFS input 0 dB 55 0 50 100 150 200 250 300 350 400 450 500 fIN − Input Frequency − MHz G028 0 50 100 150 200 250 300 350 400 450 500 fIN − Input Frequency − MHz Figure 40. 34 G027 75 Input adjusted to get −1dBFS input 95 SFDR − dBc 70 65 50 LVDS 71 Submit Documentation Feedback G029 Figure 41. Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com ..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008 TYPICAL CHARACTERISTICS - ADS6148 (continued) All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 DBFS differential analog input, internal reference mode, 0 dB gain, LVDS output interface (unless otherwise noted) PERFORMANCE vs INPUT AMPLITUDE PERFORMANCE vs INPUT COMMON-MODE VOLTAGE 110 78 80 75 SNR (dBFS) 74 60 73 50 72 94 75 SFDR 92 74 SNR 90 73 88 SFDR (dBc) fIN = 60 MHz −50 −40 −30 −20 −10 70 Input Amplitude − dBFS 77 75 88 74 SNR 86 73 84 82 3.3 3.4 3.5 AVDD − Supply Voltage − V 94 76 90 3.6 G031 78 fIN = 60.1 MHz AVDD = 3.3 V 77 SFDR 92 76 90 75 88 74 SNR 86 73 72 84 72 71 82 71 70 3.7 80 1.6 G032 1.7 1.8 1.9 70 2.0 DRVDD − Supply Voltage − V Figure 44. Copyright © 2008, Texas Instruments Incorporated 71 1.65 96 SFDR − dBc SFDR − dBc 1.60 PERFORMANCE vs DRVDD SUPPLY SFDR 3.2 1.55 PERFORMANCE vs AVDD SUPPLY 78 3.1 1.50 VCM − Common-Mode Voltage of Analog Inputs − V G030 fIN = 60.1 MHz DRVDD = 1.8 V 3.0 1.45 Figure 43. 92 80 2.9 1.40 Figure 42. 96 94 86 1.35 0 SNR − dBFS 30 −60 72 71 SNR − dBFS 40 SNR − dBFS 76 SFDR − dBc 90 70 76 77 SNR − dBFS SFDR − dBc, dBFS 100 96 fIN = 60.1 MHz SFDR (dBFS) G033 Figure 45. Submit Documentation Feedback Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 35 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ..................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS - ADS6148 (continued) All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 DBFS differential analog input, internal reference mode, 0 dB gain, LVDS output interface (unless otherwise noted) PERFORMANCE vs TEMPERATURE PERFORMANCE vs INPUT CLOCK AMPLITUDE 96 90 94 76 SFDR 78 fIN = 60 MHz 77 86 74 84 73 SNR 82 72 80 −40 71 −20 0 20 40 60 90 88 86 73 84 72 82 71 1.70 2.20 Figure 47. PERFORMANCE vs INPUT CLOCK DUTY CYCLE PERFORMANCE vs VCM VOLTAGE 75 84 74 SNR 80 73 76 72 72 94 50 55 60 65 SFDR 92 74 90 73 86 1.30 70 Input Clock Duty Cycle − % 75 SNR 88 71 45 SFDR − dBc SFDR 76 fIN = 60.1 MHz External Reference Mode 76 88 G035 96 SNR − dBFS 92 SFDR − dBc 1.20 Input Clock Amplitude − VPP 77 40 70 0.70 G034 fIN = 5 MHz 35 74 SNR Figure 46. 96 30 75 80 0.20 80 T − Temperature − °C 76 SFDR SFDR − dBc 75 SNR − dBFS SFDR − dBc 92 88 SNR − dBFS 77 fIN = 60.1 MHz 1.35 G036 1.40 1.45 72 1.50 1.55 VVCM − VCM Voltage − V Figure 48. SNR − dBFS 92 1.60 1.65 71 1.70 G037 Figure 49. OUTPUT NOISE HISTOGRAM 40 RMS (LSB) = 1 35 Occurence − % 30 25 20 15 10 5 0 8203 8204 8205 8206 8207 8208 8209 8210 8211 8212 Output Code G038 Figure 50. 36 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com ..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008 TYPICAL CHARACTERISTICS - ADS6129 All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 DBFS differential analog input, internal reference mode, 0 dB gain, LVDS output interface (unless otherwise noted) FFT for 20 MHz INPUT SIGNAL FFT for 60 MHz INPUT SIGNAL 0 0 SFDR = 94.87 dBc SINAD = 70.73 dBFS SNR = 70.77 dBFS THD = 89.9 dBc −20 −40 Amplitude − dB Amplitude − dB −40 SFDR = 87.8 dBc SINAD = 70.5 dBFS SNR = 70.6 dBFS THD = 84 dBc −20 −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 25 50 75 100 f − Frequency − MHz 125 0 25 50 G039 Figure 51. FFT for 170 MHz INPUT SIGNAL 125 G040 FFT for 300 MHz INPUT SIGNAL 0 SFDR = 81.9 dBc SINAD = 69.2 dBFS SNR = 69.5 dBFS THD = 79.7 dBc −20 SFDR = 76.09 dBc SINAD = 67.13 dBFS SNR = 67.95 dBFS THD = 73.72 dBc −20 −40 Amplitude − dB −40 Amplitude − dB 100 Figure 52. 0 −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 25 50 75 100 f − Frequency − MHz 125 0 25 50 G041 G042 fIN1 = 185.1 MHz, –36 dBFS fIN2 = 190.1 MHz, –36 dBFS 2-Tone IMD = –103 dBFS SFDR = –97 dBFS −20 −40 Amplitude − dB −40 125 FFT for 2-TONE INPUT SIGNAL (IMD) 0 fIN1 = 185.1 MHz, –7 dBFS fIN2 = 190.1 MHz, –7 dBFS 2-Tone IMD = –90.5 dBFS SFDR = –91 dBFS −20 100 Figure 54. FFT for 2-TONE INPUT SIGNAL (IMD) 0 75 f − Frequency − MHz Figure 53. Amplitude − dB 75 f − Frequency − MHz −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 25 50 75 f − Frequency − MHz 100 125 G043 0 25 50 Figure 55. Copyright © 2008, Texas Instruments Incorporated 75 100 f − Frequency − MHz 125 G044 Figure 56. Submit Documentation Feedback Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 37 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ..................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS - ADS6129 (continued) All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 DBFS differential analog input, internal reference mode, 0 dB gain, LVDS output interface (unless otherwise noted) SFDR vs INPUT FREQUENCY SNR vs INPUT FREQUENCY 100 74 95 73 72 LVDS 85 SNR − dBFS SFDR − dBc 90 80 CMOS 75 70 70 LVDS 69 68 65 67 60 66 55 65 50 CMOS 64 0 50 100 150 200 250 300 350 400 450 500 fIN − Input Frequency − MHz 0 50 100 150 200 250 300 350 400 450 500 fIN − Input Frequency − MHz G045 Figure 57. Figure 58. SFDR vs GAIN SINAD vs GAIN 100 5 dB 80 6 dB 75 70 2 dB 65 60 1 dB 2 dB 71 SINAD − dBFS 85 0 dB 73 3 dB 4 dB 90 69 67 65 3 dB 63 4 dB 5 dB 61 6 dB 59 1 dB 55 57 0 dB 50 Input adjusted to get −1dBFS input 55 0 50 100 150 200 250 300 350 400 450 500 fIN − Input Frequency − MHz G047 0 50 100 150 200 250 300 350 400 450 500 fIN − Input Frequency − MHz Figure 59. 38 G046 75 Input adjusted to get −1dBFS input 95 SFDR − dBc 71 Submit Documentation Feedback G048 Figure 60. Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com ..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008 TYPICAL CHARACTERISTICS - ADS6129 (continued) All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 DBFS differential analog input, internal reference mode, 0 dB gain, LVDS output interface (unless otherwise noted) PERFORMANCE vs INPUT AMPLITUDE PERFORMANCE vs INPUT COMMON-MODE VOLTAGE 110 76 73 SNR (dBFS) 72 60 71 50 70 fIN = 60 MHz −50 −40 −30 −20 −10 68 1.40 1.45 1.50 1.55 1.60 PERFORMANCE vs AVDD SUPPLY PERFORMANCE vs DRVDD SUPPLY 90 94 74 92 73 88 72 86 71 84 SNR 82 3.2 3.3 3.4 3.5 AVDD − Supply Voltage − V 3.6 74 73 SFDR 88 72 86 71 84 69 82 80 1.6 G051 75 90 70 68 3.7 76 fIN = 60.1 MHz AVDD = 3.3 V 70 SNR 69 1.7 1.8 1.9 68 2.0 DRVDD − Supply Voltage − V Figure 63. Copyright © 2008, Texas Instruments Incorporated G050 96 75 SFDR 69 1.65 VCM − Common-Mode Voltage of Analog Inputs − V 76 3.1 70 Figure 62. 92 SFDR − dBc 82 1.35 G049 fIN = 60.1 MHz DRVDD = 1.8 V 3.0 71 SNR Figure 61. 96 80 2.9 86 84 0 Input Amplitude − dBFS 94 72 69 SFDR (dBc) SFDR − dBc 30 −60 SFDR 88 SNR − dBFS 40 73 SNR − dBFS 80 90 SFDR − dBc 74 SNR − dBFS 90 70 74 75 SNR − dBFS SFDR − dBc, dBFS 100 92 fIN = 60 MHz SFDR (dBFS) G052 Figure 64. Submit Documentation Feedback Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 39 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ..................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS - ADS6129 (continued) All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 DBFS differential analog input, internal reference mode, 0 dB gain, LVDS output interface (unless otherwise noted) PERFORMANCE vs TEMPERATURE PERFORMANCE vs INPUT CLOCK AMPLITUDE 74 94 fIN = 60 MHz 92 73 75 86 71 SNR 84 70 74 SFDR SFDR − dBc 72 SFDR SNR − dBFS SFDR − dBc 90 88 88 73 86 72 84 71 82 82 69 80 −40 0 20 40 60 78 0.20 80 T − Temperature − °C 1.70 2.20 Figure 66. PERFORMANCE vs INPUT CLOCK DUTY CYCLE PERFORMANCE vs VCM VOLTAGE 73 84 72 SNR 80 71 76 69 45 50 55 60 Input Clock Duty Cycle − % 65 73 SFDR 86 72 84 71 SNR 82 70 72 74 88 SFDR − dBc 88 G054 fIN = 60.1 MHz External Reference Mode 74 SFDR 2.70 90 SNR − dBFS 92 SFDR − dBc 1.20 Input Clock Amplitude − VPP 75 40 68 0.70 G053 fIN = 5 MHz 35 69 Figure 65. 96 30 70 SNR 80 68 −20 SNR − dBFS 90 76 fIN = 60 MHz 80 1.30 70 SNR − dBFS 92 70 1.35 G055 1.40 1.45 1.50 1.55 VVCM − VCM Voltage − V Figure 67. 1.60 1.65 69 1.70 G056 Figure 68. OUTPUT NOISE HISTOGRAM 60 Occurence − % 50 40 30 20 10 0 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 Output Code G057 Figure 69. 40 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com ..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008 TYPICAL CHARACTERISTICS - ADS6128 All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 DBFS differential analog input, internal reference mode, 0 dB gain, LVDS output interface (unless otherwise noted) FFT for 20 MHz INPUT SIGNAL FFT for 60 MHz INPUT SIGNAL 0 0 SFDR = 90.8 dBc SINAD = 70.6 dBFS SNR = 70.7 dBFS THD = 87.8 dBc −20 −40 Amplitude − dB Amplitude − dB −40 SFDR = 92.5 dBc SINAD = 70.5 dBFS SNR = 70.6 dBFS THD = 88.9 dBc −20 −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 20 40 60 80 100 f − Frequency − MHz 0 20 40 G058 Figure 70. FFT for 170 MHz INPUT SIGNAL 100 G059 FFT for 300 MHz INPUT SIGNAL 0 SFDR = 82.59 dBc SINAD = 69.18 dBFS SNR = 69.42 dBFS THD = 80.99 dBc −20 SFDR = 76.3 dBc SINAD = 67.5 dBFS SNR = 68.1 dBFS THD = 75.1 dBc −20 −40 Amplitude − dB −40 Amplitude − dB 80 Figure 71. 0 −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 20 40 60 80 100 f − Frequency − MHz 0 20 40 60 80 100 f − Frequency − MHz G060 Figure 72. G061 Figure 73. FFT for 2-TONE INPUT SIGNAL (IMD) FFT for 2-TONE INPUT SIGNAL (IMD) 0 0 fIN1 = 185.1 MHz, –7 dBFS fIN2 = 190.1 MHz, –7 dBFS 2-Tone IMD = –90 dBFS SFDR = –88 dBFS −20 fIN1 = 185.1 MHz, –36 dBFS fIN2 = 190.1 MHz, –36 dBFS 2-Tone IMD = –101 dBFS SFDR = –96 dBFS −20 −40 Amplitude − dB −40 Amplitude − dB 60 f − Frequency − MHz −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 20 40 60 f − Frequency − MHz 80 100 0 G062 20 40 Figure 74. Copyright © 2008, Texas Instruments Incorporated 60 80 100 f − Frequency − MHz G063 Figure 75. Submit Documentation Feedback Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 41 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ..................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS - ADS6128 (continued) All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 DBFS differential analog input, internal reference mode, 0 dB gain, LVDS output interface (unless otherwise noted) SFDR vs INPUT FREQUENCY SNR vs INPUT FREQUENCY 100 74 95 73 72 LVDS 85 SNR − dBFS SFDR − dBc 90 80 CMOS 75 70 70 LVDS 69 68 65 67 60 66 55 65 50 CMOS 64 0 50 100 150 200 250 300 350 400 450 500 fIN − Input Frequency − MHz 0 50 100 150 200 250 300 350 400 450 500 fIN − Input Frequency − MHz G064 Figure 76. Figure 77. SFDR vs GAIN SINAD vs GAIN 100 5 dB 80 6 dB 75 70 2 dB 65 60 1 dB 2 dB 71 SINAD − dBFS 85 0 dB 73 3 dB 4 dB 90 69 67 65 3 dB 63 4 dB 5 dB 61 6 dB 59 1 dB 55 57 0 dB 50 Input adjusted to get −1dBFS input 55 0 50 100 150 200 250 300 350 400 450 500 fIN − Input Frequency − MHz G066 0 50 100 150 200 250 300 350 400 450 500 fIN − Input Frequency − MHz Figure 78. 42 G065 75 Input adjusted to get −1dBFS input 95 SFDR − dBc 71 Submit Documentation Feedback G067 Figure 79. Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com ..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008 TYPICAL CHARACTERISTICS - ADS6128 (continued) All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 DBFS differential analog input, internal reference mode, 0 dB gain, LVDS output interface (unless otherwise noted) PERFORMANCE vs INPUT AMPLITUDE PERFORMANCE vs INPUT COMMON-MODE VOLTAGE 110 76 60 71 50 70 SFDR (dBc) −40 −30 −20 −10 68 1.45 1.50 1.55 1.60 PERFORMANCE vs AVDD SUPPLY PERFORMANCE vs DRVDD SUPPLY 90 75 94 74 92 73 88 72 SNR 86 71 84 82 3.3 3.4 3.5 AVDD − Supply Voltage − V 3.6 G069 76 fIN = 60.1 MHz AVDD = 3.3 V 75 74 SFDR 90 73 88 72 SNR 86 71 70 84 70 69 82 69 68 3.7 80 1.6 G070 1.7 1.8 1.9 68 2.0 DRVDD − Supply Voltage − V Figure 82. Copyright © 2008, Texas Instruments Incorporated 69 1.65 96 SFDR − dBc SFDR 3.2 1.40 VCM − Common-Mode Voltage of Analog Inputs − V 76 3.1 70 Figure 81. 92 SFDR − dBc 86 1.35 G068 fIN = 60.1 MHz DRVDD = 1.8 V 3.0 71 SNR Figure 80. 96 80 2.9 90 88 0 Input Amplitude − dBFS 94 72 69 fIN = 60 MHz −50 SFDR 92 SNR − dBFS 40 73 SNR − dBFS 72 SFDR − dBc 73 SNR (dBFS) 70 30 −60 94 74 SNR − dBFS 90 80 74 75 SNR − dBFS SFDR − dBc, dBFS 100 96 fIN = 60 MHz SFDR (dBFS) G071 Figure 83. Submit Documentation Feedback Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 43 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ..................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS - ADS6128 (continued) All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 DBFS differential analog input, internal reference mode, 0 dB gain, LVDS output interface (unless otherwise noted) PERFORMANCE vs TEMPERATURE PERFORMANCE vs INPUT CLOCK AMPLITUDE 96 SFDR 92 94 74 76 fIN = 60 MHz 75 88 72 SNR 86 71 84 70 82 −40 69 −20 0 20 40 60 90 88 86 71 84 70 82 69 1.70 2.20 Figure 85. PERFORMANCE vs INPUT CLOCK DUTY CYCLE PERFORMANCE vs VCM VOLTAGE 73 84 72 SNR 80 71 76 94 69 45 50 55 60 Input Clock Duty Cycle − % 65 73 SFDR 92 72 90 71 SNR 88 70 72 SFDR − dBc SFDR 74 fIN = 60.1 MHz External Reference Mode 74 88 G073 96 SNR − dBFS 92 SFDR − dBc 1.20 Input Clock Amplitude − VPP 75 40 68 0.70 G072 fIN = 5 MHz 35 72 SNR Figure 84. 96 30 73 80 0.20 80 T − Temperature − °C 74 SFDR SFDR − dBc 73 SNR − dBFS SFDR − dBc 92 90 SNR − dBFS 75 fIN = 60.1 MHz 86 1.30 70 1.35 G074 1.40 1.45 70 1.50 1.55 VVCM − VCM Voltage − V Figure 86. SNR − dBFS 94 1.60 1.65 69 1.70 G075 Figure 87. OUTPUT NOISE HISTOGRAM 60 Occurence − % 50 40 30 20 10 0 2048 2049 2050 2051 2052 2053 2054 2055 2056 Output Code G076 Figure 88. 44 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com ..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008 TYPICAL CHARACTERISTICS - COMMON PLOTS All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 DBFS differential analog input, internal reference mode, 0 dB gain, LVDS output interface (unless otherwise noted) CMRR vs INPUT FREQUENCY TOTAL POWER vs SAMPLING FREQUENCY 1.0 0.9 −20 0.8 P − Total Power − W 0 −10 CMRR − dB −30 −40 −50 −60 −70 CL = 10 pF 0.7 0.6 LVDS 0.5 0.4 CMOS 0.3 −80 0.2 −90 0.1 0.0 −100 0 20 40 60 80 0 100 fIN − Input Frequency − MHz 50 100 150 200 fS − Sampling Frequency − MSPS G079 Figure 89. 250 G077 Figure 90. DRVDD CURRENT vs SAMPLING FREQUENCY IDRVDD − DRVDD Current − mA 100 fIN = 3 MHz CL = 10 pF 90 80 70 LVDS 60 50 40 CMOS 30 20 OE Disabled 10 0 0 50 100 150 200 fS − Sampling Frequency − MSPS 250 G078 Figure 91. Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 45 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ..................................................................................................................................................... www.ti.com CONTOUR PLOTS - ADS6149/ADS6148/ADS6129/ADS6128 Plots are at 25°C, AVDD = 3.3V, DRVDD = 1.8 V, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, LVDS output interface (unless otherwise noted) 250 240 92 84 76 84 84 220 fS - Sampling Frequency - MSPS 80 88 64 68 72 60 84 200 76 84 68 80 180 88 160 76 72 84 80 84 140 68 80 120 50 60 72 88 92 80 20 64 88 88 100 64 60 92 76 84 100 200 150 250 350 300 400 500 450 fIN - Input Frequency - MHz 65 60 70 75 80 85 90 95 SFDR - dBc M0049-17 Figure 92. SFDR Contour Plot (0 dB gain) 250 240 84 84 84 68 72 80 64 76 fS - Sampling Frequency - MSPS 220 72 200 180 60 88 84 80 88 68 84 160 84 76 84 64 72 84 60 140 120 84 100 80 20 64 80 88 84 100 200 300 400 500 60 68 72 76 600 800 700 fIN - Input Frequency - MHz 65 60 70 80 85 90 SFDR - dBc 95 M0049-18 Figure 93. SFDR Contour Plot (6 dB gain) 46 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com ..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008 CONTOUR PLOTS - ADS6149/ADS6148 Plots are at 25°C, AVDD = 3.3V, DRVDD = 1.8 V, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, LVDS output interface (unless otherwise noted) 250 240 220 fS - Sampling Frequency - MSPS 66 67 73 70 71 72 69 68 200 180 69 73 70 72 160 66 67 68 71 140 120 69 73 100 66 70 71 72 68 67 350 400 65 74 80 20 50 100 200 150 250 300 500 450 fIN - Input Frequency - MHz 64 66 65 67 68 69 70 71 72 73 74 75 SNR - dBFS M0048-19 Figure 94. SNR Contour Plot (0 dB gain) 250 240 67 66 65 64 63 62 fS - Sampling Frequency - MSPS 220 200 67 180 160 66 68 63 64 65 62 140 120 68 63 64 65 66 67 62 100 61 80 20 100 300 200 400 500 600 700 800 fIN - Input Frequency - MHz 60 61 63 62 64 65 66 67 SNR - dBFS 68 69 M0048-20 Figure 95. SNR Contour Plot (6 dB gain) Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 47 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ..................................................................................................................................................... www.ti.com APPLICATION INFORMATION THEORY OF OPERATION ADS6149/48 and ADS6129/28 is a family of high performance, low power 14-bit and 12-bit pipeline A/D converters with maximum sampling rate up to 250 MSPS. At every rising edge of the input clock, the analog input signal is sampled and sequentially converted by a pipeline of low resolution stages. In each stage, the sampled and held signal is converted by a high speed, low resolution flash sub-ADC. The difference (residue) between the stage input and its quantized equivalent is gained and propagates to the next stage. At every clock, each succeeding stage resolves the sampled input with greater accuracy. The digital outputs from all stages are combined in a digital correction logic block to create the final 14 or 12 bit code, after a data latency of 18 clock cycles. The digital output is available as either DDR LVDS or parallel CMOS and coded in either straight offset binary or binary 2s complement format. The dynamic offset of the first stage sub-ADC limits the maximum analog input frequency to about 500MHz (with 2VPP amplitude) and about 800MHz (with 1VPP amplitude). ANALOG INPUT The analog input consists of a switched-capacitor based differential sample and hold architecture. This differential topology results in a good AC performance even for high input frequencies at high sampling rates. The INP and INM pins have to be externally biased around a common-mode voltage of 1.5V, available on VCM pin. For a full-scale differential input, each input pin INP, INM has to swing symmetrically between VCM + 0.5V and VCM – 0.5V, resulting in a 2Vpp differential input swing. Sampling Switch Lpkg~1 nH 10 W Sampling Capacitor RCR Filter INP Cbond ~ 1 pF 100 W Resr 200 W Ron 15 W Csamp 2 pF 3 pF 3 pF Lpkg~1 nH Cpar2 0.5 pF 10 W Ron 10 W Cpar1 0.25 pF 100 W Csamp 2 pF Ron 15 W INM Cpar2 0.5 pF Cbond ~ 1 pF Resr 200 W Sampling Capacitor Sampling Switch Figure 96. Analog Input Equivalent Circuit The input sampling circuit has a high 3-dB bandwidth that extends up to 700 MHz (measured from the input pins to the sampled voltage). 48 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com ..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008 Drive Circuit Requirements For optimum performance, the analog inputs must be driven differentially. This improves the common-mode noise immunity and even order harmonic rejection. A 5 Ω to 15 Ω resistor in series with each input pin is recommended to damp out ringing caused by package parasitics. It is also necessary to present low impedance (< 50 Ω) for the common mode switching currents. This can be achieved by using two resistors from each input terminated to the common mode voltage (VCM). Note that the device includes an internal R-C filter from each input to ground. The purpose of this filter is to absorb the glitches caused by the opening and closing of the sampling capacitors. The cut-off frequency of the R-C filter involves a trade-off. A lower cut-off frequency (larger C) absorbs glitches better, but also reduces the input bandwidth and the maximum input frequency that can be supported. On the other hand, with no internal R-C filter, high input frequency can be supported, but now the sampling glitches need to be supplied by the external driving circuit. This has limitations due to the presence of the package bond-wire inductance. In ADS61x9/x8, the R-C component values have been optimized while supporting high input bandwidth (up to 750 MHz). However, in applications where high input frequency support is not required, the filtering of the glitches can be improved further using an external R-C-R filter (as shown in Figure 99 and Figure 100). In addition to the above, the drive circuit may have to be designed to provide a low insertion loss over the desired frequency range and matched impedance to the source. While doing this, the ADC input impedance must be considered. Figure 97 and Figure 98 show the impedance (Zin = Rin || Cin) looking into the ADC input pins. 100 Resistance - kW 10 1 0.1 0.01 0 100 200 300 400 500 600 700 800 900 1000 f - Frequency - MHz Figure 97. ADC Analog Input Resistance (Rin) Across Frequency Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 49 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ..................................................................................................................................................... www.ti.com 4.5 4 Capacitance - pF 3.5 3 2.5 2 1.5 1 0 100 200 300 400 500 600 700 800 900 1000 f - Frequency - MHz Figure 98. ADC Analog Input Capacitance (Cin) Across Frequency Driving Circuit Two example driving circuit configurations are shown in Figure 99 and Figure 100 – one optimized for low bandwidth (low input frequencies) and the other one for high bandwidth to support higher input frequencies. In Figure 99, an external R-C-R filter using 22pF has been used. Together with the series inductor (39nH), this combination forms a filter and absorbs the sampling glitches. Due to the large capacitor (22pF) in the R-C-R and the 15Ω resistors in series with each input pin, the drive circuit has low bandwidth, and supports low input frequencies (< 100MHz).. To support high input frequencies (up to about 300MHz, see Figure 100), the capacitance used in the R-C-R is reduced to 3.3pF and the series inductors are shorted out. Together with the lower series resistors (5Ω), this drive circuit provides high bandwidth and supports high input frequencies. A transformer such as ADT1-1WT or ETC1-1-13 can be used up to 300MHz. In Figure 100, by dropping the external R-C-R filter, the drive circuit has high bandwidth and can support high input frequencies (> 300MHz). For example, a transformer such as the ADTL2-18 can be used. Note that both the drive circuits have been terminated by 50Ω near the ADC side. The termination is accomplished using a 25Ω resistor from each input to the 1.5V common-mode (VCM) from the device. This biases the analog inputs around the required common-mode voltage. 50 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com ..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008 39 nH 15 W 0.1 mF 0.1 mF INP 50 W 0.1 mF 50 W 25 W 22 pF 25 W 50 W 50 W INM 1:1 1:1 0.1 mF 15 W 39 nH VCM Figure 99. Drive Circuit with Low Bandwidth (for low input frequencies) The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order harmonic performance. Connecting two identical RF transformers back to back helps minimize this mismatch and good performance is obtained for high frequency input signals. An additional termination resistor pair may be required between the two transformers as shown in the figures. The center point of this termination is connected to ground to improve the balance between the P and M sides. The values of the terminations between the transformers and on the secondary side have to be chosen to get an effective 50Ω (in the case of 50Ω source impedance). 0.1 mF 5W 0.1 mF INP 0.1 mF 50 W 25 W 3.3 pF 25 W 5W 50 W INM 1:1 1:1 0.1 mF VCM Figure 100. Drive Circuit with High Bandwidth (for high input frequencies) Input Common-Mode To ensure a low-noise common-mode reference, the VCM pin is filtered with a 0.1µF low-inductance capacitor connected to ground. The VCM pin is designed to directly drive the ADC inputs. The input stage of the ADC sinks a common-mode current in the order of 500µA (per input pin, at 250 MSPS). Equation 1 describes the dependency of the common-mode current and the sampling frequency. 500 mA ´ Fs 250 MSPS (1) This equation helps to design the output capability and impedance of the CM driving circuit accordingly. REFERENCE ADS614X/2X has built-in internal references REFP and REFM, requiring no external components. Design schemes are used to linearize the converter load seen by the references; this and the on-chip integration of the requisite reference capacitors eliminates the need for external decoupling. The full-scale input range of the converter can be controlled in the external reference mode as explained below. The internal or external reference modes can be selected by programming the serial interface register bit <REF>. Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 51 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ..................................................................................................................................................... www.ti.com INTREF Internal Reference VCM INTREF EXTREF REFM REFP S0165-09 Figure 101. Reference Section Internal Reference When the device is in internal reference mode, the REFP and REFM voltages are generated internally. Common-mode voltage (1.5V nominal) is output on VCM pin, which can be used to externally bias the analog input pins. External Reference When the device is in external reference mode, the VCM acts as a reference input pin. The voltage forced on the VCM pin is buffered and gained by 1.33 internally, generating the REFP and REFM voltages. The differential input voltage corresponding to full-scale is given by Equation 2. Full-scale differential input pp = (Voltage forced on VCM) × 1.33 (2) In this mode, the 1.5V common-mode voltage to bias the input pins has to be generated externally. CLOCK INPUT ADS614X/2X clock inputs can be driven differentially (sine, LVPECL or LVDS) or single-ended (LVCMOS), with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to VCM using internal 5-kΩ resistors. This allows using transformer-coupled drive circuits for sine wave clock or ac-coupling for LVPECL, LVDS clock sources. 52 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com ..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008 Clock buffer Lpkg ~1 nH 20 W CLKP Cbond ~1 pF Ceq Ceq 5 kW Resr ~100 W VCM 2 pF 5 kW Lpkg ~1 nH 20 W CLKM Cbond ~1 pF Resr ~100 W Ceq ~ 1 to 3 pF, equivalent input capacitance of clock buffer Figure 102. Internal Clock Buffer Single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-µF capacitor, as shown in Figure 104. For best performance, the clock inputs have to be driven differentially, reducing susceptibility to common-mode noise. For high input frequency sampling, it is recommended to use a clock source with low jitter. Band-pass filtering of the clock source can help reduce the effect of jitter. There is no change in performance with a non-50% duty cycle clock input. 0.1 mF 0.1 mF CMOS Clock Input CLKP CLKP Differential Sine-Wave or PECL or LVDS Clock Input VCM 0.1 mF 0.1 mF CLKM CLKM S0168-14 S0167-10 Figure 103. Differential Clock Driving Circuit Copyright © 2008, Texas Instruments Incorporated Figure 104. Single-Ended Clock Driving Circuit Submit Documentation Feedback Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 53 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ..................................................................................................................................................... www.ti.com FINE GAIN CONTROL ADS614X/2X includes gain settings that can be used to get improved SFDR performance (compared to no gain). The gain is programmable from 0dB to 6dB (in 0.5 dB steps). For each gain setting, the analog input full-scale range scales proportionally, as shown in Table 9. The SFDR improvement is achieved at the expense of SNR; for each gain setting, the SNR degrades about 0.5–1dB. The SNR degradation is less at high input frequencies. As a result, the gain is useful at high input frequencies as the SFDR improvement is significant with marginal degradation in SNR. So, the gain can be used to trade-off between SFDR and SNR. Note that the default gain after reset is 0 dB. Table 9. Full-Scale Range Across Gains Gain, dB Type 0 Default after reset Full-Scale, VPP 2V 1 1.78 2 1.59 3 4 Fine, programmable 1.42 1.26 5 1.12 6 1.00 OFFSET CORRECTION ADS61x9/x8 has an internal offset correction algorithm that estimates and corrects the dc offset up to ±10mV. The correction can be enabled using the serial register bit <ENABLE OFFSET CORR>. Once enabled, the algorithm estimates the channel offset and applies the correction every clock cycle. The time constant of the correction loop is a function of the sampling clock frequency. The time constant can be controlled using register bits <OFFSET CORR TIME CONSTANT> as described inTable 10. After the offset is estimated, the correction can be locked in by setting <OFFSET CORR TIME CONSTANT> = 0. Once locked, the last estimated value is used for offset correction every clock cycle. Note that offset correction is disabled by default after reset. Figure 105 shows the time response of the offset correction algorithm, after it is enabled. Table 10. Time Constant of Offset Correction Algorithm <OFFSET CORR TIME CONSTANT> D3-D0 Time constant (TCCLK), number of clock cycles Time constant, sec (=TCCLK x 1/Fs) (1) 0000 256 k 1 ms 0001 512 k 2 ms 0010 1M 4 ms 0011 2M 8 ms 0100 4M 17 ms 0101 8M 33 ms 0110 16 M 67 ms 0111 32 M 134 ms 1000 64 M 268 ms 1001 128 M 536 ms 1010 256 M 1.1 s 1011 512 M 2.2 s 1100 RESERVED – 1101 RESERVED – 1110 RESERVED – 1111 RESERVED – 54 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com ..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008 8204 Offset Correction Disabled 8200 Offset Correction Enabled 8196 8192 8188 Code − LSB 8184 Output Data With Offset Corrected 8180 8176 8172 8168 Output Data With 36 LSB Offset 8164 8160 8156 8152 8148 0 4 8 12 16 20 24 28 32 36 40 44 48 52 t − Time − µs 56 G080 Figure 105. Output Code Time Response With Offset Correction Enabled POWER DOWN ADS614X/2X has three power down modes – power down global, standby and output buffer disable. Power Down Global In this mode, the entire chip including the A/D converter, internal reference and the output buffers are powered down resulting in reduced total power dissipation of about 20 mW. The output buffers are in high impedance state. The wake-up time from global power down to data becoming valid in normal mode is typically 25 µs. This can be controlled using register bit <PDN GLOBAL> or using SDATA pin (in parallel configuration mode). Standby Here, only the A/D converter is powered down and internal references are active, resulting in fast wake-up time of 300 ns. The total power dissipation in standby is about 120 mW. This can be controlled using register bit <STANDBY>. Output Buffer Disable The output buffers can be disabled and put in high impedance state – wakeup time from this mode is fast, about 40 ns. This can be controlled using register bit <PDN OBUF>. Input Clock Stop In addition to the above, the converter enters a low-power mode when the input clock frequency falls below 1 MSPS. The power dissipation is about 120 mW. POWER SUPPLY SEQUENCE During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies are separated in the device. Externally, they can be driven from separate supplies or from a single supply. DIGITAL OUTPUT INFORMATION ADS614X/2X provides 14-bit/12-bit data and an output clock synchronized with the data. Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 55 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ..................................................................................................................................................... www.ti.com Output Interface Two output interface options are available – Double Data Rate (DDR) LVDS and parallel CMOS. They can be selected using the serial interface register bit <ODI> or using DFS pin in parallel configuration mode. DDR LVDS Outputs In this mode, the data bits and clock are output using LVDS (Low Voltage Differential Signal) levels. Two data bits are multiplexed and output on each LVDS differential pair. Pins 14 bit ADC data CLKOUTP CLKOUTM Output Clock D0_D1_P D0_D1_M Data bits D0, D1 D2_D3_P D2_D3_M Data bits D2, D3 D4_D5_P D4_D5_M Data bits D4, D5 CLKOUTP CLKOUTM D0_D1_P D0_D1_M LVDS Buffers LVDS Buffers Pins Output Clock Data bits D0, D1 P D2_D3_ D2_D3_M D4_D5_P D4_D5_M Data bits D2, D3 Data bits D4, D5 12 bit ADC data D6_D7_P D6_D7_P D6_D7_M Data bits D6, D7 D8_D9_P D8_D9_M Data bits D8, D9 D10_D11_P D10_D11_M Data bits D10, D11 D12_D13_P D12_D13_M Data bits D12, D13 D6_D7_M D8_D9_P D8_D9_M Data bits D6, D7 Data bits D8, D9 D10_D11_P D10_D11_M Data bits D10, D11 ADS612X ADS 614 X Figure 106. 14-Bit ADC LVDS Outputs Figure 107. 12-Bit ADC LVDS Outputs Even data bits D0, D2, D4… are output at the falling edge of CLKOUTP and the odd data bits D1, D3, D5… are output at the rising edge of CLKOUTP. Both the rising and falling edges of CLKOUTP have to be used to capture all of the data bits (see Figure 108). 56 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com ..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008 CLKOUTP CLKOUTM D0_D1_P, D0_D1_M D0 D1 D0 D1 D2_D3_P, D2_D3_M D2 D3 D2 D3 D4_D5_P, D4_D5_M D4 D5 D4 D5 D6_D7_P, D6_D7_M D6 D7 D6 D7 D8_D9_P, D8_D9_M D8 D9 D8 D9 D10_D11_P, D10_D11_M D10 D11 D10 D11 D12_D13_P, D12_D13_M D12 D13 D12 D13 Sample N Sample N+1 T0110-01 Figure 108. DDR LVDS Interface LVDS Buffer The equivalent circuit of each LVDS output buffer is shown in Figure 109. The buffer is designed to present an output impedance of 100 Ω (Rout). The differential outputs can be terminated at the receive end by a 100 Ω termination. The buffer output impedance behaves like a source-side series termination. By absorbing reflections from the receiver end, it helps to improve signal integrity. Note that this internal termination cannot be disabled and its value cannot be changed. Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 57 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ..................................................................................................................................................... www.ti.com + – Low 0.35 V High ADS6149/48/29/28 OUTP + – –0.35 V + – Rout High 1.2 V Low External 100-W Load OUTM Switch impedance is nominally 50 W (±10%) When the High switches are closed, OUTP = 1.375 V, OUTM = 1.025 V When the Low switches are closed, OUTP = 1.025 V, OUTM = 1.375 V When the High (or Low) switches are closed, Rout = 100 W S0374-01 Figure 109. LVDS Buffer Equivalent Circuit Parallel CMOS Interface In the CMOS mode, each data bit is output on separate pin as CMOS voltage level, every clock cycle. The rising edge of the output clock CLKOUT can be used to latch data in the receiver (for sampling frequencies up to 150 MSPS). Up to 150 MSPS, the setup and hold timings of the output data with respect to CLKOUT are specified. It is recommended to minimize the load capacitance seen by data and clock output pins by using short traces to the receiver. Also, match the output data and clock traces to minimize the skew between them. For sampling frequencies > 150 MSPS, it is recommended to use an external clock to capture data. The delay from input clock to output data and the data valid times are specified for the higher sampling frequencies. These timings can be used to delay the input clock appropriately and use it to capture the data (see Figure 4). 58 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com ..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008 Pins OVR_SDOUT CLKOUT D0 14-Bit ADC Data CMOS Output Buffers D1 D2 • • • D11 D12 D13 ADS614x Figure 110. CMOS Output Interface Output Buffer Strength Programmability Switching noise (caused by CMOS output data transitions) can couple into the analog inputs during the instant of sampling and degrade the SNR. The coupling and SNR degradation increases as the output buffer drive is made stronger. To minimize this, the CMOS output buffers are designed with controlled drive strength to get best SNR. The default drive strength also ensures wide data stable window for load capacitances up to 5 pF. CMOS Interface Power Dissipation With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every output pin. The maximum DRVDD current occurs when each output bit toggles between 0 and 1 every clock cycle. In an actual application, the DRVDD current would be determined by the average number of output bits switching, which is a function of the sampling frequency and the nature of the analog input signal. Digital current due to CMOS output switching = CL × DRVDD × (N × FAVG), where CL = load capacitance, N x FAVG = average number of output bits switching. Figure 91 shows the current across sampling frequencies at 2 MHz analog input frequency. Output Data Format Two output data formats are supported – 2s complement and offset binary. They can be selected using the serial interface register bit <DATA FORMAT> or controlling the DFS pin in parallel configuration mode. In the event of an input voltage overdrive, the digital outputs go to the appropriate full scale level. For a positive overdrive, the output code is 0x3FFF in offset binary output format, and 0x1FFF in 2s complement output format. For a negative input overdrive, the output code is 0x0000 in offset binary output format and 0x2000 in 2s complement output format. Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 59 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ..................................................................................................................................................... www.ti.com BOARD DESIGN CONSIDERATIONS Grounding A single ground plane is sufficient to give good performance, provided the analog, digital, and clock sections of the board are cleanly partitioned. See the EVM User Guide (SLWU061) for details on layout and grounding. Supply Decoupling As the ADS61x9/x8 already includes internal decoupling, minimal external decoupling can be used without loss in performance. Note that decoupling capacitors can help filter external power supply noise, so the optimum number of capacitors would depend on the actual application. The decoupling capacitors should be placed close to the converter supply pins. Exposed Pad In addition to providing a path for heat dissipation, the pad is also electrically connected to digital ground internally. So, it is necessary to solder the exposed pad to the ground plane for best thermal and electrical performance. For detailed information, see the application notes for QFN Layout Guidelines (SLOA122) and QFN/SON PCB Attachment (SLUA271). 60 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 ADS6149/ADS6129 ADS6148/ADS6128 www.ti.com ..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008 DEFINITION OF SPECIFICATIONS Analog Bandwidth – The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low frequency value. Aperture Delay – The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs. This delay will be different across channels. The maximum variation is specified as aperture delay variation (channel-channel). Aperture Uncertainty (Jitter) – The sample-to-sample variation in aperture delay. Clock Pulse Width/Duty Cycle – The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a percentage. A perfect differential sine-wave clock results in a 50% duty cycle. Maximum Conversion Rate – The maximum sampling rate at which certified operation is given. All parametric testing is performed at this sampling rate unless otherwise noted. Minimum Conversion Rate – The minimum sampling rate at which the ADC functions. Differential Nonlinearity (DNL) – An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs. Integral Nonlinearity (INL) – The INL is the deviation of the ADC's transfer function from a best fit line determined by a least squares curve fit of that transfer function, measured in units of LSBs. Gain Error – Gain error is the deviation of the ADC's actual input full-scale range from its ideal value. The gain error is given as a percentage of the ideal input full-scale range. Gain error has two components: error due to reference inaccuracy and error due to the channel. Both these errors are specified independently as EGREF and EGCHAN. To a first order approximation, the total gain error will be ETOTAL ~ EGREF + EGCHAN. For example, if ETOTAL = ±0.5%, the full-scale input varies from (1-0.5/100) x FSideal to (1 + 0.5/100) x FSideal. Offset Error – The offset error is the difference, given in number of LSBs, between the ADC's actual average idle channel output code and the ideal average idle channel output code. This quantity is often mapped into mV. Temperature Drift – The temperature drift coefficient (with respect to gain error and offset error) specifies the change per degree Celsius of the parameter from TMIN to TMAX. It is calculated by dividing the maximum deviation of the parameter across the TMIN to TMAX range by the difference TMAX–TMIN. Signal-to-Noise Ratio – SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding the power at DC and the first nine harmonics. P SNR = 10Log10 S PN (3) SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s full-scale range. Signal-to-Noise and Distortion (SINAD) – SINAD is the ratio of the power of the fundamental (PS) to the power of all the other spectral components including noise (PN) and distortion (PD), but excluding dc. PS SINAD = 10Log10 PN + PD (4) SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter's full-scale range. Effective Number of Bits (ENOB) – The ENOB is a measure of the converter performance as compared to the theoretical limit based on quantization noise. Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 61 ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ..................................................................................................................................................... www.ti.com ENOB = SINAD - 1.76 6.02 (5) Total Harmonic Distortion (THD) – THD is the ratio of the power of the fundamental (PS) to the power of the first nine harmonics (PD). P THD = 10Log10 S PN (6) THD is typically given in units of dBc (dB to carrier). Spurious-Free Dynamic Range (SFDR) – The ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier). Two-Tone Intermodulation Distortion – IMD3 is the ratio of the power of the fundamental (at frequencies f1 and f2) to the power of the worst spectral component at either frequency 2f1–f2 or 2f2–f1. IMD3 is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s full-scale range. DC Power Supply Rejection Ratio (DC PSRR) – The DC PSSR is the ratio of the change in offset error to a change in analog supply voltage. The DC PSRR is typically given in units of mV/V. AC Power Supply Rejection Ratio (AC PSRR) – AC PSRR is the measure of rejection of variations in the supply voltage by the ADC. If ΔVSUP is the change in supply voltage and ΔVout is the resultant change of the ADC output code (referred to the input), then DVOUT (Expressed in dBc) PSRR = 20Log 10 DVSUP (7) Voltage Overload Recovery – The number of clock cycles taken to recover to less than 1% error after an overload on the analog inputs. This is tested by separately applying a sine wave signal with 6dB positive and negative overload. The deviation of the first few samples after the overload (from their expected values) is noted. Common Mode Rejection Ratio (CMRR) – CMRR is the measure of rejection of variation in the analog input common-mode by the ADC. If ΔVcm_in is the change in the common-mode voltage of the input pins and ΔVOUT is the resultant change of the ADC output code (referred to the input), then DVOUT (Expressed in dBc) CMRR = 20Log10 DVCM (8) Cross-Talk (only for multi-channel ADC)– This is a measure of the internal coupling of a signal from adjacent channel into the channel of interest. It is specified separately for coupling from the immediate neighboring channel (near-channel) and for coupling from channel across the package (far-channel). It is usually measured by applying a full-scale signal in the adjacent channel. Cross-talk is the ratio of the power of the coupling signal (as measured at the output of the channel of interest) to the power of the signal applied at the adjacent channel input. It is typically expressed in dBc. 62 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 PACKAGE OPTION ADDENDUM www.ti.com 17-Oct-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty ADS6128IRGZR ACTIVE QFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6129IRGZR ACTIVE QFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6129IRGZT ACTIVE QFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6148IRGZR ACTIVE QFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6148IRGZT ACTIVE QFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6149IRGZR ACTIVE QFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS6149IRGZT ACTIVE QFN RGZ 48 250 CU NIPDAU Level-3-260C-168 HR Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 30-Sep-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS6129IRGZR QFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 ADS6129IRGZT QFN RGZ 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 30-Sep-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS6129IRGZR QFN RGZ 48 2500 333.2 345.9 28.6 ADS6129IRGZT QFN RGZ 48 250 333.2 345.9 28.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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