May 1999 [ /Title (CA31 26) /Subject (TV Chrom a Processor) /Autho r () /Keywords (Harris Semiconductor, TV chroma processor, subcarrier regeneration, ntsc, acc, overload detector, keyed chroma output, color processor, industrial CA3126 T UCT ROD ACEMEN 47 P E 7 T L OLE REP 00-442-7 OBS ENDED 8 M ns 1 .com COM pplicatio @harris E R NO ntral A entapp Ce : c Call or email TV Chroma Processor Features Description • Phase Locked Subcarrier Regeneration Utilizes Sample-and-Hold Techniques The Harris CA3126 is a monolithic silicon integrated circuit designed for TV chroma processing and is ideally suited for NTSC color graphic applications that require subcarrier regeneration of the color burst signal. • Automatic Chrominance Control (ACC)/Killer Detector Employs Sample-and-Hold Techniques Part Number Information • Supplementary ACC with an Overload Detector to Prevent Oversaturation of this Picture Tube • Sinusoidal Subcarrier Output PART NUMBER • Keyed Chroma Output • Emitter Follower Buffered Outputs for Low Output Impedance TEMP. RANGE (oC) PKG. NO. PACKAGE CA3126E -40 to 85 16 Ld PDIP E16.3 CA3126M1 -40 to 85 20 Ld SOIC M20.3 • Linear DC Saturation Control Applications • TV/CATV Receiver Circuits • NTSC Color Decoder/Processor • Computer Graphics Subcarrier Regenerator • Timing Reference for Frame Grabbers • DSP Clock Timing Reference Source Pinouts CA3126 (PDIP) TOP VIEW CA3126 (SOIC) TOP VIEW CHROMA IN 1 16 CHROMA GAIN CONT. AFPC FILTER + 2 15 CHROMA OUT AFPC FILTER - 3 14 ZENER REF RF BYPASS 4 13 OVERLOAD DET. GROUND 5 12 V+ VCO OUT 6 VCO IN 7 CARRIER OUT 8 CHROMA IN 1 20 CHROMA GAIN CONT. AFPC FILTER + 2 19 CHROMA OUT NC 3 18 NC AFPC FILTER - 4 17 ZENER REF RF BYPASS 5 16 OVERLOAD DET. GROUND 6 15 V+ VCO OUT 7 14 ACC + VCO IN 8 13 ACC - NC 9 12 HORIZ. KEY IN 11 ACC+ 10 ACC9 HORIZ. KEY IN NC 10 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1999 8-33 11 CARRIER OUT File Number 860.5 CA3126 Absolute Maximum Ratings Thermal Information DC Supply Voltage (V+ to GND) (Note 1). . . . . . . . . . . . . . . . . 13.2V DC Current: Into V+ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38mA Into Zener Reference Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA DC Voltage (Horizontal Key In) Negative Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5V Positive Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V Thermal Resistance (Typical, Note 1) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Maximum Junction Temperature (Plastic Packages) . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. This rating does not apply when using the internal zener reference in conjunction with an external pass transistor. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER TA = 25oC, Chroma Gain Control at maximum position for all tests except as noted. Electrical specifications referenced to test circuit. TERMINAL, MEASUREMENT AND SYMBOL SWITCH POS. S1 S2 VCHROMA INPUT TP1 MIN TYP MAX UNITS DC ELECTRICAL SPECIFICATIONS Voltage Regulator V12 2 2 0 10.1 11.2 12.1 V Supply Current I12 2 2 0 16 25 38 mA SWITCHING ELECTRICAL SPECIFICATIONS (Note 3) Pull-In Range (Note 4) V8 (Note 6) 2 0.5VP-P ±250 - - Hz Oscillator Output V8 2 2 0 0.6 1.0 - VP-P 100% Chroma Output V15 1 2 0.5VP-P 1.4 2.7 - VP-P Overload Detector V15 1 1 0.5VP-P 0.4 - 0.7 VP-P Minimum Chroma Output (Note 5) V15 1 2 0.5VP-P - - 20 mVP-P 200% Chroma Output V15 1 2 1VP-P 70 100 140 20% Chroma Output V15 1 2 0.1VP-P 40 - 105 % of 100% Reading VTP1 1 2 Vary 5 - 60 mVP-P Kill Level NOTES: 3. Except for pull-in range testing, tune oscillator trimmer capacitor for free running frequency of 3.579545MHz ±10Hz. 4. Set Switch 1 to Position 2, detune oscillator ±250Hz, set Switch 1 to Position 1, and check for oscillator pull-in. 5. Set Chroma Gain Control to minimum position (CCW). 8-34 CA3126 Test Circuit +24V 10kΩ 270Ω 2N2102 VREG 0.05µF 3.9kΩ 1 2 CW 0.02µF S2 47kΩ 10kΩ CCW OSCILLOSCOPE 0.02µF I 2kΩ 0.01µF 1µF 1µF 16 15 14 13 CHROMA GAIN CONTROL 12 11 10 9 5 6 7 8 CA3126 1 2 4 0.01µF 2 kΩ 0.01µF 2.45kΩ 3 0.01µF 0.1µF 0.01µF 10pF NPO 0.01µF TP1 S1 33pF N750 20pF N750 XTAL 3.579545MHz 2 1 CHROMA INPUT SIGNAL COUNTER 680Ω 50Ω VARIABLE ATTENUATOR TEST SIGNAL GENERATOR 2.5µs Pin numbers refer to the PDIP package. (A) BURST BURST SYNC. SUBCARRIER OUTPUT KEY PULSE PULSE GENERATOR 63.5µs 3.579545MHz 4µs (A) Chroma input signal (B) Key pulse input signal VCHROMA 0.46VCHROMA 1.0VPEAK (MIN) (B) 5µs CENTERED ON BURST 8-35 CA3126 Block Diagram TV CHROMA PROCESSOR AFPC FILTER 1.0µF 2kΩ RF BYPASS 0.01µF 0.01µF CRYSTAL FILTER 20pF 0.01µF 7 33pF 680Ω 4 2 3 6 10pF CARRIER OUTPUT SIGNAL SAMPLE AND HOLD DC CONTR. BALANCED φ SHIFTER AFPC DET. -π/4 φ SHIFTER BIAS SAMPLE AND HOLD VCO AMPL. SUPPLY VOLTAGE +24V 8 0.01µF 270Ω AMPL. LIMIT 13 CHROMA INPUT +π/4 φ SHIFTER 2.45kΩ INTERN. REF. OVERLOAD DETECTOR ATTENUATOR SECOND CHROMA AMPL. COUPLING NETWORK CW 10 kΩ CCW CHROMA INPUT 1 CHROMA GAIN CONTROL 16 50kΩ 2µF 1.2kΩ FIRST CHROMA AMPL. 0.05 µF +11.2V 0.01 µF (NOTE 6) CHROMA OUTPUT 15 3.9kΩ BIAS CONTROL KILLER AMPL. ZENER REF. 14 KEYER 9 DELAY BIAS KILLER FILTER SIGNAL SAMPLE AND HOLD ACC AMPL. GND 2N2102 (NOTE 6) 12 0.01µF TO TERM. 12 10kΩ BALANCEUNBALANCE TRANSLATOR ACC DET. 2kΩ BIAS SAMPLE AND HOLD 5 DELAY BIAS CA3126 10 0.01µF 11 1µF ACC FILTER NOTES: 6. Optional design features. 7. Pinout numbers refer to the PDIP package. 8-36 0.01µF 0V 5µs WIDTH HORIZONTAL KEY INPUT CA3126 Schematic Diagram 4 RF BYPASS A SINGLE SAMPLE AND HOLD AFPC DETECTOR FIRST CHROMA AMPLIFIER R13 4K Q71 Q53 Q9 R1 300 1 R60 1.5K Q2 R17 2K Q54 Q50 R7 Q7 Q8 R6 500 R3 250 Q5 F R18 1K Q6 R12 1K D1 G SECOND CHROMA AMPLIFIER ACC DETECTOR SIGNAL SAMPLE AND HOLD R54 4K R43 2.5K J K Q72 Q35 Q69 Q24 Q70 Q36 R59 2K R78 1K Q65 H I R57 2K Q68 Q80 Q66 Q13 Q4 R9 500 R8 2.2K Q12 R19 12K R10 1.6K Q3 Q11 R16 12K C1 10pF 500 CHROMA INPUT R20 5K E R15 700 R14 2.1K C3 5pF R5 700 Q1 Q10 Q51 Q52 R11 1.3K R4 300 R2 700 B C D L M Q34 Q33 Q23 N O Q32 Q31 CHROMA OUTPUT P 15 CHROMA GAIN CONTROL Q67 16 R77 750 R42 8K R79 300 13 OVERLOAD DETECTOR ACC AMP. R44 5K Q22 Q25 R41 1K R40 330 D3 D1 Q29 R46 5K Q20 Q27 Z2 Z3 R48 2K KILLER AMP. ZENER REFERENCE R49 700 R51 2K Q28 R47 5K R45 220 Q30 R50 5K R52 1K Q47 Q R53 700 R55 3.5K R S T OVERLOAD DETECTOR 5 GROUND (SUBSTRATE) NOTE: Pin numbers refer to the PDIP Package. Resistance values are in ohms. 8-37 ZENER 14 REFERENCE CA3126 Schematic Diagram (Continued) AFPC FILTER 2 3 A CARRIER OUTPUT XTAL FILTER 6 7 BALANCED PHASE SHIFTER 8 BIAS SAMPLE AND HOLD LIMITER AMPLIFIER B C D Q59 R24 5K Q64 Q57 R27 3K R26 2K Q62 Q21 Q61 R28 390 Q18 R22 2K E R30 430 Q17 Q55 R29 390 Q58 Q16 Q56 R36 3K R3 4K Q15 R35 4.5K Q14 R25 1K F Q60 R23 8.2K R21 5K Q19 R32 750 G H I Q63 R37 2.2K R34 Q20 R33 1K R38 1.5K 1K R36 2.2K OSCILLATOR R39 500 D2 BIAS SAMPLE AND HOLD BALANCE - UNBALANCE TRANSLATOR J Q49 Q81 C2 12pF D6 POWER 12 SUPPLY +VCC K R64 4.9K R63 100 Q73 R69 2K R71 5K Q76 Q43 Q79 L Q44 Q45 M Q40 N 10 Q41 Q37 ACC FILTER Q46 O P 11 Q39 R72 2K R56 3.5K R62 1.8K Q75 R70 2.4K KEYER Q Q77 R61 2.94K R68 1.5K R73 2.5K Q74 Q38 R65 5K R67 1.5K Q42 R54 1K R66 2K R Q48 R74 1K Z1 D5 D4 R75 1.2K S T VOLTAGE REFERENCES 9 HORIZONTAL KEYING INPUT 8-38 CA3126 Circuit Description (Pin numbers refer to the DIP package.) The following paragraphs briefly describe the circuit operation of the CA3126 (shown in the Block Diagram and Schematic Diagram). A detailed description of the operation of various portions of the CA3126 is given in AN6247, “Application of the CA3126 Chroma-Processing lC Using Sample-and-Hold Techniques”. The chroma input is applied to Terminal 1 through the desired band-shaping network. A 2,450Ω resistor should be placed in series with Terminal 1 to minimize oscillator pickup in the first chroma amplifier. This amplifier supplies signals to the second chroma amplifier and to the ACC and AFPC detectors. The first chroma amplifier is gain-controlled by the ACC amplifier. A horizontal keying pulse is applied to Terminal 9. This pulse must be present to ensure proper operation of the oscillator circuit. The subcarrier burst is sampled during the keying interval in the AFPC detector. The error voltage, produced at Terminal 2 and proportional to the burst phase, is compared to the quiescent bias voltage at Terminal 3 by the sample-and-hold circuitry. This “compared” voltage controls the phase- shifting network in the phase-locked loop. The operation of the AFPC loop is independent of any external adjustments or voltages except for an initial capacitor adjustment to set the free-running frequency. The regenerated oscillator signal at Terminal 8 is applied internally to the AFPC and ACC detectors through +45 and -45-degree phase-shifter networks to establish the proper phase relationship for these detectors. The ACC detector, which also samples the burst during the keying interval, produces a correction voltage proportional to the burst amplitude. The correction voltage is compared to the quiescent bias level using sample-and-hold circuitry similar to that used in the AFPC portion of the circuit. The “compared” voltage is applied internally to the ACC amplifier and killer amplifier. Because the amplifier gains and killer threshold are determined by the ratios of the internal resistors, these functions are independent of external voltages or controls. 2. When the overload detector is used, a large resistor (nominally 47,000Ω) must be placed in series with Terminal 16 to set the required RC time constant. The same RC network series serves to set the killer time constant. 3. The setting of the free-running oscillator frequency requires the presence of the keying pulse. The free-running frequency will be erroneous if Terminal 1 is DC shorted during the setting operation because of the DC offset voltage introduced to the AFPC detector. 4. Care must be taken in PC board designs to provide reasonable isolation between the oscillator portion of the circuit (Terminals 6, 7, and 8) and the chroma input (Terminal 1). Overload Detector The overload detector accomplishes two purposes: 1. It prevents oversaturation due to low burst-to-chroma ratios. 2. It prevents overload conditions due to noise. Both of these conditions are discussed in more detail in AN6247. The extent to which the overload detector is used depends upon the individual receiver design goals. If greater than 0.5VP-P output is desired, the chroma output at Terminal 15 can be tapped to yield any desired degree of overload detector action. Chroma Gain Control The chroma gain control operates by varying the base bias on current source transistor Q25. To ensure proper temperature tracking of the chroma gain control, it is essential that the control be operated from a supply source derived from the reference voltage at Terminal 12. Because the control operates from a current source, chroma gain is much more predictable and far less temperature sensitive than controls that steer current by means of a differential amplifier. The typical chroma gain characteristic for the CA3126 is shown in Figure 1. CHROMA OUTPUT (% OF MAX. VALUE) Application Information The attenuated chroma signal is fed to the second chroma amplifier, where the burst is removed by keyer action. The killer amplifier, the chroma gain control, and the overload detector control the action of the second chroma amplifier, whose gain is proportional to the dc voltage at Terminal 16. The overload detector (Terminal 13) receives a sample of the chroma output (Terminal 15) and detects the peak of the signal. The detected voltage is stored in an external capacitor connected to Terminal 16. This stored voltage on Terminal 16 affects the gain of the second chroma in the same manner as the chroma gain control. TA = 25oC, CHROMA INPUT = 0.5VP-P 100 80 60 40 20 0 20 40 60 80 100 120 140 VOLTAGE AT TERMINAL 16 (% OF V12) General Considerations The block diagram shown is typical of the type of circuit used in the practical application of the CA3126. Several items are critical for proper operation of the circuit. 1. A series resistor of approximately 2,450Ω (or high source impedance) must be used at the chroma input, Terminal 1. This high impedance minimizes pickup of unbalanced currents, particularly of the subcarrier oscillator signal. FIGURE 1. CHROMA GAIN CONTROL Subcarrier Regenerator Oscillator The oscillator filter consists of a 3.579545MHz crystal, a 680Ω resistor, and a 10pF capacitor connected in series across Terminals 6 and 7. A 33pF capacitor, shunt connected from Terminal 7 to ground, rolls off higher order harmonics, thereby preventing oscillation at the crystal third-harmonic frequency. A 8-39 6 4 2 0 -2 130 10 120 5 PHASE 110 100 0 -5 AMPLITUDE -10 90 80 -50 -25 0 25 50 75 -15 100 TEMPERATURE (oC) FIGURE 4. AMPLITUDE AND PHASE VARIATIONS OF CHROMA OUTPUT vs TEMPERATURE -4 -300 400 -200 -100 0 100 200 300 OSCILLATOR FREE-RUNNING FREQUENCY (DEVIATION IN Hz FROM 3.579545MHz) FIGURE 2. STATIC PHASE ERROR Thermal Considerations The circuit of the CA3126 is thermally compensated to achieve the optimal operating characteristics over the normal operating temperature range of TV receivers. Figures 3 and 4 show the oscillator and chroma-output amplitudes and phases as a function of temperature (Terminals 8 and 15), respectively. Both the oscillator and chroma-output amplitudes and phases are measured relative to the chroma-input phase. The performance of the oscillator free-running frequency as a function of temperature is shown in Figure 5. All the temperature plots are characteristic of the test circuit with the indicated component types and values given. CHROMA INPUT = 0VP-P 100 50 0 -50 -100 -150 -50 -25 0 25 50 75 100 TEMPERATURE (oC) 110 CHROMA INPUT = 0.25VP-P, 3.58MHz CW SIGNAL 100 0 PHASE 90 AMPLITUDE 80 -5 70 60 -50 -25 0 25 50 TEMPERATURE (oC) 75 -10 100 OSCILLATOR PHASE (DEGREE OF DEVIATION FROM 25oC VALUE) OSCILLATOR AMPLITUDE (% OF 25oC VALUE) 15 CHROMA INPUT = 0.25VP-P , 3.58MHz CW SIGNAL CHROMA OUTPUT PHASE (DEGREE OF DEVIATION FROM 25oC VALUE) TA = 25oC 140 OSCILLATOR FREE-RUNNING FREQUENCY (DEVIATION IN Hz FROM 3.579545 MHz) STATIC PHASE ERROR (DEGREES) curve of the typical static phase error as a function of the freerunning oscillator frequency is shown in Figure 2. It should be noted that the slope of the curve determines the DC gain of the phase-locked loop, i.e., 40Hz per degree. CHROMA OUTPUT AMPLITUDE (% OF 25oC VALUE) CA3126 FIGURE 3. AMPLITUDE AND PHASE VARIATIONS OF OSCILLATOR OUTPUT vs TEMPERATURE 8-40 FIGURE 5. VARIATION OF OSCILLATOR FREE RUNNING FREQUENCY vs TEMPERATURE 125 CA3126 0.01µF 1µF 0.01µF +12V 0.01µF 5pF-25pF 2kΩ 0.01µF 680Ω INPUT FILTER 82pF 68pF L1 12µH L2 27µH 12 4 33pF 10pF 6 2 3 XTAL 7 FSC 3.579545MHz SUBCARRIER OUTPUT (CW) TYP. 0.5VP-P 56 pF 500Ω VCC AFPC DET/FILT. 2.4kΩ SUBCARRIER AMP VCO 8 0.01µF CA3126 COMPOSITE VIDEO/CHROMA INPUT 0.01µF 1 CHROMA/ BURST-GATE SWITCH FIRST CHROMA AMP ACC AMP 14 CHROMA O.L. DET KILLER AND GAIN CONT. ACC DET/FILT. 11.2V ZENER REF 10 5 0.01µF 11 1µF 2ND CHROMA AMP 13 16 15 BURST KEYER AMP 9 2kΩ 0.01µF >1VPEAK 0V BURST KEY PULSE 4µs (TYP), CENTERED ON BURST NOTE: For Subcarrier Regenerator, the second chroma amp is not used; Pins 13,14, and 15 are not connected and pin 16 is grounded. FIGURE 6. TYPICAL APPLICATION OF THE CA3126 AS A SUBCARRIER REGENERATOR 8-41