V21N3 - OCTOBER

October 2011
I N
T H I S
I S S U E
2-channel and 4-channel
pin-selectable I2C
multiplexer 11
high efficiency power
supply for Intel IMVP6/6+/6.5 CPUs 20
3A linear regulator easily
paralleled to spread power
and heat 24
LTspice IV update 36
frequency shifter for
isolated PWM control 40
Volume 21 Number 3
Fast, Accurate Step-Down DC/DC
Controller Converts 24V Directly to
1.8V at 2MHz
Bud Abesingha
The continuous march in electronics toward lower supply voltages
and higher load currents puts tremendous pressure on point-ofload DC/DC converters to maintain a fast pace of performance
improvements. For instance, a lower supply voltage means a
regulator must support a higher step-down ratio from a 12V
or 24V power rail while maintaining high efficiency. Regulation
accuracy also becomes more important as supply voltages
drop—and accuracy must be maintained in the
presence of parasitic IR drops and dynamic load
transients. EMI generated by switching converters
is also of concern, especially in RF applications.
Some applications require that their power supplies meet all of these stringent requirements: high power, high efficiency, high accuracy, high stepdown ratio, fast transient performance and low EMI—and that they do
it in a small footprint. The LTC®3833 is a high performance synchronous
step-down DC/DC controller that steps up to the challenge. Figure 1 shows
a typical application. The LTC3833 accepts an unregulated input voltage between 4.5V and 38V (40V abs max) and downconverts it to 0.67%
accurate output voltage between 0.6V and 5.5V (6V abs max).
Caption
Published September 2011 and now available. See page 2.
w w w. li n ea r.com
It features a 20ns minimum on-time, enabling a high step-down ratio
(high VIN to low VOUT) at high frequency (up to 2MHz), and its control architecture is primed for fast transient performance. The
LTC3833 is offered in 20-pin QFN (3mm × 4mm) and TSSOP packages with exposed pads for enhanced thermal performance.
(continued on page 4)
Linear in the News
In this issue...
COVER STORY
Fast, Accurate Step-Down DC/DC Controller
Converts 24V Directly to 1.8V at 2MHz
1
Bud Abesingha
ANALOG CIRCUIT DESIGN BOOK PUBLISHED
DESIGN FEATURES
2-Channel and 4-Channel Pin-Selectable I C
Multiplexer Features High Noise Margin, Capacitance
Buffering, Level Translation and Stuck Bus Recovery
2
Rajesh Venugopal
11
Low IQ, High Efficiency Dual Output Controllers for
Wide Ranging Input and Output Voltages
Jason Leonard
16
High Efficiency Power Supply for Intel
IMVP-6/IMVP-6+/IMVP-6.5 CPUs
Jian Li and Gina Le
24
8-Output Regulator Powers Applications Processors
Kevin Ohlson
27
3-Phase Synchronous Step-Down DC/DC
Controller with Stage Shedding™, Active Voltage
Positioning and Nonlinear Control for High
Efficiency and Fast Transient Response
Jian Li and Kerry Holliday
32
DESIGN IDEAS
What’s New with LTspice® IV?
Gabino Alonso
36
15A µModule® Regulator Solves Thermal Problems
by Converting 12V to 1V with High Efficiency
Eddie Beville
Analog Circuit Design is a comprehensive source book of circuit design
solutions that will aid systems designers with elegant and practical
design techniques that focus on common circuit design challenges.
20
3A Linear Regulator Can Be Easily Paralleled to
Spread Power and Heat
Todd Owen
The much-anticipated book, Analog Circuit Design: A Tutorial Guide to
Applications and Solutions was just published by Newnes, an imprint of
Elsevier Science & Technology Books. Edited by industry gurus, Bob Dobkin
and Jim Williams, the 960-page book covers a broad range of analog design
topics. This is the first time that such an extensive collection of application notes has appeared in one volume from Linear Technology engineers.
38
Solve Isolated Control Problems by Up-Shifting
Control Frequency with TimerBlox® PWM Generator
Tim Regan
40
product briefs
43
back page circuits
44
The book includes an extensive power management section, covering such topics as switching regulator design, linear regulator design,
high voltage and high current applications, powering lasers and illumination devices, and automotive and industrial power design. Other sections of the book span a broad range of analog design areas, including
data conversion, signal conditioning and high frequency/RF design.
Jim Williams wrote in the book’s Introduction, “The nature of analog circuit design is so diverse, the devices so sophisticated, and user
requirements so demanding that designers require (or at least welcome)
assistance. Ultimately, the use of analog ICs is tied to the user’s ability to
solve the problems confronting them. Anything that enhances this ability, in both specific and general cases, obviously benefits all concerned.”
Bob Dobkin stated in the book’s Foreword, “One of the best avenues for learning analog design is to use the application notes and information from companies
who supply analog integrated circuits. These application notes include circuitry,
test results, and the basic reasoning for some of the choices made in the design
of these analog circuits. They provide a good starting point for new designs.
“Since the applications are aimed at solving problems, the application
notes, combined with the capability to simulate circuits on Spice, provide a key learning pathway for engineers. The analog information in
most of these application notes is timeless and will be as valid twenty
years from now as it is today. It’s my hope that anyone reading this
book is helped through the science and art of good analog design.”
For more information, go to www.linear.com/designtools/acd_book.php. To
purchase Analog Circuit Design, click on the Elsevier link for a 30 percent
discount on the cover price, or go to the Amazon link at the bottom of the page.
2 | October 2011 : LT Journal of Analog Innovation
Linear in the news
Jim Williams’ workbench
COMPUTER HISTORY MUSEUM
EXHIBIT ON ANALOG &
JIM WILLIAMS OPENS
The Computer History Museum
in Mountain View, California has
announced a new exhibit opening this
month, “An Analog Life: Remembering
Jim Williams.” The exhibit, which
runs from October 15,
2011 until April 15,
2012, will focus on
how engineers work.
In their project overview for the exhibit,
the museum’s curator stated, “It is said
that we spend about one-third of our lives
at work. How we work is often reflected
in the way we organize our desks and
workspaces. Analog circuit guru Jim
Williams’ workbench tells us some things
about the way he worked. For example,
with its years-old strata of past circuits
embedded in a matrix of thousands of
overlapping components and still more
circuits, we see someone who worked
iteratively, drawing on past designs to continually invent new circuits and systems.
“Jim Williams’ workbench is an inspirational object that allows Computer
History Museum visitors to explore
engineering work styles, be inspired
by an extraordinary person and discover the world of analog circuitry and
its impact on today’s technology.”
the museum carefully transported from his
Linear Technology lab to the museum. The
display will include interpretive graphics, explaining various aspects of analog
design. In addition, the exhibit includes
video interviews with engineers who
worked closely with Jim Williams over the
years, plus video footage of his labs, both
at Linear Technology and at his home lab.
The “Analog Life” exhibit will launch
on October 15, with an evening event at
the Computer History Museum. Visitors
to the launch will have an opportunity to view the exhibit, hear a panel
discussion of analog experts discussing analog design and Jim Williams’
contributions, and attend a book signing of the new Analog Circuit Design
book with co-editor Bob Dobkin. For
more information about the exhibit, visit
computerhistory.org/highlights/analoglife.
The centerpiece of the exhibit is Jim
Williams’ engineering workbench, which
A video interview with Linear Technology co-founders Bob Swanson and Bob Dobkin
and CEO Lothar Maier can be found at www.linear.com/30yearinterview.
30 YEARS OF ANALOG INNOVATION
On September 26, Linear Technology commemorated three decades of innovation
in analog integrated circuits. When the
company was founded in September 1981,
at the dawn of the
digital revolution,
some questioned the
wisdom of founding
a company focused
purely on analog
technology. Since
then, the analog
market has grown 20-fold with Linear
contributing solutions to all corners of the
electronics industry. The dawn of digital
only increased the demand for analog.
Linear is consistently at the leading edge
of new electronic markets as they have
emerged. These include the PC revolution,
laptop and tablet computers, industrial
control and robotics, network infrastructure, cellular and satellite communications,
automotive electronics including advanced
displays, electronic braking and steering
and now the growth of the hybrid/electric
automotive segment, to name just a few. n
October 2011 : LT Journal of Analog Innovation | 3
The LTC3833 is a high performance synchronous
step-down DC/DC controller that regulates to 0.67%
output accuracy, operates up to 2MHz switching
frequency and has a 20ns minimum on-time.
(LTC3833, continued from page 1)
FAST TRANSIENT PERFORMANCE
AND CONSTANT FREQUENCY
EFFICIENCY ➘
The LTC3833 uses a new, sophisticated
controlled-on-time architecture—a
variant of the constant on-time control
architecture with the distinction that the
on-time is controlled so that the switching frequency remains constant over
steady state conditions under line and
load. This architecture takes advantage
of all the benefits of a constant on-time
controller, namely fast transient response
and small on-times for high step-down
ratios, while imitating the behaviors
of a constant frequency controller.
V IN
200kHz, 2.00μH
500kHz, 0.82μH
1MHz, 0.47μH
2MHz, 0.20μH
6V
91%
92%
91%
87%
12V
92%
92%
89%
84%
15V
92%
91%
87%
81%
24V
91%
88%
83%
73%
Table 1: Example of efficiency variation over input and frequency. Higher frequencies have lower efficiencies
but allow smaller component size for compact solutions. VOUT = 1.8V ILOAD = 10A.
The LTC3833 can respond to a load step
immediately without waiting until the next
switching cycle as in a conventional constant frequency controller. During a load
step, the LTC3833 increases its switching
frequency to respond faster and reduce
the droop on the output. Similarly, during
a load release, the LTC3833 reduces the
switching frequency in order to prevent
the input rail from charging the output
capacitor any further. Once the transient
condition subsides, the LTC3833 brings the
switching frequency back to the nominal
programmed value, or to the external
clock frequency if it is being synchronized.
INTVCC
VIN
VRNG
RPGD
100k
1.2MHz
CSS
0.01µF
RT
33.2k
VOUT
SENSE–
SENSE+
MODE/PLLIN
CITH1
220pF RITH
20k
CIN2
10µF
LTC3833
PGOOD
RUN
EXTVCC
RDCR
MT 1.1k
TG
SW
TRACK/SS
+
BOOST
DB
ITH
INTVCC
CVCC
4.7µF
SGND
PGND
VOSNS+
VOSNS–
VIN
6V TO 28V
VOUT
2.5V
5A
COUT1
100µF
MB
BG
RT
CIN1
47µF
35V
CDCR
0.1µF
L1
1µH
CB 0.1µF
INTVCC
FREQUENCY, INDUCTANCE
RFB1
10k
RFB2
31.6k
CIN1: KEMET T521X476M035ATE070
DB: DIODES INC. SDM10K45
L1: VISHAY IHLP2525CZ-1µH
MT, MB: VISHAY/SILICONIX Si4816BDY
4 | October 2011 : LT Journal of Analog Innovation
Figure 1. 28V input, 2.5V output, 5A, 1.2MHz
step-down converter. The high frequency
capabilities of the LTC3833 enable designs
that can squeeze into tight spaces.
The LTC3833’s low minimum off-time
of 90ns allows it to achieve high duty
cycle operation and thus avoid output
dropout when VIN is only slightly above
the required VOUT. The low minimum
off-time also factors into fast transient
performance. If the switching converter’s control loop is designed for
high bandwidth and high speed, the
minimum off-time of the LTC3833 does
not limit performance. That is, in a load
step condition, the time between consecutive on-time pulses can be as low
as 90ns for a high bandwidth design.
Figure 2 shows a low voltage, high current
application typical of a microprocessor
power supply where the LTC3833 responds
quickly to a 20A load step and release.
WIDE FREQUENCY RANGE FOR A
MULTITUDE OF APPLICATIONS
The LTC3833 is capable of a full decade
of switching frequency, from 200kHz
to 2MHz (programmed with an external
resistor on the RT pin). This wide range
allows the LTC3833 to meet the requirements of a wide variety of applications,
from low frequency applications that
require high efficiency, to higher frequency
design features
INTVCC
VIN
RPGD
100k
Figure 2a. 14V input, 1.5V output, 20A, 300kHz step-down converter. The
LTC3833 excels in low voltage, high current applications such as these,
which are typical of a microprocessor power supply. It can respond
quickly to sudden, high slew current requirements of the microprocessor.
LTC3833
PGOOD
The choice of operating frequency is a
tradeoff between efficiency and component size. Lower frequencies are more
efficient due to a reduction of switchingrelated losses in the converter. On the
other hand, lower frequencies require
larger inductors and capacitors to achieve
a given output ripple. At higher frequencies, smaller components can be used to
achieve the same output ripple, but at the
cost of efficiency. Table 1 illustrates the
trade-offs between efficiency and inductor size required to maintain output ripple
when the LTC3833 is used to generate a
1.8V output at several frequencies and
input voltages. As seen from the table,
switching losses are exacerbated at higher
frequencies and higher VIN, mainly due to
the higher VDS across the high side MOSFET.
+
VIN
4.5V TO 14V
CIN1
180µF
16V
VOUT
SENSE–
RUN
SENSE+
VRNG
TG
MODE/PLLIN
SW
EXTVCC
applications that require smaller solution size, to 2MHz applications that stay
above the AM radio band while being
able to downconvert from a high input
rail and deliver high output current.
CIN2
22µF
×2
L1
0.47µH
DB
CITH2 47pF
RITH 84.5k
RT 137k
TRACK/SS
RSENSE
1.5mΩ
BOOST
CSS 0.1µF
CITH1 220pF
MT
INTVCC
RFB2
15k
CB
0.1µF
INTVCC
RFB1
10k
CVCC
4.7µF
MB
BG
ITH
RT
SGND
COUT2
100µF
×2
+
VOUT
1.5V
20A
COUT1
330µF
2.5V
×2
PGND
VOSNS+
VOSNS–
CIN1: SANYO 16SVP180M
COUT1: SANYO 2R5TPE330M9
DB: CENTRAL CMDSH-3
The LTC3833’s wide frequency range also
helps minimize EMI interference from
the switching regulator. The switching
frequency can be chosen, and held over
line and load, such that the operating frequency and harmonics of the regulator fall
outside of the frequency band of the end
application. This allows the end application to easily filter out switching noise of
the DC/DC converter. Figure 3 shows an
example of a 5.5V application that operates
above the AM radio band (fSW > 1800kHz)
that could be used to power electronics
in an automotive infotainment system.
L1: PULSE PA0515.471NLT
MB: RENESAS RJK0330DPB
MT: RENESAS RJK0305DPB
The LTC3833 provides an additional
safeguard against EMI and noise interference by allowing it to be synchronized
to an external clock applied to the
MODE/PLLIN pin. This way, the end application has control over the DC/DC converter’s switching cycles and timing so
it does not interfere during critical time
periods in the application where sensitive signal processing might occur.
Figure 2b. The LTC3833 can respond quickly to sudden, high slew current requirements.
ILOAD
20A/DIV
ILOAD
20A/DIV
VOUT
50mV/DIV
VOUT
50mV/DIV
IL
20A/DIV
IL
20A/DIV
50µs/DIV
VIN = 12V
VOUT = 1.5V
LOAD TRANSIENT = 0A TO 20A
ILOAD
20A/DIV
VOUT
50mV/DIV
IL
20A/DIV
5µs/DIV
VIN = 12V
VOUT = 1.5V
LOAD STEP = 0A TO 20A
5µs/DIV
VIN = 12V
VOUT = 1.5V
LOAD RELEASE = 20A TO 0A
October 2011 : LT Journal of Analog Innovation | 5
High VIN, high frequency applications are susceptible
to minimum on-time limitations. Consider converting
28V down to 2.5V at 1.2MHz: this requires an on-time
of about 74ns, which the LTC3833 easily achieves.
HIGH STEP-DOWN RATIOS
AT HIGH FREQUENCY
28V down to 2.5V at 1.2MHz. This requires
an on-time of about 74ns, which the
LTC3833 easily achieves. In contrast, most
conventional current mode controllers
cannot achieve 74ns of on-time. To run
at high frequency, a conventional current mode controller would require two
stages of DC/DC conversion, with stage
one converting down to an intermediate voltage rail (e.g. 12V), and stage two
converting to the final required voltage.
This effectively doubles the solution
size and degrades overall efficiency.
The LTC3833 supports high side
MOSFET on-times down to 20ns. This is
important as lower minimum on-times
translate to higher possible step-down
ratios (VIN to VOUT) at a given switching
frequency. Higher switching frequencies require lower on-times to achieve
the same step-down ratio. Although the
LTC3833’s minimum on-time is a function
of VIN, VOUT and switching frequency (see
the data sheet at www.linear.com/3833
for details), it scales in the correct direction—the lowest minimum on-time is at
high VIN to low VOUT at high frequency.
At very low on-times (20ns–60ns), the
power MOSFETs’ own switching delays can
limit the minimum achievable on-time.
Appropriate care must be given to choose
power MOSFETs that have low turn-on and
turn-off delays, and more importantly, little or no imbalance between their turn-on
Of course, high VIN, high frequency
applications are susceptible to minimum
on-time limitations. Consider the application in Figure 1 that requires converting
and turn-off delays. For example, most
power MOSFETs’ turn-off delay is about
30ns greater than their turn-on delay. This
difference directly adds to the LTC3833’s
20ns minimum on-time for an effective
minimum on-time of about 50ns. Figure 4
shows a high step down ratio application
operating at 2MHz where the high side
power MOSFET has about a 12ns imbalance between turn-on and turn-off delays.
HIGH ACCURACY WITH
MINIMAL EFFORT
The LTC3833 features true remote differential output sensing. This enables
accurate regulation of the output even
in high power distributed systems with
heavy load currents and shared ground
planes. Remote differential sensing is critical for low output voltages, where small
offsets caused by parasitic IR drops in
Figure 3. 14V input, 5.5V output, 4A, 2MHz step-down converter. The LTC3833 can operate at switching frequencies above the AM radio
band (f > 1.8MHz) allowing the AM radio to sufficiently filter switching noise and EMI emanating from the step-down converter.
RPGD
100k
INTVCC
RDIV1
100k
RDIV2
26.1k
RUN
+
EXTVCC
VOUT
CIN1
47µF
35V
VIN
7V TO 14V
EXTERNAL
CLOCK
2V/DIV
SENSE–
TRACK/SS
RT
18.2k
CIN2
4.7µF
×2
LTC3833
VRNG
CSS
0.1µF
CITH1
220pF RITH
20k
VIN
PGOOD
MODE/PLLIN
SENSE+
MT
TG
SW
ITH
BOOST
CB 0.1µF
L1
1.2µH
DB
RT
SGND
INTVCC
BG
INTVCC
CVCC
4.7µF
RSENSE
10mΩ
CFF
22pF
MB
PGND
VOSNS+
VOSNS–
CIN1: KEMET T521X476M035ATE070
DB: DIODES, INC. SDM10K45
L1: WURTH 744313120
MT, MB: INFINEON BSC093N04LS
6 | October 2011 : LT Journal of Analog Innovation
RFB2
165k
RFB1
20k
VOUT
5.5V
4A
COUT1
22µF
×2
SW
5V/DIV
VOUT
20mV/DIV
VIN = 12V
VOUT = 5.5V
ILOAD = 2A
fSW = 2MHz
500ns/DIV
design features
RPGD
100k
INTVCC
VIN
PGOOD
VRNG
LTC3833
VOUT
MODE/PLLIN
RUN
EXTVCC
SENSE–
CSS
0.01µF
TRACK/SS
MT
L1
0.2µH
CB 0.1µF
BOOST
RSENSE
3mΩ
DB
CITH2
47pF
INTVCC
INTVCC
CVCC
4.7µF
BG
RT
18.2k
RFB2
165k
MB
RFB1
20k
PGND
VOSNS+
VOSNS–
RT
SGND
VIN
6V TO 24V
SENSE+
SW
ITH
CIN1
100µF
50V
EXTERNAL
CLOCK
2V/DIV
TG
CITH1
470pF RITH
8.66k
+
CIN2
10µF
×2
SW
10V/DIV
VOUT
1.8V
15A
COUT1
100µF
×2
VOUT
50mV/DIV
VIN = 24V
VOUT = 1.8V
ILOAD = 10A
fSW = 2MHz
L1: WURTH 744355122
MT, MB: INFINEON BSC093N04LS
CIN1: NICHICON UCJ1H101MCL1GS
DB: DIODES, INC. SDM10K45
100ns/DIV
Figure 4. 24V input, 1.8V output, 15A, 2MHz step-down converter. The LTC3833 can achieve very low on-times, which allows for a single-stage converter design.
Using a traditional controller with longer minimum on-times would require two or more stages, which would mean a costlier, bigger and less efficient design.
board traces can cost several percentage points in regulation accuracy.
Remote differential output sensing and
an accurate internal reference combine
to give the LTC3833 excellent output
regulation accuracy over line, load
and temperature, even when there are
offsets caused by trace losses on the
PC board. The LTC3833 is able to achieve
output accuracy figures of ±0.25% at
25°C, ±0.67% from 0°C to 85°C and ±1%
from –40°C to 125°C. Total accuracy
that accounts for line, load and remote
ground variations are ±1% from 0°C to
85°C and ±1.5% from –40°C to 125°C.
Figure 5 illustrates typical regulation
accuracy that could be expected from the
LTC3833 over line, load and temperature.
Conventional schemes for remote differential output sensing involves a unity
gain differential amplifier that senses
the remote output and remote ground
terminals directly (Figure 6). The output of this amplifier is then scaled down
through an external resistor divider
(which also programs the output voltage)
and fed back into the core controller. In addition to greater design effort
involved with this scheme, input and/
or output common mode range limitations of the unity gain amplifier can
reduce the range of output voltages where
remote differential sensing can be used.
Remote differential output sensing is
seamless in the LTC3833. It is simple to use,
requires minimal, if any, design effort,
and requires less area than other remote
sensing schemes. As in traditional feedback
sensing, the output is sensed through a
Figure 5. Typical regulation accuracy of the LTC3833 over line, load and temperature
0.2
0.1
0
–0.1
–0.2
0
5
10
15
20 25
VIN (V)
30
35
40
0.2
VIN = 15V
VOUT = 0.6V
VOUT NORMALIZED AT ILOAD = 4A
0.1
NORMALIZED ∆VOUT (%)
VOUT = 0.6V
ILOAD = 5A
VOUT NORMALIZED AT VIN = 15V
NORMALIZED ∆VOUT (%)
NORMALIZED ∆VOUT (%)
0.2
0
0
–0.1
–0.1
–0.2
VIN = 15V
VOUT = 0.6V
ILOAD = 0A
0.1 VOUT NORMALIZED AT TA = 25°C
0
2
6
4
ILOAD (A)
8
10
–0.2
–50 –25
0
25 50 55 100 125 150
TEMPERATURE (°C)
October 2011 : LT Journal of Analog Innovation | 7
The LTC3833 features true remote differential output sensing. This allows for
accurate regulation of the output even in high power distributed systems with
heavy load currents and shared ground planes. Remote differential sensing is
critical for low output voltages, where small offsets caused by parasitic IR drops
in board traces can cost several percentage points in regulation accuracy.
resistor divider network that is used to
program the output voltage. The LTC3833
takes this one step further by sensing the
output’s remote ground terminal where the
other end of the resistor divider network
is terminated. Therefore, output voltage
programming is similar to other feedbacksensing controllers, but with the advantage that the LTC3833 is able to correct
for board losses and offsets. The LTC3833
is invaluable when regulation accuracy
is required in high power, high current
distributed applications where multiple
systems share power and ground planes.
The LTC3833 is designed to handle
remote ground offsets as large as
±500mV with respect to local ground.
This includes the ability to soft-start
smoothly from an initial condition
state where the output of the regulator
is sitting 500mV below local ground.
VIN
CONVENTIONAL
REMOTE SENSE
CONTROLLER
VFB
TRACE PARASITICS
ON POWER AND GND
+
REMOTE
OUTPUT
EA
VREF
–
+
DA
(A = 1)
RFB2
–
RFB1
VIN
TRACE PARASITICS
ON POWER AND GND
REMOTE
OUTPUT
EA
VREF
–
RFB2
+
DA
(A = 1)
RFB1
–
Figure 6. Conventional remote differential sensing involves more design effort and board space than remote
sensing with the LTC3833.
8 | October 2011 : LT Journal of Analog Innovation
Programmable Current Limit
As a valley current mode controller, the
LTC3833 senses and controls the valley
point of the inductor current in order to
maintain output regulation. The inductor current is sensed with a sense resistor
in series with the inductor or by sensing
the inductor’s DCR voltage drop through
a RC network across the inductor. Either
way, the inductor current is continuously
sensed in all switching cycles, which allows
accurate and fast control of the output
current including output current limit.
The LTC3833 allows programming the
output current limit through the voltage
on VRNG pin, providing an extra degree
of freedom when choosing inductors
and sense resistors for a given application. The maximum current sense voltage
across the sense resistor or inductor’s
DCR can be programmed continually
from 30mV to 100mV. Figure 7 shows
the maximum current sense voltage
as a function of the VRNG voltage.
EXTV CC and INTV CC
LTC3833
+
OTHER FEATURES
The LTC3833 has an internal 5.3V low
dropout regulator that powers internal
control circuitry including the strong
high and low side gate drivers, and is
available to the outside world through
the INTVCC pin. The INTVCC regulator
can source a maximum of 50m A while
maintaining good regulation, so it can be
used in moderation as a supply to power
external circuitry or as a bias voltage
source. An external supply source (≥4.8V)
can be connected to EXTVCC pin to bypass
the internal regulator. This is especially
design features
The LTC3833 also features a continuously
programmable current limit, EXTVCC, selectable
pulse-skipping or forced continuous modes,
run enable, supply tracking and soft-start.
useful for high VIN applications where
the internal linear regulator becomes
less efficient. If the LTC3833 switching
regulator is generating a 5V output, it
can be connected back to EXTVCC (shown
in Figures 3 and 8). This scheme can
increase overall efficiency by 2%–3%
versus using the internal 5.3V regulator.
VSENSE(MAX) (mV)
100
80
60
40
20
Pulse-Skipping or Forced Continuous
Mode at Light Loads
0
The LTC3833 offers two modes of
operation at light loads to best meet
the requirements of a given application. For applications that require high
efficiency at light loads, the LTC3833
can be programmed for pulse-skipping
mode (by tying MODE/PLLIN pin to GND),
which allows the switching regulator to
transition into discontinuous conduction mode, thus increasing efficiency
by lowering the number of switching
0.6
0.8
EXTVCC
CSS
0.1µF
CITH1
220pF RITH
86.6k
RT
205k
CIN2
10µF
×3
VOUT
SENSE–
SENSE+
MT
TG
SW
TRACK/SS
BOOST
DB
ITH
SGND
CDCR
0.22µF
VOSNS–
RFB1
20k
Soft-Start and Tracking
The LTC3833 provides soft-start—either
from zero or prebiased output voltage
condition (Figure 9)—and external tracking capability through the TRACK/SS pin.
The soft-start time and ramp rate can
be programmed by a capacitor from
TRACK/SS pin to GND. This capacitance
and the 1µ A current source out of the
TRACK/SS pin determine the soft-start time
100
VOUT
5V
8A
+
PGND
VOSNS+
2
COUT1
330µF
6.3V
×2
PULSE-SKIPPING
MODE
95
FORCED
CONTINUOUS
MODE
90
85
80
75
RFB2
147k
CIN1: NICHICON UCJ1H101MCL1GS
COUT1: SANYO 6TPE330MIL
DB: DIODES INC. SDM10K45
Figure 8. 38V input, 5V output, 8A, 200kHz step-down converter. The
LTC3833 offers two modes of operation at light loads: pulse-skipping
mode for higher efficiency or forced continuous mode for constant
switching frequency.
VIN
7V TO 38V
MB
BG
RT
CIN1
100µF
50V
COUT2
100µF
×2
INTVCC
CVCC
4.7µF
INTVCC
RDCR
5.9k
+
L1
6µH
CB 0.1µF
10Ω
1.8
On the other hand, for applications that
require predictable EMI performance and
LTC3833
MODE/PLLIN
1.6
cycles. The downsides of pulse-skipping
mode are the variable switching frequency (dependent on load current) and
a slightly higher output voltage ripple.
VIN
PGOOD
RUN
1.2 1.4
VRNG (V)
EFFICIENCY (%)
RPGD
100k
1
Figure 7. The LTC3833 provides a programmable
current limit.
INTVCC
VRNG
value constant switching frequency or
require very accurate regulation at light
loads, the LTC3833 can be programmed
for forced continuous mode (by tying
MODE/PLLIN pin to INTVCC). In forced
continuous mode, the LTC3833 maintains
the programmed switching frequency
even at no load, but sacrifices light
load efficiency in the process. Figure 8
shows an example of the differences in
efficiency between the two modes.
120
70
L1: COOPER HC2LP-6R0
MB: INFINEON BSC035N04LS
MT: INFINEON BSC035N04LS
VIN = 12V
VOUT = 5V
0.1
1
LOAD CURRENT (A)
10
October 2011 : LT Journal of Analog Innovation | 9
The LTC3833 acts quickly and effectively to protect
the output and external components of the switching
regulator if the output encounters overvoltage,
overcurrent and short-circuit conditions.
and ramp rate. The output reaches its final
programmed value when TRACK/SS voltage
reaches 0.6V, the internal reference voltage
for the LTC3833. Alternatively, an external
ramp can drive the TRACK/SS pin in order
to track the output of the switching regulator to the external ramp, providing better control of power-up and power-down
conditions of the switching regulator.
The programmed current limit prevents
overcurrent conditions and allows the
output to droop down when the output
current exceeds current limit. During
short-circuit conditions, the LTC3833 forces
foldback current limiting, where the current limit is progressively lowered to about
a quarter of the programmed current limit
for a hard short at the output (Figure 10).
Run Enable
Overvoltage conditions are handled by forcing the low side power
MOSFET to turn on to discharge
the overvoltage at the output.
The LTC3833 provides a dedicated enable/
disable function through the RUN pin. The
LTC3833 self-enables when the RUN pin is
left floating. It is disabled or shut down by
forcing RUN to GND. The quiescent current of the LTC3833 in shutdown is 15µ A.
The LTC3833 is enabled when RUN is pulled
greater than 1.2V, which is an accurate,
well-controlled threshold. This allows
the RUN pin to be programmed as an
input undervoltage lockout if desired
by programming a resistor divider from
VIN to RUN to GND. The RUN pin can also
sink about 35µ A of current, allowing it
to be pulled directly up to VIN through
a sufficiently large pull-up resistor.
CONCLUSION
The LTC3833 is a synchronous stepdown DC/DC controller that can meet
the demands of high current, low
voltage applications while remaining versatile enough to fit a wide range
of step-down DC/DC applications.
The LTC3833 provides a power good
function through the PGOOD pin, which
is an open drain output that is resistively
pulled up to a logic level voltage (or
INTVCC) externally. If the output is within
±7.5% of the programmed value, then
PGOOD is high, indicating power is good.
It provides the usual set of features such as
soft-start, power good and fault protection commonly available with step-down
controllers. It also adds some invaluable
extras, including remote output sensing,
programmable current limit, external
clock synchronization and EXTVCC . It
also features high performance specs,
including 0.67% output accuracy, switching frequency (up to 2MHz) above the
AM radio band, high step-down ratios
through a 20ns minimum on-time,
and quick response time to transient
conditions in the line and load. n
Figure 9. The LTC3833 can smoothly start up into a
prebiased output.
Figure 10. During a short circuit at the output,
the LTC3833 reduces the output current to 1/4 of
programmed current limit.
Power Good and Fault Protection
The LTC3833 acts quickly and effectively
to protect the output and external components of the switching regulator if the
output encounters overvoltage, overcurrent and short-circuit conditions.
SHORTCIRCUIT
TRIGGER
RUN
2V/DIV
SHORT-CIRCUIT
REGION
VOUT
1V/DIV
VOUT
500mV/DIV
TRACK/SS
200mV/DIV
IL
10A/DIV
ILOAD
12A
*
ILOAD
12A
VOUT PRE-BIASED TO 0.75V
INDUCTOR CURRENT FOLDBACK
DURING SHORT-CIRCUIT
VIN = 12V
VOUT = 1.5V
10 | October 2011 : LT Journal of Analog Innovation
10ms/DIV
VIN = 12V
1ms/DIV
VOUT = 1.5V
* INDUCTOR CURRENT REACHES
CURRENT LIMIT BEFORE FOLDBACK
AND DURING SHORT-CIRCUIT RECOVERY
design features
2-Channel and 4-Channel Pin-Selectable I2C Multiplexer
Features High Noise Margin, Capacitance Buffering, Level
Translation and Stuck Bus Recovery
Rajesh Venugopal
The inherent simplicity of I2C and SMBus 2-wire protocols
has made them a popular choice for communicating vital
information in large systems. Both standards employ
simple open-drain pull-down drivers with resistive or
current source pull-ups. Nevertheless, several practical
problems arise as systems grow in complexity.
The first problem with large systems is
that devices with hard-wired I2C addresses
require address expansion to prevent
conflicts. Second, noise causes glitches that
can be interpreted as legitimate clock or
data transitions, compromising data reliability. Third, I2C devices can cause the bus
to stick low. Finally, timing specifications
are increasingly difficult to meet, and clock
frequencies are limited by the equivalent
bus capacitance, which increases with
system size and complexity. The LTC4312
and LTC4314 pin-selectable 2-channel
and 4-channel I2C multiplexers with bus
buffers address these issues with a number of powerful features (see Table 1).
Since these two devices share the same
features, except for the number of channels, this article focuses on the LTC4314.
An upstream I2C bus (SDAIN, SCLIN) can be
connected to any combination of downstream buses through the LTC4314’s bus
buffers and multiplexer switches by driving the ENABLE pins of the desired output
buses high. Multiple devices having the
same address can be placed on different
buses and isolated using the ENABLE pins,
thereby achieving address expansion.
The buffers provide capacitance isolation between the upstream bus and the
downstream buses, allowing for partitioning of the bus capacitance. In single
supply systems, the buffers regulate the
bus up to 0.33 • VCC , providing a large
logic low noise margin. Rise time accelerators (RTAs) of appropriate strength
can be activated to overcome bus capacitance limitations, reduce rise time and
allow for higher switching frequencies
even when operating with heavy loads.
The LTC4314 is compatible with the
I2C standard and Fast Mode, SMBus and
PMBus specifications. Stuck bus recovery
circuitry disconnects the upstream bus
from downstream buses when SDA and
SCL have not been simultaneously high at
least once in 45ms, freeing the upstream
bus to resume communications. The recovery circuitry also attempts to convince
Table 1. Key features of the LTC4312 and LTC4314
FEATURE
BENEFITS
2- and 4-Pin Selectable
Downstream Buses
• Maximum flexibility of bus configurations
I 2 C Buffers
Selectable V IL
Level Translation
Rise Time Accelerators
(RTAs)
Disconnection and Recovery
from Stuck Bus
• Address expansion when used as a MUX
• Breaks up bus capacitance, which allows large I 2 C compliant systems to be built, by keeping the capacitance of
each section < 400pF
• High logic low noise margin up to 0.33 • V CC
• Selectable RTA Operating voltage range
• Provides I 2 C communication between 1.5V, 1.8V, 2.5V, 3.3V and 5V buses
• Reduce rise time
• Allow larger bus pull-up resistors for better noise margin
• Selectable RTA pull-up current strength
• Free masters to resume upstream communications
• Generates up to to 16 clock pulses and a stop bit on the stuck buses to convince the stuck device to release high
October 2011 : LT Journal of Analog Innovation | 11
The LTC4314 is compatible with the I2C standard and
Fast Mode, SMBus and PMBus specifications. Stuck
bus recovery circuitry disconnects the upstream bus
from downstream buses when SDA and SCL have
not been simultaneously high at least once in 45ms,
freeing the upstream bus to resume communications.
the stuck device to release high by generating up to 16 clock pulses and a stop
bit on the enabled downstream buses.
SCLOUT
2V/DIV
(AC-COUPLED)
Finally, cards can be hot-swapped into
and out of the LTC4314’s I2C output buses
provided that the channel being hotswapped has been disabled. The LTC4314’s
operating voltage range is VCC from 2.9V to
5.5V, VCC2 from 2.25V to 5.5V and bus
voltages from 2.25V to 5.5V. The LTC4314
can level translate down to 1.5V and
1.8V buses under certain conditions if
RTAs are disabled on the low voltage bus.
SCLIN
2V/DIV
500ns/DIV
Figure 1. The LTC4314 transmitting a noisy 400kHz
I2C signal applied to SCLIN. The SCLOUT1 waveform
tracks SCLIN when SCLIN is a logic low. During
logic highs, noise on SCLIN above 0.33 • VMIN is not
propagated to SCLOUT.
HIGH BANDWIDTH BUFFERS
IMPROVE NOISE MARGIN AND SPEED
WHILE MAINTAINING LOW OFFSET
the high bandwidth buffers do not limit
the rise rate of the bus, permitting them
to stay on to a higher bus voltage.
High noise margin is obtained by leaving
the LTC4314 buffers on until both the input
and output bus voltages are > 0.33 • VMIN,
where VMIN is the lower of the VCC and
VCC2 voltages. This is possible because
As seen in Figure 1, when a noisy 400kHz
square wave signal is applied to SCLIN,
the SCLOUT1 waveform tracks SCLIN when
3.3V
C1
0.01µF
R1
10k
R2
10k
the SCLIN voltage is < 0.33 • VMIN, and
releases high when the SCLIN voltage
is > 0.33 • VMIN . The low offset makes the
SCLOUT1 waveform almost identical to the
SCLIN waveform for voltages < 0.33 • VMIN .
No output glitches occur as the input
crosses the VIL level of 0.33 • VMIN ,
as seen in the SCLOUT1 waveform.
2.5V
R4
10k
VCC2
VCC
R5
10k
C2
0.01µF
SCLIN
I2C
DEVICE
SDAIN
ENABLE1
ENABLE1
SCLOUT1
ENABLE2
ENABLE2
SDAOUT1
ENABLE3
ENABLE3
ENABLE4
ENABLE4
LTC4314
ACC
SCLOUT4
DISCEN
FAULT
FAULT
SDAOUT4
GND
• • •
R3
10k
ADDRESS = 1001 000
• • •
3.3V
I2C
DEVICE
5V
R6
10k
R7
10k
I2C
DEVICE
ADDRESS = 1001 000
Figure 2. The LTC4314 in a nested addressing and level shifting application where a device on the upstream
3.3V bus communicates with devices on the 2.5V and 5V downstream buses. Only buses 1 and 4 are shown for
simplicity.
12 | October 2011 : LT Journal of Analog Innovation
As the buffers are disconnected when
both input and output bus voltage
are > 0.33 • VMIN, any noise applied to
the logic high state on one side is not
propagated to the other side as long as
that bus voltage does not drop below
0.33 • VMIN . This is seen in Figure 1
where the logic high state of SCLOUT1
is unaffected by noise on SCLIN.
Designers who are in control of the entire
I2C system can set the LTC4314 to operate
at frequencies of up to 1MHz by adjusting
the RC load on the bus and using strong
RTAs (see Table 2). The LTC4314’s highto-low propagation delay tPDHL is always
positive, on the order of 100ns. Depending
on bus loading conditions on the upstream
and downstream sides of the LTC4314, the
low-to-high propagation delay tPDLH of the
LTC4314 can be either positive or negative.
For systems operating at high frequencies (>400kHz) designers should quantify
the tPDLH -tPDHL skew in their SDA and
SCL pathways and ensure data set-up and
hold times are acceptable on all buses.
design features
BACKPLANE
SHMC #1
3.3V
R1
10k
VCC
SDAIN
µP
3.3V
VCC2
R2
10k
LTC4314 #1
ENABLE1
ENABLE2A
ENABLE2
SDAOUT2
ENABLE3A
ENABLE3
SDAOUT3
ENABLE4A
ENABLE4
IPMB-B
SDA1
SDAOUT4
•
GND
•
•
•
•
• • •
3.3V
VCC2
VCC
•
SDAIN
LTC4314 #6
ENABLE1
SDAOUT1
ENABLE22A
ENABLE2
SDAOUT2
ENABLE23A
ENABLE3
SDAOUT3
ENABLE24A
ENABLE4
SDAOUT4
3.3V
•
ENABLE21A
R3
10k
IPMB-A
SDA24
SDA1
IPMB-B (×24)
• • •
GND
•
ACC
IPMB-A
SDA1
•
ENABLE1A
SDAOUT1
ACC
Figure 3. The LTC4314 used in a radially
connected telecommunications system
in a 6 × 4 arrangement. The ENABLE
pins of only one shelf manager are
high at any given time. Only the SDA
pathway is shown for simplicity.
FRU #1
3.3V
FRU #24
SDA24
SHMC #2
(IDENTICAL TO SHMC#1)
IPMB-A (×24)
SDA1
• • •
IPMB-B (×24)
IPMB-B
SDA24
SDA24
LEVEL TRANSLATION AND
NESTED ADDRESSING
The circuit shown in Figure 2 illustrates
level translation and nested addressing
features of the LTC4314. The LTC4314
can level translate the input and output
buses to voltages between 2.25V (1.5V and
1.8V under some circumstances) and
5.5V. In Figure 2 the LTC4314 translates a
3.3V input to 5V and 2.5V outputs. Only
downstream buses 1 and 4 are shown
for simplicity. Each output channel has a
dedicated ENABLE pin select that allows
the master to communicate independently with slave devices with identical
I2C addresses provided that only one
downstream bus is enabled at a time.
RADIALLY CONNECTED
TELECOMMUNICATIONS
APPLICATION
Figure 3 shows the LTC4314 used in a
radially connected telecommunications
application such as ATCA. Two shelf
managers (SHMCs) are used to communicate with slave I2C devices for redundancy. Each shelf manager can have as
many LTC4314s as required depending on
the number of boards in the system and
the desired radial/star configuration (6
× 4 in Figure 3). The ENABLE pins inside
only one shelf manager are asserted high
at any time. Since the LTC4314 can be
cascaded with other Linear Technology
bus buffers, up to 24 FRUs with Linear
Technology bus buffers on their edges
can be plugged into the backplane.
PARALLELING LTC4314s TO ACHIEVE
MULTIPLEXING OF MORE BUSES
Multiple LTC4314s can be connected
in parallel to perform higher order
multiplexing. Figure 4 shows a 1:8
multiplexer using two LTC4314s.
INTEROPERABILITY WITH
NONCOMPLIANT I 2C DEVICES
The high buffer turn-off voltage of the
LTC4314 ensures interoperability with
noncompliant I2C devices that drive
a high VOL > 0.4V. This is shown in
Figure 5 where a noncompliant device
on channel 4 drives a high VOL = 0.6V.
The buffer turn-off voltage is 1.089V,
yielding a logic low noise margin
of > 0.4V at both the input and output.
October 2011 : LT Journal of Analog Innovation | 13
3.3V
C1
0.01µF
R1
10k
3.3V
R2
10k
R4
10k
VCC2
VCC
R5
10k
C2
0.01µF
SCLIN
I2C
DEVICE
SDAIN
Figure 4. Paralleling LTC4314 devices to realize a 1:8 multiplexer
ENABLE1
SCLOUT1
SCLOUT1
ENABLE2
ENABLE2
SDAOUT1
SDAOUT1
ENABLE3
ENABLE3
ENABLE4
ENABLE4
LTC4314
3.3V
• • •
• • •
ENABLE1
ACC
R3
10k
DISCEN
FAULT
5V
R6
10k
R7
10k
SCLOUT4
SCLOUT4
SDAOUT4
SDAOUT4
generated, whichever comes first. After the
final clock pulse, a stop bit is generated to
reset the bus for further communication.
GND
3.3V
A rising edge on one or more ENABLE pins,
after all ENABLEs have been taken low,
is required to reestablish connection
between the input and output. Doing
this also clears the FAULT flag. The master can wait for the fault condition to
clear (FAULT released high), either on
its own or through the 16 clock pulses
issued by the LTC4314, before toggling
the LTC4314’s ENABLE pins, or it can do
so preemptively before the fault has
cleared to reestablish connection. The
master can then take appropriate action
to clear the stuck low condition.
3.3V
C3
0.01µF
VCC2
VCC
R9
10k
R10
10k
C4
0.01µF
SCLIN
SDAIN
ENABLE1
SCLOUT1
SCLOUT5
ENABLE6
ENABLE2
SDAOUT1
SDAOUT5
ENABLE7
ENABLE3
ENABLE8
ENABLE4
LTC4314
3.3V
R8
10k
• • •
• • •
ENABLE5
ACC
DISCEN
FAULT
HOT SWAP™ APPLICATION
I/O cards can be hot swapped into the
downstream buses of an LTC4314 residing
on a live backplane as shown in Figure 6.
Before plugging or unplugging an I/O
card, care must be taken to disable the
corresponding output channel so that the
card does not disturb any I2C transaction
that may be in progress. The connection
to the inserted card must be enabled only
when all ongoing transactions on the
bus have completed and the bus is idle.
5V
R11
10k
R12
10k
SCLOUT4
SCLOUT8
SDAOUT4
SDAOUT8
GND
3.3V
C1
0.01µF
Figure 5. The LTC4314 in operation with a
noncompliant I2C device that drives a VOL
= 0.6V. The buffer turn-off voltage is 1.089V
yielding a logic low noise margin > 0.4V.
R2
10k
3.3V
R4
10k
VCC2
VCC
C2
0.01µF
R5
10k
SCLIN
SDAIN
ENABLE1
ENABLE1
SCLOUT1
SCLOUT1
ENABLE2
ENABLE2
SDAOUT1
SDAOUT1
ENABLE3
ENABLE3
ENABLE4
ENABLE4
LTC4314
3.3V
• • •
• • •
14 | October 2011 : LT Journal of Analog Innovation
R1
10k
I2C
DEVICE
STUCK BUS DETECTION AND
RECOVERY
Occasionally, slave devices get confused
and get stuck in a low state. The LTC4314
monitors the enabled output buses to
detect if clock and data have been simultaneously high at least once in 45ms. If
this condition is not detected, the LTC4314
asserts the FAULT flag low. If DISCEN is
Figure 7 shows the waveforms during an SDAOUT1 stuck low and recovery
event. After the 45ms timeout period has
elapsed, the FAULT flag is asserted low and
the input and output sides are disconnected. This causes SDAIN to release high.
tied high, the LTC4314 also disconnects
the input and output sides and generates
clock pulses on the enabled downstream
buses in an attempt to free the stuck bus.
Clocking is stopped when data releases
high or 16 clocks have been
ACC
R3
10k
DISCEN
FAULT
GND
5V
R6
10k
R7
10k
SCLOUT4
SCLOUT4
SDAOUT4
SDAOUT4
NON-COMPLIANT
I2C DEVICE
VOL = 0.6V
design features
Table 2. ACC control of the rise time accelerator current
IRTA and buffer turn-off voltage VIL,RISING(typ)
ACC
I RTA
V RTA(TH)
V IL,RISING
Low
Strong
0.8V
0.6V
Hi-Z
3mA
0.4 • V MIN
0.33 • V MIN
High
None
N/A
0.33 • V MIN
3.3V
C1
0.01µF
R1
10k
R2
10k
3.3V
ENABLE1
SCLOUT1
ENABLE2
ENABLE2
SDAOUT1
ENABLE3
ENABLE3
ENABLE4
ENABLE4
DISCEN
FAULT
R7
10k
IO CARD
GND
ENABLE1
5V/DIV
CONNECT AT RISING EDGE OF ENABLE1
RECOVERS
SDAOUT1
5V/DIV STUCK LOW>45ms
CONNECTOR
I2C
DEVICE
SDAOUT4
For heavily capacitive buses with low to
moderate noise, tie ACC low to meet system
rise times and maximize SCL switching frequency. Tying ACC low provides
the strongest pull-up current over the
maximum voltage range. For higher
noise immunity, leave ACC open or tie
it to 0.5 • VCC to set the buffer VIL to
SDAIN
5V/DIV
R6
10k
SCLOUT4
FAULT
DISCONNECT
AT TIMEOUT
5V
• • •
LTC4314
into the buses making them rise at a typical rate of 40V/µs. The RTA current and
the buffer turn-off voltage are selected
by the ACC setting as shown in Table 2.
RISE TIME ACCELERATORS
The rise time accelerators (RTAs) of the
LTC4314 can be configured either in
current source mode (ACC open), slew
limited switch mode (ACC grounded),
or disabled (ACC high). In the current
source mode the RTAs source a constant
3m A current into the bus. In the slew
controlled switch mode, the RTAs turn on
in a controlled manner and source current
IO CARD
ACC
R3
10k
I2C
DEVICE
• • •
• • •
If automatic stuck bus disconnection is not desired, this feature can be
disabled by tying DISCEN low. In this
case, during a stuck bus event, the
FAULT flag is asserted low, but no stop
bit or clock generation occurs and the
input and output sides stay connected.
C2
0.01µF
SDAIN
ENABLE1
3.3V
Clock pulses are generated on SCLOUT1.
SDAOUT1 releases high before 16 clock
pulses have been generated. Clock pulsing is stopped and a stop bit is generated. When the ENABLE1 pin is toggled,
a connection is established between the
input and output and a driven low level
on SDAOUT1 is propagated to SDAIN.
R5
10k
SCLIN
I2C
DEVICE
Figure 6. The LTC4314 in a Hot Swap™ application where
cards are being plugged in to or unplugged from the outputs.
The corresponding ENABLE pin must be driven low before a
card can be plugged or unplugged and should only be driven
high when the other buses are idle.
R4
10k
VCC2
VCC
DRIVEN LOW
SCLOUT1
5V/DIV
AUTOMATIC CLOCKING
1ms/DIV
Figure 7. Bus waveforms during a SDAOUT1 stuck
low and recovery event
CONNECTOR
0.33 • VMIN and to get 3m A of RTA current. The 3m A RTA current is enough to
meet the 1µs standard mode I2C rise time
requirement (100kHz operation) for bus
capacitances up to 690pF with DC bus
pull-up currents < 4m A. Tie ACC high if no
acceleration is needed. To selectively disable RTAs only on the outputs, ground VCC2
and either ground ACC or leave ACC open.
CONCLUSION
The LTC4314 and LTC4312 are pin-selectable I2C multiplexers that solve practical design issues associated with large
I2C bus systems by providing capacitance
buffering, nested addressing and level
translation. These parts maintain a low
offset and high logic low noise margin
up to 0.33 • VCC . Their high bandwidth
buffers and integrated RTAs allow for
operation at frequencies up to 1MHz
with guaranteed stability from zero to
1.2nF capacitive loads. They also disconnect and recover buses when buses are
stuck low and allow I/O cards to be hot
swapped into and out of live systems. n
October 2011 : LT Journal of Analog Innovation | 15
Low IQ, High Efficiency Dual Output Controllers for
Wide Ranging Input and Output Voltages
Jason Leonard
The LTC3857 and LTC3858 are versatile low quiescent
current (IQ), 2-phase dual output synchronous buck
controllers that are ideal for applications demanding
high efficiency and minimal power loss over a broad
range of load currents, from virtually no load to many
amps. They feature a wide input supply range of 4V
to 38V (40V abs max) that covers a broad range of
battery chemistries and power sources. Each output
can be set from 0.8V to 24V (28V abs max).
RB1
215k
CF1
15pF
RA1
68.1k
C1
1nF
LTC3857
SENSE1+
PGOOD2
SENSE1–
PGOOD1
VFB1
RITH2 27k
CITH2A 100pF
RA2
44.2k
CF2
39pF
MB1
L1
3.3µH
C2
1nF
RSENSE1
5mΩ
CB1
0.1µF
BOOST1
ITH1
+
MT1
TG1
COUT1
150µF
VOUT1
3.3V
5A
COUT1A
100µF
D1
CSS1 0.1µF
CSS2 0.1µF
CITH2 680pF
100k
SW1
RITH1 15k
CITH1 820pF
LOW I Q EXTENDS
BATTERY RUN TIME
INTVCC
100k
BG1
CITH1A 150pF
The LTC3857 and LTC3858 are pin-compatible parts that differ only slightly,
most notably in short-circuit operation
and at light load operation. These differences are discussed below and summarized in Table 1. A “-1” version of each
is available with slightly fewer features
(Table 2). The LTC3857/LTC3858 are also
mostly pin compatible with the popular
LTC3827/LTC3826 family of low IQ controllers. Figure 1 shows a typical application circuit in which the LTC3857 is used
to convert a widely varying car battery
voltage to two well regulated outputs.
VIN
TRACK/SS1
INTVCC
ILIM
PHASMD
CLKOUT
PGND
PLLIN/MODE
SGND
TG2
EXTVCC
RUN1
BOOST2
RUN2
FREQ
TRACK/SS2
SW2
ITH2
BG2
CIN2
47µF
×2
CINT
4.7µF
+
CIN1
47µF
VIN
4.5V TO 38V
D2
MT2
CB2
0.1µF
L2
7.2µH
RSENSE2
8mΩ
+
MB2
VOUT2
8.5V
3A
COUT2
68µF
10µF
In many applications, one or more supplies remain active at all times, often in
a standby mode where little or no load
current is drawn. In these “always-on”
systems, the quiescent current of the
power supply circuit represents the vast
majority of the current drawn from the
input supply (battery). Having a low
IQ power supply is crucial to extending
battery run times. In Burst Mode® operation, the LTC3857 draws only 50µ A when
one output is active and only 65µ A when
both outputs are enabled, while the
LTC3858 draws 170µ A when one output is
active and only 300µ A when both outputs
are enabled. Both devices consume only
8µ A when both outputs are shut down.
VFB2
SENSE2–
SENSE2+
RB2
422k
COUT1: SANYO 4TPE220MF
COUT1A: TAIYO YUDEN JMK325BJ107MM-T
COUT2: SANYO 10TPC68M
D1, D2: CENTRAL SEMI CMDSH-4E
L1: SUMIDA CDEP105NP-3R2MC-88
L2: SUMIDA CDEP105NP-7R2MC-88
16 | October 2011 : LT Journal of Analog Innovation
MT1, MT2, MB1, MB2: INFINEON BSZ097NO4LS
Figure 1. High efficiency dual output
3.3V/8.5V step-down converter. The 8.5V
output follows V when V is less than 8.5V.
design features
In “always-on” systems, the quiescent current of the power
supply circuit represents the vast majority of the current
drawn from the input supply (battery). Having a low IQ
power supply is crucial to extending battery run times.
CURRENT SENSING, CURRENT LIMIT
AND SHORT-CIRCUIT PROTECTION
Table 1. Key differences between the LTC3857 and LTC3858
FEATURE
LTC3857
LTC3858
Quiescent Current
(One Channel On)
50µA
170µA
Quiescent Current
(Both Channels On)
65µA
300µA
Burst Mode Operation
Lowest Ripple
Highest Midrange Efficiency
Short-Circuit Protection
Cycle-by-Cycle Current Limiting
with Current Foldback
Cycle-by-Cycle Current Limiting with
Current Foldback and
Optional Short-Circuit Latchoff
Output Voltage Tracking
During Start-Up
Yes, Tracking or Soft-Start
(TRACK/SS Pin)
No, Soft-Start Only (SS Pin also Used
for Short-Circuit Latchoff Timer)
The LTC3857 and LTC3858 operate similarly
to each other in forced continuous and
pulse-skipping mode. There are differences
in Burst Mode operation, however. The
LTC3857 is optimized for the lowest quiescent current and for relatively low ripple.
The LTC3858 is optimized for the highest
efficiency over a broad range of load current. This means the LTC3857 transitions
to constant frequency operation (with
lower ripple) at a lower load current than
the LTC3858, while the LTC3858 maintains
higher efficiency (with higher ripple) at
intermediate light loads (Figures 4 and 5).
The LTC3858 has an additional feature
that further protects during a short-circuit
event. The SS pin can be used as a shortcircuit timer. If the short circuit lasts long
enough, the output “latches off” and stops
100
100
90
90
80
70
80
BURST MODE
OPERATION
EFFICIENCY (%)
The PLLIN/MODE pin is used to program
one of three modes at low load currents—
Burst Mode operation, pulse-skipping
mode, or forced continuous mode. Forced
continuous mode maintains constant
frequency operation from no load to full
load, at the expense of light load efficiency. Burst Mode operation is the most
efficient mode at light loads, albeit with
slightly higher ripple and features the
lowest quiescent current. Pulse-skipping
mode is somewhat of a compromise,
maintaining very low ripple and moderate
efficiency at light loads. Figures 2 and 3
show the efficiencies in these three modes.
EFFICIENCY (%)
OPERATING MODES
The LTC3857/LTC3858 each uses a peak
current mode architecture. A high speed
rail-to-rail differential current sense comparator constantly monitors the voltage
across a current sense element, either a
sense resistor or the inductor’s DC resistance (as derived from an R-C network).
The peak sense voltage is set by the threestate ILIM pin (fixed on the “-1” version).
If a short circuit occurs, current limit
foldback reduces the peak current to minimize the dissipation in the power components. Foldback is disabled during start-up
for predictable tracking or soft-start.
60
PULSESKIPPING
MODE
50
40
30
20
70
60
PULSESKIPPING
MODE
50
40
30
20
10
0
0.1m
BURST MODE
OPERATION
FORCED CONTINUOUS MODE
1m
10m
0.1
ILOAD (A)
1
10
Figure 2. Efficiency of in the circuit of Figure 1 using
the LTC3857. Efficiencies are shown for the three
modes of operation (forced continuous, pulseskipping, and Burst Mode operation). At heavier
loads, the efficiency is independent of the mode.
10
0
0.1m
FORCED CONTINUOUS MODE
1m
10m
0.1
ILOAD (A)
1
10
Figure 3. Efficiency of in the circuit of Figure 1
using the LTC3858. Note that the efficiencies in
forced continuous and pulse-skipping modes are
essentially identical to the LTC3857’s in Figure 2—
only Burst Mode operation is different at light to
intermediate loads.
October 2011 : LT Journal of Analog Innovation | 17
switching. The latch can only be reset by
cycling the RUN pin or by cycling the input
power (VIN). This latchoff feature can be
defeated by connecting a resistor between
the SS and INTVCC pins. The two channels
of the LTC3858 operate independently;
i.e., a short-circuit latchoff on one channel does not affect the other channel.
OTHER IMPORTANT FEATURES
The FREQ pin is used to set the switching
frequency. Tying this pin to ground selects
350kHz while tying it to INTVCC selects
535kHz. Connecting a single resistor
from this pin to ground allows the frequency to be set anywhere from 50kHz
to 900kHz. A short minimum on-time
of 95ns allows low duty cycle operation even at high frequencies. The maximum 99% duty cycle capability allows
low dropout operation for low input/
high output voltage applications.
An internally compensated phase-locked
loop (PLL) enables the LTC3857/LTC3858 to
synchronize to an external clock source
(applied to the PLLIN/MODE pin) from
75kHz to 850kHz. When synchronized,
the LTC3857/LTC3858 operates in forced
continuous mode to maintain constant
frequency operation independent of
the load current. When the external
clock is absent or momentarily interrupted, the LTC3857/LTC3858 operates at
the frequency set by the FREQ pin. The
internal PLL filter is prebiased to a voltage corresponding to this free-running
frequency. When an external clock is
detected, the PLL is enabled. Since the
PLL filter is prebiased and barely has to
18 | October 2011 : LT Journal of Analog Innovation
LTC3858
IL
2A/DIV
FORCED CONTINUOUS MODE
IL
2A/DIV
PULSE SKIPPING MODE
IL
2A/DIV
BURST MODE OPERATION
VIN = 12V
VOUT = 3.3V
ILOAD = 100µA
2µs/DIV
2µs/DIV
Figure 4. Inductor current ripple at 12V to 3.3V at 100µA load current. The LTC3857 and LTC3858 differ only in
Burst Mode operation.
charge or discharge during this transition, synchronization is achieved quickly,
with only small changes in frequency
and minimal output voltage ripple.
The MOSFET drivers and control circuits
are powered by INTVCC , which by default
is generated from an internal low dropout (LDO) regulator from the main input
supply pin (VIN). The strong gate drivers
with optimized dead time control provide
high efficiency at heavy loads. To reduce
power dissipation due to MOSFET gate
charge losses and improve efficiency at
high input voltages, a supply between
5V and 14V (abs max) can be connected to
Figure 5. Comparison of the LTC3857 and LTC3858
efficiency when configured for Burst Mode operation
(PLLIN/MODE pin connected to ground) for the
Figure 1 circuit. At very light to virtually no load, the
LTC3857 has the lowest power loss due to its low IQ.
At intermediate loads, the LTC3858 is more efficient,
at the expense of ripple.
100
90
80
EFFICIENCY (%)
Although both current foldback and
latchoff provide additional levels of
protection during a short-circuit event,
the LTC3857/LTC3858 is fundamentally
protected by its current mode architecture. The current comparator is always
active, meaning switching cycles can be
gracefully skipped as needed to keep the
inductor current under control at all times.
LTC3857
LTC3858
70
LTC3857
60
50
40
30
20
10
0
0.1m
1m
10m
0.1
ILOAD (A)
1
10
the EXTVCC pin. When a supply is detected
on EXTVCC , the VIN LDO is disabled
and another LDO between EXTVCC and
INTVCC is enabled. EXTVCC is commonly
connected to one of the output voltages generated by the LTC3857/LTC3858.
The LTC3857/LTC3858 features a RUN pin
for each channel. RUN enables the output
and the INTVCC supply. The LTC3857 has
a TRACK/SS pin for each channel, which
acts as a soft-start or allows the output to
track an external reference (e.g., another
supply). The LTC3858 has a dual-function
SS pin for each channel. SS is used for
soft-start (like the TRACK/SS pin on the
LTC3857 but without tracking) and also as
the optional short-circuit latchoff timer.
IDEAL FOR AUTOMOTIVE
APPLICATIONS
The LTC3857, in particular, is well suited
for automotive applications, including
navigation, telematics and infotainment
systems. The wide input voltage range is
high enough to protect against double
battery and load dump transients, while
low enough to allow continuous operation during cold crank and engine start.
The ultralow 50µ A quiescent current
is ideal for always-on supplies that are
enabled even when the ignition is off.
The wide output voltage range supports
the higher voltage rails often used for
audio systems, CD/DVD players, and disk
design features
RB1
698k
CF1
10pF
C1
1nF
RA1
49.9k
SENSE1+
PGOOD2
SENSE1–
PGOOD1
VFB1
CITH1 3300pF
MB1
L1
6µH
CSS1 0.1µF
VIN
TRACK/SS1
INTVCC
ILIM
PHASMD
CLKOUT
PGND
PLLIN/MODE
SGND
TG2
EXTVCC
RUN1
BOOST2
RUN2
FREQ
SS2
SW2
ITH1
ITH2
BG2
VFB1
VFB2
C2
1nF
SENSE2–
SENSE2
COUT1
22µF
16V
10µF
16V
VOUT
12V
12.5A
D1
LTC3857
SS1
Figure 6. 2-phase single output application. Multiple
LTC3857/LTC3858 controllers can be cascaded to
drive a single output with up to 12 power stages
operating out-of-phase for very high power
applications.
MT1
TG1
ITH1
RSENSE1
5mΩ
CB1
0.47µF
BOOST1
VOUT
The LTC3857/LTC3858 is normally configured for two independent outputs
that run 180° out-of-phase. Operating
the channels out-of-phase minimizes the required input capacitance.
However, the LTC3857/LTC3858 can also
be configured with both power stages
100k
SW1
RITH1 2.94k
MULTIPHASE SINGLE OUTPUT
APPLICATIONS
INTVCC
BG1
CITH1A 68pF
drives. The 99% duty cycle capability
provides a low dropout voltage for these
rails when the battery voltage dips.
100k
CIN
10µF
50V
CINT
4.7µF
10µF
50V
VIN
19V TO 28V
D2
MT2
CB2
0.47µF
L2
6µH
RSENSE2
5mΩ
COUT2
22µF
16V
MB2
10µF
16V
COUT1, COUT2: SANYO 16T0C22M
D1, D2: CMDSH-4E
L1, L2: SUMIDA CDEP106-6ROM
MT1, MT2, MB1, MB2: INFINEON BSZ097NO4LS
+
driving a single output. Figure 6 depicts
a 19V–28V input supply generating a
regulated 12V/150W output. In this configuration, both channels’ compensation
(ITH), feedback (VFB), enable (RUN) and
soft-start (TRACK/SS or SS) pins are tied
together. Since the channels operate outof-phase, the effective switching frequency
is doubled, minimizing the required
input and output capacitance and voltage ripple, while allowing for even faster
transient response. The LTC3857/LTC3858
provides inherently fast, accurate
Table 2. Key differences between the standard and “-1” parts
LTC3857/LTC3858
LTC3857-1/LTC3858-1
Current Sense Voltage
Adjustable 30mV/50mV/75mV
(ILIM pin)
Fixed 50mV
Power Good Output
Voltage Monitor
Independent Monitors for Each Channel
(PGOOD1 and PGOOD2 pins)
Monitor for Channel 1 Only
(PGOOD1 pin)
CLKOUT/PHASMD Pins for
Three or More Phases
Yes
No
Package
5mm × 5mm QFN
28-Lead Narrow SSOP
cycle-by-cycle current sharing due to its
peak current mode control architecture.
The LTC3857/LTC3858 can also be
used in designs with three or more
phases. The CLKOUT pin can drive the
PLLIN/MODE pin of other controllers,
while the PHASMD pin adjusts the relative phases of each controller. This allows
3-, 4-, 6- and 12-phase operation.
CONCLUSION
The LTC3857 and LTC3858 are nearly
pin-compatible parts, ideal for converters
requiring high efficiency over a broad load
range, from no load to full load. Their low
quiescent current extends operating life
in battery-powered systems. They each
regulate two separate outputs from 0.8V to
24V from inputs of 4V to 38V. The short
minimum on-time and 99% duty cycle
capability allows high frequency operation
from very low to very high duty cycles.
The LTC3857 and LTC3858 incorporate
these features and more in 5mm × 5mm
QFN and 28-lead narrow SSOP packages. n
October 2011 : LT Journal of Analog Innovation | 19
High Efficiency Power Supply for Intel
IMVP-6/IMVP-6+/IMVP-6.5 CPUs
Jian Li and Gina Le
The LTC3816 is a single-phase synchronous step-down DC/DC switching regulator
controller that complies with Intel Mobile Voltage Positioning (IMVP)-6/6+/6.5 specifications.
It uses a constant-frequency voltage mode architecture with a leading edge modulation
topology, allowing extremely low output voltages and very fast load transient response.
The LTC3816 satisfies all of the IMVP-6, IMVP-6+ and IMVP-6.5 requirements, including
7-bit VID code, start-up to a preset boot voltage, differential remote output voltage sensing
with programmable active voltage positioning (AVP), IMON output current reporting, power
optimization during sleep state and fast or slow slew rate sleep state exit. It is suitable for a
wide range of input voltages from 4.5V to 36V and output voltages up to 1.5V. The LTC3816
is available in 38-pin thermally enhanced eTSSOP and 5mm × 7mm QFN packages.
Figure 1. An IMVP-6.5 converter using
temperature-compensated inductor
DCR sensing
10k
14k
8.25k
ISENN
15nF
15nF
5.1k
21k
ITCFB
IMAX
ITC
ISENP
RPTC
1000pF
VRON
LFF
PREIMON
IMON
IMON
LTC3816
VRON
22pF
2.2nF
470pF
22pF
VID0
VID1
VID2
VID3
VID4
VID5
VID6
COMP
VIN
EXTVCC
SS
INTVCC
DPRSLPVR
20 | October 2011 : LT Journal of Analog Innovation
BG
VID0
BSOURCE
MODE/SYNC
RFREQ
VID1
VID6
VID2
VID5
VID3
PWRGD 1.9k
1.1V
3.3V
GND
VID4
VIN
4.5V TO 24V
+
NTC
0.1µF
BOOST
VFB
CSLEW
CLKEN# 1.9k
CLKEN#
TG
SERVO
10pF
56Ω
2.55k
SW
VCC(SEN)
12k
0.1µF
VRTT#
VRTT#
PWRGD
VSS(SEN)
10k
6.98k
DB
5V
QT
100Ω
CVIN
100Ω
L
+
QB
PTC
CBULK
CCER
4.7µF
CBULK: 3 × SANYO 2TPF330M6 (330µF)
CCER: 20 × 10µF + 2 × 1µF
CIN: 2 × SANYO OS-CON 35SVPD47M + 2 × 10µF
DB: CMDSH-4E
L: IHLP-5050CE-01 (0.33µH, DCR = 1.3mΩ)
NTC: MURATA NCP18XH103
PTC: MURATA PRF18BC471QB1RB
QB: 2 × RENESAS RJK0330DPB
QT: RENESAS RJK0305DPB
VCC(CORE)
ILOAD(MAX) = 27A
design features
The LTC3816 meets all of Intel’s IMVP-6, IMVP-6+ and IMVP-6.5 specifications in a small
5mm × 7mm 38-pin QFN. With strong gate drivers and short dead-time, the LTC3816
offers high efficiency solutions over a wide input voltage range. Its leading edge modulation
topology allows very small duty cycle operation and ultrafast transient response.
0.78
100
MEASURED RESULT
VCC_CORE(DC MAX)
VCC_CORE(DC MIN)
0.76
80
EFFICIENCY (%)
VOUT (V)
0.74
0.72
0.7
INTEL’S SPEC
0.68
70
60
50
40
30
20
0.66
0.64
PULSE SKIPPING MODE
fSW = 400kHz
90
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.5V
10
0
5
10
15
20
25
30
0
0
10
1
ILOAD (A)
100
ILOAD (A)
Figure 2. Load regulation with -3mV/A slope
Figure 3. Efficiency with 12V input
AN IMVP-6.5 CONVERTER WITH
4.5V~24V INPUT AND 27A OUTPUT
dead-time, the LTC3816 offers a highly
efficienct solution, as shown in Figure 3.
Figure 1 shows an IMVP-6.5 application
using temperature-compensated inductor DCR sensing. The output voltage is
programmed by a 7-bit VID code. With
temperature-compensated inductor
DCR sensing, the LTC3816 provides an
accurate –3mV/A AVP slope over temperature as shown in Figure 2. With
strong integrated FET drivers and short
The LTC3816’s leading edge modulation topology allows ultrafast transient
response to meet Intel’s stringent requirements. As shown in Figure 4, no undershoot other than AVP is observed during
a load step-up test, easily meeting Intel’s
specifications. Moreover, the LTC3816
incorporates a line feedforward function
to compensate for changes in the line
VOUT = 1V
VOUT
50mV/DIV
voltage and to simplify the loop compensation. The LTC3816 feedback loop is
also capable of dynamically changing the
regulator output to different VID DAC voltages as shown in Figure 5. Upon receiving
a new VID code, the LTC3816 regulates to
its new potential with a programmable
slew rate selected to prevent the converter from generating audible noise.
During start-up, the output voltage is
charged to VBOOT first, according to Intel’s
VRON
1V/DIV
VOUT = IOUT • RDROOP
VBOOT
VOUT
1V/DIV
VOUT
200mV/DIV
VOUT = 0.5V
IOUT
20A/DIV
CLKEN
5V/DIV
PWRGD
5V/DIV
20µs/DIV
Figure 4. Transient response with 20A load step
200µs/DIV
Figure 5. Output voltage transition from 0.5V to 1.0V
in dynamic VID mode
2ms/DIV
Figure 6. Start-up test with preset boot voltage 1.1V
October 2011 : LT Journal of Analog Innovation | 21
The LTC3816 includes an onboard current limit circuit, so that the peak inductor
current can be sensed via inductor DCR or a discrete sense resistor. The
LTC3816 current limit architecture allows momentary overcurrent events for a
predefined duration. The LTC3816 also provides input undervoltage lockout,
output overvoltage protection and PWRGD and overtemperature flags.
IMVP specification. As shown in Figure 6,
VBOOT is 1.1V in IMVP-6.5 and 1.2V in
IMVP-6. Once the output voltage reaches
VBOOT, the CLKEN# output goes low and
the output voltage transitions to the
voltage programmed by the VID code.
ISENN
ITCFB
IMAX
ITC
ISENP
IMON
INTVCC
RPTC
VRON
LTC3816
VRON
22pF
6800pF
470pF 22pF
COMP
VIN
EXTVCC
SS
INTVCC
DPRSLPVR
Figure 7. A dual-channel IMVP-6 converter with
44A output using RSENSE sensing configuration
BG
VID0
BSOURCE
MODE/SYNC
RFREQ
VID1
VID6
VID2
VID5
VID3
P
BOOST
VFB
CSLEW
CONCLUSION
CLKEN#
TG
SERVO
10pF
C
SW
VCC(SEN)
12k
V
VRTT#
PWRGD
VSS(SEN)
10k
3k
LFF
PREIMON
The LTC3816 includes an onboard current limit circuit, so that the peak inductor current can be sensed via inductor
DCR or a discrete sense resistor. The
LTC3816 current limit architecture
allows momentary overcurrent events
for a predefined duration. The LTC3816
also provides input undervoltage lockout, output overvoltage protection and
PWRGD and overtemperature flags.
22 | October 2011 : LT Journal of Analog Innovation
2.43k
22pF
Figure 7 demonstrates that for high current applications, multiple LTC3816s can
be paralleled to provide more power.
The current sharing performance is very
good in both static and dynamic operation conditions, as shown in Figure 8.
The LTC3816 meets all of Intel’s IMVP-6,
IMVP-6+ and IMVP-6.5 specifications in
a small 5mm × 7mm 38-pin QFN. With
strong gate drivers and short dead-time,
the LTC3816 offers high efficiency solutions
over a wide input voltage range. Its leading edge modulation topology allows very
small duty cycle operation and ultrafast
transient response. The LTC3816 provides
high efficiency, high power density, and
high reliability solutions for embedded
computing, mobile computers, Internet
devices and navigation displays. n
10.2k
1000pF
GND
VID4
VID6
VID5
VID4
VID3
VID2
VID1
VID0
CBULK: 4 × SANYO 2TPF330M6 (330µF)
CCER: 32 × 10µF + 2 × 1µF
CIN: 3 × SANYO OS-CON 35SVPD47M + 2 × 10µF
DB: CMDSH-4E
L: IHLP-5050CE-01 (0.33µH, DCR = 1.3mΩ)
PTC: MURATA PRF18BC471QB1RB
QT: RENESAS RJK0305DPB
QB: 2 × RENESAS RJK0330DPB
RSENSE: PANASONIC ERJM1WTF1M0U (1mΩ)
5V
design features
The LTC3816 feedback loop is also capable of dynamically changing the
regulator output to different VID DAC voltages. Upon receiving a new VID
code, the LTC3816 regulates to its new potential with a programmable
slew rate selected to prevent the converter from generating audible noise.
VIN
4.5V TO 24V
100Ω
100Ω
2.43k
1000pF
1.1V 3.3V
511Ω
511Ω
56Ω
3k
1000pF
VRTT#
PWRGD
DB
PREIMON
LTC3816
CLKEN#
L
CVIN
+
QB
CBULK
PTC
–
CCER
L
QT
QB
PTC
+
VCC_CORE
ILOAD(MAX) = 54A
4.7µF
DB
VCC(SEN)
TG
0.1µF
SERVO
BOOST
5V
VFB
VIN
EXTVCC
COMP
INTVCC
SS
BG
4.7µF
BSOURCE
MODE/SYNC
RFREQ
DPRSLPVR
VID6
400kHz
SQUARE WAVE
10k
10pF
12k
6800pF
22pF
22pF
470pF
CSLEW
VID0
VID1
VID5
VID4
INTVCC
VSS(SEN)
SW
RSENSE
RSENSE
IMON
RPTC
VRON
PWRGD
+
0.1µF
ITC
VRTT#
QT
22pF
LFF
3.3V
1000pF
ITCFB
IMAX
ISENP
1.9k
CLKEN# 1.9k
ISENN
10.2k
VID2
GND
VID3
VOUT
200mV/DIV
IL1
10A/DIV
Figure 8. Current sharing performance
for a dual-channel IMVP-6 converter
IL2
10A/DIV
20µs/DIV
October 2011 : LT Journal of Analog Innovation | 23
3A Linear Regulator Can Be Easily Paralleled to
Spread Power and Heat
Todd Owen
One drawback to using a traditional linear
regulator is that the minimum output
voltage is limited to the reference voltage of the regulator. Another is that it is
not easy to increase the available output
current or spread power dissipation by
paralleling devices. To distribute the load
between multiple regulators, one must
either add large ballast resistors, which
incur load regulation errors, or balance
LT3083
IN
VCONTROL
50µA
+
–
the load with complicated schemes of
input sense resistors and op amp loops,
which inevitably cancels out the promise
of simplicity originally offered by using
the ostensibly simple linear regulator.
But what if the voltage reference is
thrown out and replaced with a precision current source? The resulting device
is deceptively simple, as shown in the
block diagram of Figure 1; a precision
current source connects to the noninverting input of an amplifier and the output
drives a large NPN pass element and connects to the inverting input to give unity
gain. This small change to the venerable
linear regulator device yields enormous
gains in versatility and performance.
Now, in this new architecture, connecting each of the SET pins together when
paralleling regulators provides a common
reference point for all the error amplifiers,
making it possible to balance any deviceto-device offset variations with mere
milliohms of ballast. Suddenly it is easy to
spread power dissipation between as many
devices are needed, and likewise scale the
output current as necessary. The beauty
of this architecture is that a single resistor generates the reference point for all
of the regulators, whether one, ten or one
hundred regulators are used. Additionally,
the architecture allows zero resistance to
equal zero output—there is no longer a
fixed reference voltage to limit the bottom
end of the usable output voltage range.
BENEFITS OF A NEW ARCHITECTURE
The LT®3080 1.1A linear regulator was
the first linear regulator to use a precision current source architecture, making it
possible to produce high current, surface
mount power supplies by paralleling any
number of LT3080s. The LT3083 follows in
the footsteps of the LT3080 with similar
high performance specifications, but with
an increased 3A output current capability. The performance advantages offered
by this new architecture are numerous.
Frequency Response and Load
Regulation are Fixed
With traditional linear regulators, gain
and bandwidth change as the output
voltage is changed via resistor divider.
Bypassing the feedback pin of the regulator affects loop response. Load regulation is not a fixed value, but a fixed
percentage of the output as the resistor
divider gains up any voltage deviation.
Furthermore, reference voltage noise is
gained up by the same resistor divider.
50.5
50.4
50.3
SET PIN CURRENT (µA)
The basic 3-terminal
regulator has been a building
block in designer tool kits
for over thirty years without
any significant change to
its basic architecture. Using
a fixed voltage reference,
a resistor divider boosts
the output voltage to the
desired level. These are easy
to use devices, hence their
popularity, but there are
some inherent downsides
to this simple architecture.
50.2
50.1
50.0
49.9
49.8
49.7
49.6
49.5
–50 –25
SET
Figure 1. LT3083 block diagram
24 | October 2011 : LT Journal of Analog Innovation
0
25 50 75 100 125 150
TEMPERATURE (°C)
OUT
Figure 2. Reference current temperature
characteristics
design features
Suddenly it is easy to spread power dissipation between as
many devices are needed, and likewise scale the output current
as necessary. The beauty of this architecture is that a single
resistor generates the reference point for all of the regulators,
whether one, ten or one hundred regulators are used.
the device from damage during shortcircuit conditions and thermal limiting
keeps the part safe during conditions
of excessive power dissipation.
LT3083
IN
VCONTROL
+
–
OUT 10mΩ
Top Notch AC Characteristics
SET
LT3083
IN
VIN
4.8V TO 28V
VCONTROL
+
–
OUT
10µF
10mΩ
VOUT
3.3V
6A
SET
Using a current source and unity-gain
buffer eliminates these downsides. Since
the error amplifier is always in unity
gain, frequency response does not change
as a function of output voltage or with
the use of bypassing across the reference
point. Load regulation is now a fixed
value, regardless of output voltage. Since
bypassing does not affect loop response,
two noise sources can be eliminated: the
reference current noise and resistor shot
noise are quieted using a single capacitor.
This leaves only the error amplifier noise
at the output, and again, that stays at a
fixed level, no matter the output voltage.
Top Notch DC Characteristics
DC characteristics of the LT3083 are the
same as the original LT3080. The LT3083
separates out the collector of the NPN pass
device to minimize power dissipation.
Load regulation is typically below 1mV for
the error amplifier, and nearly immeasurable on the 50µ A reference current. Line
22µF
33.2k
Figure 3. Paralleling regulators for
higher current and heat spreading
regulation for the reference current is less
than 0.0002%/V, and is typically 2µV/V for
the error amplifier offset. Temperature
characteristics of the reference current
are excellent, typically staying within
0.2% across the full operating junction
temperature range, as shown in Figure 2.
The LT3083 also provides all of the protection features that Linear Technology
parts are known for: current limit with
safe operating area protection protects
Figure 4. High current reference buffer
LT3083
IN
VIN
VCONTROL
+
–
INPUT
LT1019
GND
OUTPUT
SET
C1
1µF
OUT
VOUT*
C2
10µF
Don’t think that the AC characteristics
of the LTC3083 were sacrificed in an
effort to achieve high DC performance.
Transient response is excellent with as
little as 10µF of output capacitance. Small
ceramic capacitors can be used without
the addition of ESR. Using a bypass capacitor across the reference resistor provides
a slow-start function; the output voltage follows the RC time constant created
by the SET resistor and bypass capacitor.
Paralleling devices also provides advantages in noise performance. Paralleling
multiple LT3083 regulators lowers the output noise in the same way that paralleling
n op amps lowers noise by a factor of √n.
APPLICATIONS
The LT3083’s deceptively simple architecture and high performance parameters make it powerful building block
for applications beyond the basic linear
regulator. It can be easily paralleled to
increase output current and spread heat.
Actively driving the SET pin is perfectly
acceptable; the low offset and high output
current allow for highly accurate reference
supplies at high power levels. Digitally
programmable supplies are achieved by
driving the SET pin with a DAC. Accurate
current sources are realized without
tremendous difficulty. The possibilities are
only limited by the creativity of the user.
*MIN LOAD 0.5mA
October 2011 : LT Journal of Analog Innovation | 25
The LT3083 is easily configured as a 2-terminal
current source, simply by adjusting the ratio of the
external resistors and adding compensation.
Figure 5. Digitally programmable power supply
Easy 2-Terminal Current Source
LT3083
IN
VIN
VCONTROL
GAIN = 4
150k
SPI
LTC2641
150k
+
–
450k
–
+
OUT
SET
VOUT
10µF
LT1991
Parallel Regulators Increase Current
and Spread Heat
Figure 3 shows how to parallel multiple
LT3083s to increase output current and
spread heat. Note the minimal ballast
needed to balance the load amongst
the regulators. It’s possible to produce
quiet and accurate high current surface
mount supplies simply by adding more
LT3083s. Power dissipation is spread
evenly across the paralleled regulators,
but thermal management is still necessary. With as little as 0.5V drop across the
regulator, a 3A load translates to 1.5W of
power dissipation, pushing the thermal
capabilities for surface mount designs.
High Current Reference Buffer
Creating a high current reference buffer takes very little effort, as shown in
Figure 4. In this circuit, an LT1019-5
output connects to sink the 50µ A reference current of the regulator. This reference provides 0.2% accuracy across
temperature, or 10mV. With a maximum
offset voltage of 4mV in the LT3083,
output accuracy stays within 0.3%. The
accuracy of the reference current in
the LT3083 is not a factor in the output
tolerance, and there are no resistors to
present potential tolerance variations.
26 | October 2011 : LT Journal of Analog Innovation
Digitally Programmed Output
Programming the output voltage
digitally simply takes the addition of a
DAC to drive the SET pin. Figure 4 highlights how a DAC programs the LT3083
output to anywhere from zero to over
16V within 1.5LSB. In this circuit, an
LTC2641-12 using a 4.096V reference drives
the SET pin of the LT3083 through the
LT1991 (configured for a gain of four).
Again, the tight specifications of the
LT3083 allow for such excellent performance. Keep in mind that the minimum
load current requirement must be met
when operating at minimum output
voltages—less than 500µ A loading is
required when operating at low input
voltages, much less than traditional linear
regulators that require 5 to 10m A.
Current sources can be very difficult to
implement in certain applications. Some
must be ground referenced, others must
be referenced to a positive rail, while the
most difficult designs require floating,
2-terminal devices. The LT3083 is easily
configured as a 2-terminal current source,
simply by adjusting the ratio of the external resistors and adding compensation as
shown in Figure 5. The current source can
be ground referenced, referenced to a positive rail or fully floating without concern.
CONCLUSION
Hiding behind the simple architecture
shown in the block diagram of the LT3083
is a high performance, highly versatile,
groundbreaking building block device.
The LT3083 combines the architectural
leap forward of the LT3080, excellent
AC and DC characteristics and increased
current to easily solve problems that a
traditional 3-terminal or low dropout
regulator cannot touch. It can be used for
supplies that operate all the way down
to zero volts, paralleled for high current
and heat spreading, or driven dynamically.
High current linear power supplies are
now available for surface mount boards
without sacrificing performance. n
CCOMP*
IN
LT3083
*CCOMP
R1 ≤ 10Ω 10µF
R1 ≥ 10Ω 2.2µF
VCONTROL
Figure 6. 2-terminal current source
+
–
SET
R1
20k
IOUT =
1V
R1
design features
8-Output Regulator Powers Applications Processors
Kevin Ohlson
The market for applications processors, the integrated core/
memory/video/UI function chips used in smartphones,
tablets, netbooks and automobile infotainment systems,
is one of the fastest growing segments in electronics
today. A single applications processor IC, such as one
from Freescale, Marvell or an in-house custom processor,
is packed with functions and requires independent power
supplies for its core, I/O, memory and peripherals. The
challenge is producing all those rails in limited space, at
high efficiency, from a wide range of power inputs—a
tablet, for instance, requires power conversion from
USB, automotive battery and its built-in Li-ion battery.
The LTC3589 serves applications processor power needs with eight regulated
outputs that support processor core and
I/O voltage levels, SRAM, memory, low
power standby, other peripheral circuits
and system voltage levels. The LTC3589’s
eight supplies are completely independent, but they can be easily sequenced
with simple pin strapping. Likewise, the
LTC3589 simplifies overall power system design by integrating a number of
important control features, including:
EIGHT INDEPENDENT VOLTAGE
REGULATORS IN A SINGLE IC
While the features built into the LTC3589
certainly aid system design and optimization, it is designed foremost to output
eight independent, voltage-regulated
outputs. The LTC3589 contains a combination of LDO and switching regulators with output current capabilities
from 25m A to 1.6A, with voltage output
Figure 1. Eight power rails take less than 500mm2 of
board real estate.
levels from less than 1V to 5V. Four of the
outputs feature I2C -controlled DAC references for dynamic voltage scaling.
The integrated low power, 25m A, LDO can
supply circuits that require a constant
supply while the system is in standby
mode, such as a real time clock. The
low power LDO is capable of producing an output from 0.8V up to the input
Table 1. The LTC3589 supplies eight voltage rails delivering currents from 25mA to 1.6A
•Flexible pin strap supply sequencing
TYPE
AVAILABLE
OUTPUT
CURRENT
OUTPUT VOLTAGE CONTROL
LDO1
25mA
Resistive divider based on 0.8V feedback reference
LDO2
250mA
Resistive divider based on 0.3625V to 0.75V DAC feedback reference
•IRQ pin and status register error
reporting
LDO3
250mA
Fixed 1.8V
LDO4
250mA
1.8V, 2.5V, 2.8V, 3.3V selectable using I 2C command register
•Power good status pin and register
Buck1
1.6A
Resistive divider based on 0.3625V to 0.75V DAC feedback reference
•Built-in pushbutton controller to initiate
power-on, provide a debounced pushbutton status and force a device hard reset
Buck2
1A
Resistive divider based on 0.3625V to 0.75V DAC feedback reference
Buck3
1A
Resistive divider based on 0.3625V to 0.75V DAC feedback reference
Buck-Boost
1.2A
Resistive divider based on 0.8V feedback reference
•I2C control of all major regulator
functions
•Dynamic voltage scaling with selectable
ramp rate
October 2011 : LT Journal of Analog Innovation | 27
The LTC3589’s eight supplies are completely independent,
but they can be easily sequenced with simple pin strapping.
Likewise, the LTC3589 simplifies overall power system
design by integrating a number of important control features.
supply, set by a resistive divider. As long
as an input supply is attached to the
LTC3589, the always-alive LDO regulates.
The LTC3589 only consumes 8µ A of input
supply current in standby mode, even
as the always-alive LDO regulates.
from a voltage lower than the primary
input supply to reduce the power consumption in the LDO. Typically, the
LTC3589 switching converters supply the
LDO regulators. Two of the LDO regulators
have fixed or I2C selectable output voltage. The third LDO uses external feedback
resistors with a 5-bit DAC reference to set
its output using an I2C command register.
Three more LDOs, each capable of delivering 250m A, are handy for supplying
power to system analog functions such
as phase lock loops, D/A and A/D converters, or as general purpose rails. The
250m A LDO regulators can be powered
The LTC3589 is designed to run from an
input supply range of 2.7V to 5.5V. To
satisfy the requirements of devices that
POWERPATH
CONTROLLER/
Li-ION CHARGER
VIN
require a 3.3V or 5V rail, the LTC3589
includes a high efficiency buck-boost
switching converter that can output
voltage from 1.8V to 5V, set by a resistive divider. The buck-boost converter
is capable of supporting loads up to
1.2A. Using the I2C serial port, the buckboost converter can be set to low power
Burst Mode operation to reduce power
loss in low current output modes.
Three buck regulators complete the
LTC3589 complement of regulated
LTC3589
VOUT
REAL TIME CLOCK
LDO 1
CC/CV
Figure 2. Combine the LTC3589 with
a PowerPath™ controller/battery
charger for power distribution with
supply sequencing, I2C controls and
pushbutton control.
VOUT
LDO 2
+
Li-Ion
VOUT
LDO 3
VSTB
DVS
CONTROL
DSP
EN
PLL OR ADC
EN
VOUT
PERIPHERALS
LDO 4
SCL
SDA
VOUT
I2C
BUCK 1
µP
VOUT
RSTO
IRO
PGOOD
STATUS
WAKE
ON
28 | October 2011 : LT Journal of Analog Innovation
PUSHBUTTON
CONTROL
DDR MEMORY
EN
VOUT
BUCKBOOST
SRAM
EN
VOUT
BUCK 3
PBSTAT
PWR_ON
BUCK 2
µP
EN
EN
I/O
design features
LTC3589
BUCK OR LDO
+
VOUT
–
VOUT
1V/DIV
FB
DAC
UP/DOWN SLEW
CONTROL
5
5
I2C REGISTER
5
I2C REGISTER
PGOOD
5V/DIV
MUX
VSTB
5V/DIV
2
200µs/DIV
VRRCR = 1.75mV/µs
I2C REGISTER
I2C REGISTER
VSTB
voltage outputs. The buck converters’
output voltages, set with external resistor dividers, can range from as low as
the minimum DAC reference voltage to as
high as the input supply voltage, where
the bucks operate in dropout mode.
Depending on the requirements of the
application, each buck’s operating mode
can be set using the I2C command registers. For operation over a wide range
of output currents, pulse-skipping mode
gives good efficiency with low ripple.
Burst Mode operation offers the highest efficiency at low power. When set to
Burst Mode operation, the buck automatically moves between Burst Mode
operation at low loads and continuous
switching mode at higher output loads.
Selecting forced continuous mode results
in the lowest output voltage ripple at
the expense of some efficiency. Each
buck’s operating mode is independently
selected using the I2C command registers.
DYNAMIC VOLTAGE SCALING
Since portable battery operated devices
spend much of the time in standby or
low power modes, microprocessors may
take advantage of dynamic voltage scaling to reduce switching power loss by
decreasing the processors supply voltage.
The LTC3589 supports dynamic voltage
scaling (DVS) on one of the LDO regulators and all three buck converters.
Each scalable regulator on the LTC3589
uses two DAC feedback reference set-point
voltages in the I2C command registers
and a selectable transition slew rate
between the high and low target voltages (see Figure 3). Transition between
target voltages is initiated for all regulators using the VSTBY pin or for individual
regulators using I2C command registers.
The scalable LDO and buck converters
have independently controlled DAC-driven
feedback reference voltages. The reference voltage range runs from 0.3625V to
0.75V in 31 12.5mV steps. The converter
output voltage is scaled up from the
reference voltage using a resistive feedback divider from the converter output
to its feedback input. At power-on,
each DAC defaults to a reference output
of 0.675V so the output voltage can be
increased from the default output by
10% to increase the processor performance or for power supply margining.
Figure 3. Dynamic voltage scaling is supported
on four of the LTC3589’s eight outputs with I2C
selectable up/down slew rate.
During a voltage-down slew, the stepdown regulators are automatically
switched to forced continuous mode and
therefore are able to sink current from the
load. A 2k resistor to ground is switched
to the output of the DAC-referenced LDO to
pull down its output. Four slew rates
are selectable by choosing the rate of
change of the reference, from 0.88V/ms
to 7V/ms, via the I2C command register.
EASY SEQUENCING AND ENABLE
CONTROL
Multirail systems typically require the
supply rails come up to voltage in a
predetermined sequence (because of
latchup, brains in right order, start-up
current, etc.). Sequencing the LTC3589
outputs in any order is accomplished
by pin-strapping regulator outputs to
regulator inputs. Figure 4 shows an
example of a pin-strapped sequence. Each
enable pin has a precise 500mV comparator input with a built-in 200µs delay
timer before enabling the regulator.
The start-up sequence is defined by tying
the LTC3589 WAKE pin to the enable pin
of the first regulator or regulators in
the sequence. Wrapping regulator outputs around to the next enable in the
October 2011 : LT Journal of Analog Innovation | 29
A regulator not in the start-up sequence is controlled
by driving its pin directly or using the I2C command
register. Any of the regulators in a pin-strapped sequence
can be enabled or disabled in any order by setting a
software control bit in the I2C command registers.
Figure 4. Flexible and simple start-up
sequencing is accomplished by tying
regulator outputs to enable pins in
any order.
WAKE
V1
EN1
LTC3589
SW1
1V TO 1.2V
EN3
SW2
1.8V
SW3
0.8V TO 1V
BB_OUT
3.3V
EN_LDO34
LDO2
1.2V
ON
LDO3
1.8V
PWR_ON
LDO4
2.8V
EN_LDO2
PWR_ON
1V
V3
WAKE
EN2
EN4
1.2V
0.5V 200µs
V2
0.5V
1.8V
200µs
3.3V
V4
LDO2
LDO3
200µs
1.2V
1.8V
2.8V
LDO4
sequence brings the supplies up in order.
If additional start-up delay is required,
add a resistive divider to raise the enable
voltage threshold or add an RC filter
with the desired time constant to delay
the start of the subsequent regulator.
buck converters and the DAC-controlled
LDO have a keep-alive bit setting in the
I2C control register. Setting any of the
keep-alive bits in the I2C command register
keeps the corresponding regulators alive
when the LTC3589 is in standby mode.
A regulator not in the start-up sequence
is controlled by driving its pin directly or
using the I2C command register. Any of
the regulators in a pin-strapped sequence
can be enabled or disabled in any order
by setting a software control bit in the
I2C command registers. Once the software control bit is set, all the regulators
ignore their enable pin status and respond
only to I2C command register control.
This allows a regulator to be powered
down without affecting the subsequent
regulators in a pin-strapped sequence.
To ensure the integrity of a power-up
sequence following a power-down, the
LTC3589 adds a one second delay to allow
the regulator outputs to fall to ground.
Additionally, 2k pull-down resistors are
inserted on the LDO outputs and buck
switch pins to ensure discharge. Each
regulator’s output voltage must be less
than 300mV before it is allowed to enable.
I2C command register settings are available to override the resistor pull-downs
and the 300mV start-up rule in cases where
the regulator outputs are back-driven.
Applications with keep-alive requirements such as volatile memory or
watchdog functions requiring more
power or additional voltage rails can
take advantage of the LTC3589 keepalive control function. Each of the three
PUSHBUTTON OPERATION
30 | October 2011 : LT Journal of Analog Innovation
The pushbutton control circuit included
in the LTC3589 provides a debounced user
interface to initiate a power-up sequence.
A power-up sequence from standby
mode begins when the pushbutton is
depressed to activate the open driver
WAKE pin. If the WAKE pin is tied to a
regulator enable pin, the power-up
sequence begins. Once the controller is
satisfied system power is good then the
PWR_ON pin should be driven high. For
normal shutdown, pull PWR_ON low.
The PBSTAT pin is an open drain output
that signals to the microprocessor that
the button has been pushed and some
change in operation or power-down has
been requested. If the system is no longer responding for some reason, holding the button for five seconds forces
a hard reset, which powers down the
regulators, asserts the RSTO reset pin
and puts the LTC3589 in standby mode.
If pushbutton functions are not needed,
the WAKE pin is enabled and disabled by
driving the PWR_ON pin directly. Even
when driving the PWR_ON pin directly,
the pushbutton PBSTAT status pin and
hard reset functions are active.
design features
C7
0.47µF
3.3V, 25mA
10µF
10µF
VIN
C6
C1
4.7µF 68nF
VIN
R2
150k
BOOST
SW
R11
499k
RT
PG VC
GND
FB
BD SYNC
C2
10µF
0805
USB
VBUS
OVGATE
VC WALL
OVSENS
D0–D2
TO µC
CHRG
R7
100k
T
R8
100k
C4
22µF
1µF
68k
EN2
VL2
EN3
VB3
EN4
VB2
EN_LDO2
VBB
EN_LDO34
C3
0.1µF
0603
R9
2.94k
VBB
TO µP
SW2
LTC3589
10pF
4.7k
68k
AUTOMOTIVE,
FIREWIRE,
ETC.
M1
ZXMP10A18G
1.5µH
10pF
PWR_ON
681k
VB3
1.2V
1A
22µF
BUCK3_FB
PGOOD
787k
BB_OUT
DVDD
SDA
4.7pF
SCL
BB_FB
VSTB
SW4AB
PBSTAT
1M
VBB
3.3V
1A
22µF
316k
2.7µH
SW4CD
VIN_LDO2
D1
MMBZ524- R5
0BLT1G
10k
10V
R4
10k
22µF
SW3
M2
ZXMP10A18G
R3
33k
VB2
1.8V
1A
422k
ON
HVIN
715k
BUCK2_FB
IRQ
4.7k
+
Li-Ion
R10
1k
1.5µH
WAKE
68k
GND BATSENS
22µF
768k
VB1
68k
VB1
1.2V
1.6A
604k
BUCK1_FB
RSTO
BAT
CLPROG PROG
1µH
SW1
10pF
EN1
NTCBIAS
NTC
PVIN4
1M
68k
M5
PVIN3
316K
M4
ACPR SW
PVIN2
LDO1_FB
C5
10µF
0805
IDGATE
LTC4098
PVIN1
LDO1_STDBY
VOUT
OVGATE
TO µC
VIN
R12
100k
L1
3.3µH
10µF
22µF
HVBUCK
LT3480
RUN/SS
R6
40.2k
L2
10µH
10µF
10µF
VB2
LDO2
604k
1µF
VL2
1.2V
250mA
LDO2_FB
R1
1k
VIN_LDO34
M3
ZXMN10A08E6
VBB
768k
1µF
VL3
1.8V
250mA
1µF
VL4
2.8V
250mA
LDO3
GND
LDO4
Figure 5. Integrated power IC for mobile microprocessor system with USB/automotive battery charger
STATUS REPORTING
Three pins are provided for the LTC3589
to send status to the controlling microprocessor. The RSTO, IRQ, and PGOOD pins
are open drain outputs that signal regulator low output, hard reset events, supply
undervoltage, hot die temperature and
fault conditions. The IRQ and PGOOD pins
are matched to I2C status registers, which
can be read to determine the specific cause
of the status pin activity. In the event of a
fault, such as die overtemperature or UVLO,
that shuts down the LC3589 regulators,
the cause of the shutdown is latched in
a status register that can be read by the
system controller after system reboot.
CONCLUSION
The LTC3589 with eight regulator outputs,
flexible sequencing, dynamic voltage
scaling and serial port control is ideally
suited for applications-processor-based
consumer, industrial and automotive
devices. When coupled with a step-down
regulator, the LTC3589 can supply a complete set of system supply rails from high
voltage primary sources such as automotive systems. Add a PowerPath controller/
battery charger IC to generate system rails
for Li-ion-powered portable devices.
The LTC3589 features low power standby
and Burst Mode operation, keep-alive
functions and dynamic voltage scaling so
that system designers can optimize battery
life. Pushbutton control simplifies board
design and provides start-up, processor
interrupt and hard reset functions. n
October 2011 : LT Journal of Analog Innovation | 31
3-Phase Synchronous Step-Down DC/DC Controller with
Stage Shedding, Active Voltage Positioning and Nonlinear
Control for High Efficiency and Fast Transient Response
Jian Li and Kerry Holliday
The LTC3829 is a feature-rich single-output 3-phase synchronous buck controller
with on-chip drivers, remote output voltage sensing, inductor DCR temperature
compensation, Stage Shedding™ mode, active voltage positioning (AVP) and nonlinear
control. It is suitable for input from 4.5V to 38V and output from 0.6V up to 5V. The
LTC3829 provides high efficiency, high power density and versatile power solutions for
computers, telecom systems, industrial equipment and DC power distribution systems.
The LTC3829 is available in 38-pin 5mm × 7mm QFN and 38-pin FE packages.
VIN
VIN
DIFFOUT
20.0k
MODE
RUN
40.2k
VOSENSE–
66.5Ω
RUN
MODE
ILIM
ITH
4.7µF
16V
Q1
Q3
D1 CMDSH-3
0.1µF
ISET
TG1
TG1
DIFFN
SW1
DIFFP
BG1
AVP
SW1
180µF
16V
L1
0.33µH
Q4
S1P
S1N
RSENSE1
0.001Ω
100µF
6.3V
X5R
330µF
2.5V
SANYO
×2
+
DIFFOUT
EXTVCC
PGOOD
PGOOD
TG2
BG1
ITEMP
ITEMP
SW2
GND
BG2
10µF
16V
X5R
BOOST2
0.1µF
Q1,Q5,Q9: RJK0305DPB
Q3,Q4,Q7,Q8,Q11,Q12: RJK0330DPB
TG2
SW2
BG2
Q5
D3 CMDSH-3
L2
0.33µH
BOOST3
TK/SS
SENSE3–
0.1µF
SENSE2–
SENSE3+
VOUT
VIN
D2 CMDSH-3
LTC3829
EXTVCC
SENSE1+
VIN
7V TO 14V
+
GND
VIN
DIFFOUT
CSS
0.1µF
180µF
16V
BOOST1
SENSE1–
SENSE2+
0Ω
CLKOUT
+
INTVCC
INTVCC
VFB
13.5k
40.2k
VOSENSE+
PLLIN
CLKOUT
FREQ
PLLIN
47pF
1nF
10µF
16V
X5R
VIN
0.1µF
30.1k
IFAST
100pF
2.2Ω
100k
Q7
TG3
Q8
S2P
S2N
RSENSE2
0.001Ω
VOSENSE+
10Ω
100µF
6.3V
X5R
+
SW3
VOUT
1.5V
330µF 60A
2.5V
SANYO
×2
GND
BG3
VIN
1000pF
1000pF
1000pF
100Ω
10Ω
10µF
16V
X5R
S3N
–
VOSENSE
100Ω
S3P
Figure 1. A 1.5V/60A,
3-phase converter
featuring the LTC3829
100Ω
100Ω
100Ω
100Ω
32 | October 2011 : LT Journal of Analog Innovation
TG3
S2N
Q9
SW3
S2P
S1N
S1P
BG3
Q11
L3
0.33µH
Q12
S3P
S3N
RSENSE3
0.001Ω
100µF
6.3V
X5R
+
330µF
2.5V
SANYO
×2
VOUT
design features
The LTC3829’s constant-frequency peak current mode
control architecture allows a phase-lockable frequency of
up to 770kHz. Even at this high frequency, high step-down
ratios are possible, thanks to the LTC3829’s ability to operate
at low duty cycle due to its small minimum on-time (90ns).
LTC3829 FEATURES
22
The LTC3829 is a current mode PolyPhase®
controller, similar to the LTC3850, but with
an integrated a high speed differential
amplifier for remote output voltage sensing, which can eliminate regulation errors
due to PCB voltage drops at heavy loads.
Figure 1 shows a typical 7V~14V input,
1.5V/60A output application schematic.
20
18
VR(SENSE) (%)
16
Figure 2 shows the tightly balanced
DC current sharing between stages.
Dynamic current sharing is also well balanced cycle-by-cycle due to the LTC3829’s
peak current mode architecture.
Figure 3. Efficiency with and without Stage Shedding
mode enabled
14
12
10
8
6
4
PHASE 1
PHASE 2
PHASE 3
2
0
PolyPhase Operation and High
Step-Down Ratios at High Frequency
The LTC3829’s three channels run
120° out-of-phase, reducing input
RMS current ripple, as well as the required
input capacitance. The CLKOUT and
PLLIN pins enable up to 6-phase operation with multiple LTC3829s.
Accurate DCR Current Sensing
over Temperature
VIN = 12V
VOUT = 1.5V
–2
0
10
20
40
30
ILOAD (mA)
50
60
Figure 2. Current sharing performance
The LTC3829’s constant-frequency
peak current mode control architecture allows a phase-lockable frequency
of up to 770kHz. Even at this high
frequency, high step-down ratios are
possible, thanks to the LTC3829’s ability to operate at low duty cycle due to
its small minimum on-time (90ns).
The LTC3829’s maximum current sense
voltage is selectable—30mV, 50mV or
75mV—allowing the use of either the
inductor DCR or a discrete sense resistor as the current sensing element. The
inductor winding resistance (DCR) changes
over temperature. So to improve accuracy, the LTC3829 can sense the inductor temperature via the ITEMP pin and
maintain a constant current limit over
a broad temperature range. This makes
high efficiency inductor DCR sensing more
reliable for high current applications.
Stage Shedding for Improved
Light Load Efficiency
At heavy loads, the LTC3829 operates in
constant frequency PWM mode. At light
loads, it can operate in any of three
modes: Burst Mode operation, forced
continuous mode and Stage Shedding
mode. Burst Mode operation switches
in pulse trains of one to several cycles,
Figure 4. Stage Shedding mode: 3-phase to 1-phase
transition
Figure 5. Stage Shedding mode: 1-phase to 3-phase
transition
95
EFFICIENCY (%)
FORCED
CONTINUOUS
MODE
85
VOUT
100mV/
DIV
VOUT
20mV 100mV/
DIV
VSW1
10V/DIV
VSW1
10V/DIV
VSW2
10V/DIV
VSW2
10V/DIV
VSW3
10V/DIV
VSW3
10V/DIV
30mV
STAGE SHEDDING MODE
80
75
0
10
ILOAD (A)
100
10µs/DIV
10µs/DIV
L = 330nH
QT = RJK0305DPB
VIN = 12V
RSENSE = 1mΩ QB = 2xRJK0330DPB
VOUT = 1.5V
FSW = 400kHz
October 2011 : LT Journal of Analog Innovation | 33
Linear Technology’s proprietary programmable
Stage Shedding feature can further improve the
power supply efficiency in loads up to ~30%. At light
loads, two of the three channels can be shut down
in order to reduce switching-related losses.
VOUT
100mV/DIV
200mV
VOUT
100mV/DIV
125mV
LTC3829
AVP
RPRE-AVP
DIFFP
DIFFN
RAVP
VOUT
ILOAD
20A/DIV
ILOAD
20A/DIV
100µs/DIV
Figure 6. Programmable AVP
with the output capacitors supplying
energy during internal sleep periods. This
provides the highest possible efficiency
at very light load. Forced continuous
mode offers continuous PWM operation
from no load to full load, providing the
lowest possible output voltage ripple.
In addition, Linear Technology’s proprietary programmable Stage Shedding feature
can further improve the power supply
efficiency in loads up to ~30% of full load
as shown in Figure 3. At light loads, two
of the three channels can be shut down in
order to reduce switching-related losses.
When the MODE pin is tied to INTVCC ,
the LTC3829 enters Stage Shedding mode.
This means that the second and third
channels stop switching when the ITH pin
voltage is below a certain programmed
threshold. This threshold voltage,
VSHED, on the ITH pin is programmed
according to the following formula:
VSHED = 0.5 +
5
(0.5 − VISET )
3
34 | October 2011 : LT Journal of Analog Innovation
Figure 7. Transient performance without AVP
Connecting a single resistor from the
ISET pin to SGND sets VISET by way of the
precision 7.5µ A current source from ISET.
Stage Shedding mode in the LTC3829
features smooth transitions when dropping from 3-phase to 1-phase operation and likewise when increasing from
1-phase to 3-phases, with minimum ripple
on the output, as shown in Figures 4
and 5. The smooth transition is a direct
result of current mode control—a voltage mode, multiphase supply would have
trouble achieving this performance.
100µs/DIV
Figure 8. Transient performance with AVP
The AVP scheme modifies the regulated
output voltage depending on its current
loading. The LTC3829 senses inductor
current information by monitoring voltage across the sense resistor, RSENSE or
the DCR sensing network of all three
channels. The voltage drops are added
together and applied as VPRE-AVP between
the AVP and DIFFP pins, which are connected through resistor RPRE-AVP. Then
VPRE-AVP is scaled through RAVP and added
to the output voltage as the compensation for the load voltage drop. As shown
in Figure 6, the load slope (RDROOP) is:
Active Voltage Positioning ( AVP )
Transient performance is a priority in high
current power supply designs. To minimize
the voltage deviation during load steps, the
LTC3829 includes two features that lower
peak-to-peak output voltage deviation for
a given load step: one is the programmable
active voltage positioning (AVP); the other
is the programmable nonlinear control.
RDROOP = RSENSE •
V
 
RPRE− AVP  A 
R AVP
With proper design, AVP can reduce
the magnitude of transient induced
peak-to-peak voltage spikes by 38%,
as shown in Figures 7 and 8.
design features
The LTC3829 3-phase step-down controller fits an
outsized feature set into a small 5mm × 7mm 38-pin
QFN, making it ideal for high current applications,
including telecom and datacom systems,
industrial and high performance computers.
VOUT
100mV/DIV
95mV
VOUT
100mV/DIV
VSW1
10V/DIV
VSW1
10V/DIV
VSW2
10V/DIV
VSW2
10V/DIV
VSW3
10V/DIV
VSW3
10V/DIV
2µs/DIV
2µs/DIV
Figure 9. Transient performance without nonlinear control
Nonlinear Control
The LTC3829 features a unique nonlinear
control loop that can improve transient
response dramatically. In the nonlinear
control loop, an internal circuit monitors the output of the error amplifier. If
the amplifier is sinking or sourcing large
output currents (level programmable),
the supply output voltage has significant overshoot or undershoot. This is
when nonlinear control takes over: the
controller simultaneously turns all of
the TG signals on at a load step up, or
off at a load step down to avoid control
loop or PWM switching cycle delays.
This feature is enabled and programmed
through the IFAST pin. When the IFAST pin
is tied to INTVCC , the nonlinear control loop is disabled. The IFAST pin
75mV
Figure 10. Transient performance with nonlinear control
sources a precision 10µ A, so connecting a resistor from IFAST to SGND sets
VIFAST. When VIFAST is set below 0.5V,
the difference of 0.5V and VIFAST sets the
threshold voltage that triggers nonlinear control. Nonlinear control is only
enabled when the feedback voltage
VFB is within the UV and OV window.
Once nonlinear control is enabled, the
top gate of all channels is turned on if:
VFB = VREF −
0.5 − VIFAST
• 1.2
5
The top gate of all channels
is turned off if:
VFB = VREF +
0.5 − VIFAST
5
where VREF is the reference voltage (0.6V).
With proper design, nonlinear control
can improve transient response by
21% during the load step up transient,
as shown in Figures 9 and 10.
CONCLUSION
The LTC3829 3-phase step-down controller fits an outsized feature set into a small
5mm × 7mm 38-pin QFN. It offers high
efficiency with strong integrated drivers
and Stage Shedding/Burst Mode operation. It supports temperature compensated
DCR sensing for high reliability. Its AVP and
nonlinear control can improve transient
response with minimum output capacitance. Output tracking, multi-device current sharing and external sync capability
fill out its menu of features. The LTC3829 is
ideal for high current applications, including telecom and datacom systems, industrial and high performance computers. n
October 2011 : LT Journal of Analog Innovation | 35
What’s New with LTspice IV?
Gabino Alonso
Follow @LTspice on Twitter for
up-to-date information on models, demo circuits,
events and user tips: www.twitter.com/LTspice
NEW DEVICE MODELS
LTspice®
IV is a high performance SPICE simulator, schematic capture and waveform viewer specifically
designed to speed up the process of power supply design. LTspice IV adds enhancements and models to SPICE,
significantly reducing simulation time compared to typical SPICE simulators, allowing one to view waveforms for
most switching regulators in minutes compared to hours for other SPICE simulators.
LTspice IV is available free from Linear Technology at www.linear.com/LTspice. Included in the download is a
complete working version of LTspice IV, macro models for Linear Technology’s power products, over 200 op amp
models, as well as models for resistors, transistors and MOSFETs.
What is LTspice IV?
COOKING WITH LTspice IV
SEMINAR TAKES WORLD TOUR
Mike Engelhardt, the author and creator
of LTspice IV, is embarking on a world
tour to teach you the ins and outs of
LTspice IV in a series of free half-day seminars. At each seminar, Mr. Engelhardt will
show you how to quickly simulate switch
mode power supplies, compute efficiencies and observe power supply start-up
behavior and transient response. You
will also learn how to use LTspice IV as
a general-purpose SPICE simulator for
AC analysis, DC sweeps, noise analysis
and circuit simulations. The presentation
includes a description of the algorithms
used in LTspice IV to give
you a unique and powerful perspective on the inner
workings of LTspice IV.
For more information on these
upcoming seminars and other
events please visit www.linear.com/LTspiceEvents.
LT3029: Dual 500m A /500m A low
dropout, low noise, µpower linear
regulator www.linear.com/3029
NEW HOW-TO VIDEOS
LT6109-1/LT6109-2: High side current
One of the fastest ways to get started with
LTspice IV and learn a few user tips, is
to watch the instructional videos available at www.linear.com/LTspiceVideos.
Two new videos are now available:
sense amplifier with reference and
comparators www.linear.com/6109
•The first new instructional video covers the LTspice IV Schematic Editor
(video.linear.com/84). This video
shows how to use the LTspice IV schematic capture program in the layout
of a simple circuit so you can quickly
draft and make edits to your design.
LTC3618: Dual 4MHz , ±3A synchronous
•The second video covers the
LTspice IV Waveform Viewer (video.
linear.com/88). This video shows you
how to quickly probe
the circuit for current and voltage
response, and how to view and
measure the waveforms. It
also includes techniques
to navigate the waveforms
as you analyze results.
Get the Schedule
LT3970-3.3/LT3970-5: 40V, 350m A step-down
regulator with 2.5µ A quiescent current and
integrated diodes www.linear.com/3970
buck converter for DDR termination
www.linear.com/3618
LT6107: High temperature, high side current
sense amp in SOT-23 www.linear.com/6107
LTC4225-1/LTC4225-2: Dual ideal diode and
Hot Swap controller www.linear.com/4225
LTC3867: Synchronous step-down
DC/DC controller with differential
remote sense and nonlinear
control www.linear.com/3867
LTC3388-1/LTC3388-3: 20V high efficiency
nanopower step-down regulator
www.linear.com/3388
LTC3634: Dual 15V, 3A monolithic
step-down regulator for DDR power
www.linear.com/3634
Two new LTspice IV how-to videos are now available
LTspice IV
Schematic Editor
36 | October 2011 : LT Journal of Analog Innovation
To update your installation of
LTspice IV with the latest models,
choose Sync Release from the
Tools menu in LTspice IV. Here is
a list of some new models:
LTspice IV
Waveform Viewer
design ideas
COMPUTING THE AVERAGE OR RMS VALUE OF A TRACE IN LTSPICE IV
The LTspice IV waveform viewer can
integrate a trace to produce the average
or RMS value over a given region.
1.Zoom in to the region of interest.
To integrate a trace in the waveform
viewer:
Based on the physical units of the data
trace, LTspice IV displays a meaningful
2.Hold down the control key and click the
label of the trace you want to integrate.
average for that type of data. For example,
if the units are a voltage or current,
LTspice IV displays the average and
the RMS values. Otherwise, LTspice IV
displays the average and integral of the
data displayed in the waveform viewer.
If you’re plotting noise densities from a
.noise simulation, LTspice IV shows total
RMS noise.
Happy simulations!
LTspice IV Power-User Tip
It’s easy to calculate the
RMS or average value
of a waveform trace
in LTspice IV. For more
information, see the
LTspice IV Power-User
Tip above.
L1**
6.8µH
+
–
+
CIN
10µF
–
VIN
SW
R1
1.37M
LTC3105
RMPPC
4.99k
THERMALLY
COUPLED
FB
PGOOD
MPPC
D1*
VOUT
3.3V
VOUT
OFF ON
CMPPC
10nF
D2*
LDO
SHDN
AUX
CAUX
1µF
2.2V
COUT
10µF
R2
604k
FBLDO
GND
Download the LTspice IV demonstration circuit for
this 2-cell photovoltaic to dual output, 3.3V and
2.2V, converter at www.linear.com/3105
CLDO
4.7µF
* MRA4003T3
** PANASONIC ELL-VEG6R8N
LTC3617: ±6A monolithic synchronous
step-down regulator for DDR termination
www.linear.com/3617
LTM®4613: EN55022B-compliant,
36V input, 15V, 8A output, DC/DC µModule
regulator www.linear.com/4613
NEW LTspice IV DEMO CIRCUITS
•Automotive ±30V supply protection circuit with 3.5V undervoltage and 18V overvoltage using the
LTC4365. www.linear.com/4365
•5V to 12V, 900m A step-up
DC/DC converter using the LT3581.
www.linear.com/3581
•A dual synchronous step-up converter that takes a 5V–24V input to
24V, 3A–5A and 12V, 8A–10A using the
LTC3788. www.linear.com/3788 n
•4V–15V to 1.8V, 2.5A monolithic synchronous step-down DC/DC converter using
the LTC3603. www.linear.com/3603
The LTspice IV circuit collection is available at www.linear.com/DemoCircuits.
Here are some of the new demonstration circuits now available:
•36V to 12V, 8A integrated stepdown DC/DC converter using the
LTM4613. www.linear.com/4613
•A 4.5V–10V to 2.5V, 2.5A monolithic
synchronous step-down DC/DC using
the LTC3602. www.linear.com/3602
+
VIN
4V TO
38V
1µF
CER
4.7µF
ILIM
INTVCC IOSENSE–
PGOOD
IOSENSE+
VIN
22µF
50V
CER A
VINSNS
VOUTSNS
TG2
LTC3789
BOOST1
BOOST2
TG1
0.1µF
SW1
B
BG1
2200pF
1000pF
8k
0.01µF
D
+
C
BG2
ITH
MODE/PLLIN
SS
RUN
SGND
0.1µF
10µF
16V
CER
VOUT
12V
5A
330µF
16V
SW2
ON/OFF
VFB
FREQ
SENSE+ SENSE– PGND
The LTspice IV demonstration circuit for this 12V,
5A automotive high efficiency buck-boost DC/DC
solution with programmable output current limit
is available at www.linear.com/3789
0.010Ω
EXTVCC
121k
105k
1%
7.5k
1%
0.010Ω
4.7µH
October 2011 : LT Journal of Analog Innovation | 37
15A µModule Regulator Solves Thermal Problems by
Converting 12V to 1V with High Efficiency
Eddie Beville
Advances in silicon process technology continue
to reduce transistor geometries down to historical
levels in microprocessors, FPGAs and ASICs. The
power supply voltage levels necessary to power these
large, complex digital devices also continue to shrink,
creating unique power supply design challenges.
One major concern is the power regulator’s conversion efficiency at low output
voltages. For example a typical high
efficiency switching regulator that converts 12V to 3.3V at 15A has a conversion efficiency of ~93%. For practical
purposes, such a regulator incurs most
of its efficiency loss due to I2R losses.
Therefore 93% efficiency for processing
49.5W to the load equates to a 3.72W loss.
Likewise, a low output voltage requirement of 1V at 15A with an efficiency
of 76% incurs a power loss of 4.74W.
Typical high density power solutions
are challenged to achieve high efficiencies at low output voltages due to the
size constraints of the power stage. The
power stage must have high performance
system temperature, thus compromising system performance and reliability.
power MOSFETs and inductors to improve
low voltage conversion efficiency not
just an increase the solution size.
In reality, many feature-laden digital
devices have current requirements in the
>30A range for the low voltage supply. Thus a 76% efficiency 1V output
would incur a 9.48W loss for a 30A load,
which would certainly cause thermal
challenges. The thermal problems multiply with the number of 30A regulators required on a system board.
Unchecked regulator power losses,
when added to other system power
losses create serious thermal challenges. One issue is that small-geometry
ASIC or FPGA leakage currents rise with
Figure 1. A complete 1V at 15A converter requires only a few components around the LTM4627 µModule
regulator, which comes in a thermally enhanced 15mm × 15mm × 4.32mm package
One possible solution is to use a power
converter module that can deliver significantly higher output power than necessary
for the application, and run it at an output
current point that maximizes efficiency.
Of course, overly large solutions are not
feasible in space-constrained systems
and the current limit of this solution is
much higher than the required current.
Another solution is to use a discrete
power converter that is optimized for low
output voltage efficiency. But again space
constraints and component sourcing can
be challenging. Another challenge with a
discrete design is how to effectively cool it
and heat sink the various discrete power
components, which have different heights.
µMODULE SOLUTION
Figure 1 shows a complete 1.0V at 15A converter that uses the LTM4627 µModule
regulator housed in a 15mm × 15mm
× 4.32mm package. The LTM4627 integrates the high performance power path
Figure 2. Efficiency of the regulator in Figure 1
100
22µF
16V
×3
VOUT = 1V
fSW = 400kHz
95
10k
VIN
EXTVCC INTVCC PGOOD
RUN
VOUT
fSET
VOUT_LCL
COMP
150pF
100k
0.1µF
LTM4627
DIFF_OUT
TRACK/SS
VOSNS+
MODE_PLLIN
VOSNS–
SGND
38 | October 2011 : LT Journal of Analog Innovation
PGND
COUT1
470µF
6.3V
VFB
82pF
+
COUT2
100µF
6.3V
VOUT
1V
15A
90
EFFICIENCY (%)
VIN
4.5V TO 16V
85
80
75
70
RFB
90.9k
VIN = 5V
VIN = 8V
VIN = 12V
65
60
0
3
6
9
ILOAD (A)
12
15
design ideas
6% to 7% over typical (and larger)
solutions, or a power loss improvement of 1.68W in a small form factor.
16
OUTPUT CURRENT (A)
Figure 3 shows a LTM4627 thermal plot
for 12V to 1V at 15A with no airflow or
heat sinking. The temperature rise is ~40°C
above 25°C ambient at 65°C. The power
loss of ~3W multiplied by the data sheet
specified θJA thermal resistance of 13°C/W
matches the 40°C rise in the thermal plot.
Figure 3. Thermal plot of the LTM4627 converting
12V to 1V at 15A with no forced air or heat sink
The LTM4627 features include fully differential remote sensing, output voltage
tracking and soft-start, high efficiency
at light loads utilizing the Burst Mode
operation or pulse-skipping features,
voltage monitoring and frequency
synchronization. The LTM4627 uses
a current mode architecture, which
enables multiple µModule regulators
to run in parallel (Figure 5), sharing
the load for increased output current
with accurate current limit control.
10
VIN
The LTM4627 µModule regulator is a high
performance versatile DC/DC converter
that can be used in many applications
requiring high efficiency over a wide
output voltage range. The very small form
factor and ease of use make the LTM4627
ideal for space-constrained designs. n
VOUT
1V
30A
MODE_PLLIN
VOSNS–
SGND
GND
+
150pF
470µF
6.3V
DIFF_OUT
VOSNS+
100µF
6.3V
VFB
270pF
22µF
16V
×3
VIN
EXTVCC INTVCC PGOOD
COMP
VOUT
TRACK/SS
RUN
INTVCC
200k
LTM4627
VOUT_LCL
fSET
100k
MOD
60 70 80 90 100 110 120
AMBIENT TEMPERATURE (ºC)
VOUT
TRACK/SS
CLOCK SYNC
0˚ PHASE
SET
50
EXTVCC INTVCC PGOOD
RUN
OUT1
LTC6908-1
OUT2
GND
40
CONCLUSION
COMP
10k
1µF
0LFM, NO HEATSINK
200LFM, NO HEATSINK
400LFM, NO HEATSINK
INTVCC
22µF
16V
×3
V+
4
Current sharing is well balanced during
both steady state DC load and dynamic
transients. The accurate remote sense
amplifier yields outstanding voltage accuracy at the load point. For even higher output currents, simply add more LTM4627s.
VIN
7V TO 16V
Figure 5. A 2-phase, 30A design based on two parallel
LTM4627 µModule regulators clocked 180° out-of-phase.
For higher output currents, simply add more LTM4627s.
6
Figure 4. Derating curves for the
LTM4627 converting 12V to 1V
Figure 5 shows a 2-phase, 30A design utilizing two parallel LTM4627 µModule regulators that are clocked 180° out-of-phase
using clock signals from the LTC6908-1.
0.1µF
8
0
Figure 4 shows the LTM4627 12V to 1V derating curve. The LTM4627 can operate in
higher ambient temperatures with full load
capability in a very small form factor.
The LTM4627 µModule regulator is
optimized for high efficiency conversion
to low output voltages—with a complete
converter packaged in a small, thermally
enhanced form factor. The input voltage range is 4.5V to 20V with output
voltage programming from 0.8V to 5V.
Figure 2 shows efficiencies of 82% to 83%
for 1V at 15A from 5V, 8V and 12V inputs.
This is an efficiency improvement of
12
2
The LTM4627 package has a highly thermal
conductive substrate with a layout that
is thermally modeled and designed to
enhance thermal performance and uniform heat spreading. While the package
is small, it presents enough surface area
to a PCB (and heat sink) to minimize the
overall thermal resistance of the solution.
and control circuitry, thus simplifying the design to a few external bulk
capacitors and a few small resistors.
VIN = 12V
VOUT = 1V
14
CLOCK SYNC
180˚ PHASE
100k
LTM4627
VOUT_LCL
DIFF_OUT
fSET
VOSNS+
MODE_PLLIN
VOSNS–
SGND
GND
+
VFB
470µF
6.3V
100µF
6.3V
INTVCC
RFB1
45.3k
October 2011 : LT Journal of Analog Innovation | 39
Solve Isolated Control Problems by Up-Shifting Control
Frequency with TimerBlox PWM Generator
Tim Regan
Industrial and medical
systems often have
functions that are completely
isolated from the mains
power—requiring control
signals that must cross
the isolation barrier, usually
via a small transformer.
One cost-effective source
of control signals is the
I/O pin of embedded
controllers. The oscillators
and counters already
included in controllers can
be used to produce digitally
programmable PWM signals,
which can provide a variable
duty cycle square wave,
or, if averaged by a simple
RC lowpass filter, a linearly
variable analog voltage.
For example, if the I/O pin output of
an embedded controller produces a
varying duty cycle PWM signal that
switches between VCC and ground,
the average output voltage of the I/O
pin is simply VCC • (duty cycle).
The problem with using the PWM output
of an embedded controller to produce control signals in an isolated system is that the
frequency of these signals is often too low
for a small signal transformer to handle.
Figure 1 shows a simple strategy that
allows low frequency PWM signals to
be properly passed via small signal
40 | October 2011 : LT Journal of Analog Innovation
LOW FREQUENCY (1kHz) PWM
CONTROL SIGNAL SOURCE
V+
VISO
CONTROL
SOURCE
T1
FREQUENCY UP-SHIFT
RETAINING DUTY CYCLE
INFORMATION
PWM TO DC
CONTROL
AND/OR
RECONSTRUCTED
1kHz PWM
1kHz TO 250kHz
1kHz PWM
DC CONTROL VOLTAGE
1kHz PWM
ISOLATION BARRIER
5% TO 95% DUTY CYCLE
Figure 1. Transferring control information across a small signal isolation transformer requires a higher
frequency PWM signal than that produced by most embedded controllers. On the isolated side, the resulting
signal can be either converted to a DC control voltage or converted to a replicate of the original PWM signal.
transformers across an isolation barrier. In
this solution, the low frequency PWM signal is converted to a higher frequency
while retaining the duty cycle control
information. Specifically, a 1kHz PWM signal is shifted to 250kHz, coupled across the
isolation barrier, then shifted back down
OPTIONAL ANTICIPATOR CIRCUIT
(SEE FIGURE 5)
C2
R2
10µF
τ2 = 500ms 49.9k
R3
3.24k
V+
C3
0.1µF
to the original 1kHz (or simply converted
to a DC voltage control signal). Changes
in the source PWM signal duty cycle are
duplicated nearly instantly on the isolated
side. Accuracy of the isolated control signal is within 1% of the source duty cycle.
V+
49.9k
49.9k
0.1µF
0.22µF
τ = 10ms
B2
OPTIONAL
CMOS
BUFFER
VISO
LOW FREQUENCY
(1kHz) PWM
CONTROL SIGNAL
SOURCE
OPTIONAL
CMOS
BUFFER
V+
PWM
B1
5% TO 95% DUTY CYCLE
PRIMARY GROUND
SECONDARY GROUND
V+
–
R1
49.9k
C1
10µF
U1A
½ LTC6256
+
–
U1B
½ LTC6256
+
10k
MOD
OUT
LTC6992-2
GND
20k
780µH
V+
SET
780µH
V+
0.1µF
τ1 = 500ms
T1
10k
DIV
RSET1
200k 250kHz PWM
500V
ISOLATION BARRIER
T1: COILCRAFT WB1010-SM
Figure 2. Nonisolated control side. A TimerBlox® PWM circuit generates a 250kHz signal with the same duty
cycle as the original low frequency PWM signal. The optional anticipator circuit improves step response by
anticipating step changes in the duty cycle of the control PWM (see “Circuit Enhancements” below).
design ideas
The problem with using the PWM output of an embedded controller to produce control
signals in an isolated system is that the frequency of these signals is often too low for a
small signal transformer to handle. Here is a simple strategy that allows low frequency PWM
signals to be properly passed via small signal transformers across an isolation barrier.
UP-SHIFTING THE
PWM CONTROL FREQUENCY
programmed using resistors. Resistor
RSET fixes an internal master oscillator
frequency and the voltage on the DIV pin
sets an internal frequency divider ratio.
Figure 2 shows a circuit that converts
a 1kHz PWM signal to a 250kHz signal with the exact same duty cycle.
This 250kHz signal can easily couple
across an isolation transformer.
Amplifier U1B (one half of an LTC6256
low power dual rail-to-rail op amp) is an
integrator used to servo the voltage at the
MOD pin to force the 250kHz signal duty
cycle to match the 1kHz input signal duty
cycle. Simple RC lowpass filters convert
both PWM clocks to their average DC voltages. To minimize duty cycle jitter, the
time constants of these filters should be
much longer than the clock period. The
1k Hz PWM signal is filtered with a 500ms
time constant network while the 250kHz
filter is 10ms. The integrator output
voltage stops at the MOD pin voltage
The LTC6992-2 is a voltage-controlled
PWM generator. A voltage ranging from
0V to 1V on the MOD input pin linearly
varies the duty cycle of the output clock
from 5% to 95%. This device is chosen because it keeps its output clocking at all times. The duty cycle never
reaches 0% or 100% duty cycle, since
a DC signal would not pass through
the transformer. The output frequency
can range up to 1MHz and is easily
VISO
DC OUT
½ LTC6256
+
VISO
B4
τ = 10ms
0.22µF
VISO
10k
T1
780µH
780µH
–
+
VISO
LT1719
10k
OPTIONAL
CMOS
BUFFER
VISO
B3
+
49.9k
30.1k
½ LTC6256
–
OPTIONAL
CMOS
BUFFER
49.9k
τ = 10ms
OUT
LTC6992-2
V+
GND
0.22µF
250kHz ISOLATED PWM
ISOLATED
1kHz PWM
5% TO 95%
DUTY CYCLE
MOD
0.1µF
τ = 5ms
VISO
280k
0.47µF
500V
ISOLATION BARRIER
PRIMARY GROUND
T1: COILCRAFT WB1010-SM
SECONDARY GROUND
SET
RSET
787k
For accurate duty cycle control, the amplitudes of the two square waves must be the
same so the power supply voltage for the
LTC6992-2 is the same supply used for the
controller generating the input PWM signal.
The LTC6992-2 has 20m A of output current
drive and can directly drive the primary
winding of the isolation transformer.
The 500ms time constant network on
the control source PWM signal makes
duty cycle changes occur at a slow rate.
Amplifier U1A is an optional circuit function that can speed up the response time of
the circuit to duty cycle changes by a factor of 10. This function is described in the
section “Circuit Enhancements,” below.
CONTROL SIGNALS
ON THE ISOLATED SIDE
–
49.9k
required to force the average voltages,
and therefore the duty cycles, of the two
PWM signals to be exactly the same.
0.1µF
DIV
1kHz PWM
1M
Figure 3. Isolated side. Simply buffering the filtered average of the 250kHz PWM signal on the isolated side
provides a DC control signal. A second TimerBlox circuit can be used to reconstruct the original 1kHz PWM
signal with the same duty cycle as the control source signal.
On the isolated side of the transformer is
an LT1719 comparator. This comparator
converts the signal across the secondary
of the transformer to a 250kHz square
wave. This square wave can be filtered
and simply buffered with an op amp
to provide an isolated DC control voltage that moves proportionally to the
duty cycle of the original PWM signal.
If a reconstructed replica of the 1kHz
input PWM signal is required on the isolated side, simply add another LTC6992-2
PWM circuit, which is resistor programmed
to output a 1kHz PWM signal. An integrator can be used here, in the same fashion as on the nonisolated side, to servo
the output duty cycle to match that of
October 2011 : LT Journal of Analog Innovation | 41
A possible drawback to this circuit is the long time constant and resulting slow response
time to any changes in the duty cycle of the 1kHz control source PWM signal. The
amplifier circuit shown in Figure 5 allows the 250kHz PWM signal to respond nearly
instantly to any changes in the 1kHz control PWM despite the slow filter response time.
CIRCUIT ENHANCEMENTS
Improving Duty Cycle Accuracy
One important requirement for an
accurate match of the two duty cycles
is that the amplitude of the PWM signals
are exactly the same. Lightly loaded
CMOS outputs swing virtually all the way
between ground and the supply rail.
For more precise matching of the amplitudes of the two PWM signals, some
inexpensive CMOS logic buffers, B1 and
B2 in Figure 2 and B3 and B4 in Figure 3
on the isolated side, can be used on each
square wave signal to force the amplitudes
to be identical. Two like buffers powered from the same supply with the same
current loading will produce matched
output levels. Any supply voltage variation moves each of the two compared
signals the same amount for a good
measure of supply variation insensitivity.
Figure 4 shows the duty cycle difference between the source-side PWM and
C2
10µF
τ2 = R2 • C2
R2
49.9k
V+
4
3
DUTY CYCLE ERROR (%)
the 250kHz comparator output square
wave. Once again the average voltages,
and therefore the duty cycles, of the two
square waves are forced to be the same.
PWM
C1
10µF
SLOW EXPONENTIAL
AVERAGE VALUE INPUT
½ LTC6256
+
1
0
WITH BUFFERS
–1
–2
–3
–4
0
10 20 30 40 50 60 70 80 90 100
INPUT DUTY CYCLE (%)
Figure 4. Using simple CMOS buffers to match the
amplitudes of all PWM signals can reduce duty cycle
error to less than 1%.
the replicate isolated-side PWM—results
are shown with and without the
amplitude-matching logic buffers.
Anticipator Amplifier Predicts and
Speeds Response to the Final Value
A possible drawback to this circuit
is the long time constant and resulting slow response time to any changes
in the duty cycle of the 1kHz control
source PWM signal. The amplifier circuit
shown in Figure 5 allows the 250kHz
PWM signal to respond nearly instantly
to any changes in the 1kHz control
PWM despite the slow filter response time.
Figure 5. Anticipator amplifier circuit speeds
up step response by a factor of 10.
–
R1
49.9k
WITHOUT BUFFERS
2
OUTPUT
Circuit operation relies on knowing the
exact time constant of the exponentially
responding input signal, t1, which is set at
500ms by R1 and C1. Any step change in
duty cycle of the PWM input signal creates
a voltage at the plus input of the amplifier that changes from an initial voltage,
Vi, to a final voltage, Vf, in an exponential fashion per the familiar equation:
VIN = Vf − ( Vf − Vi ) • e
−t τ 1
The time domain step response at the
output of this circuit can be found by
the following series of equations:
VOUT = VIN + R2 • IC2( t)
IC2( t) = C2 •
dVIN
dt
Recall from the math that:
dae x
dx
= ae x •
dt
dt
so
dVIN
−1
−t τ
= − ( Vf − Vi ) • e 1 •
τ1
dt
1
−t τ 1
= ( Vf − Vi ) • e
τ1
continued on page 43
DUTY CYCLE
CONTROL
SIGNAL
1V/DIV
90%
10%
FAST OUTPUT
1V/DIV
SLOW
FILTERED
INPUT
1V/DIV
τ1 = R1 • C1
Figure 6. The anticipator output moves nearly instantly
to the final value of a slow changing exponential input
signal. Input change is a 10% to 90% duty cycle step.
1s/DIV
42 | October 2011 : LT Journal of Analog Innovation
product briefs
Product Briefs
OP AMP DRIVES SAR ADCs TO TRUE
ZERO ON A SINGLE 5V SUPPLY
The LTC6360 is a very low noise, high
speed amplifier that can drive to 0V while
maintaining high linearity on a single
5V supply. The LTC6360’s integrated
ultralow noise charge pump provides
an internal negative rail, eliminating the
need for a negative supply. Compared to
typical rail-to-rail output single-supply
amplifiers that can only swing to within
a few hundred millivolts of ground, the
LTC6360 provides improved linearity
and dynamic range in applications that
benefit from a true zero output swing.
The LTC6360 achieves outstanding precision and is ideal for driving 16- and
18-bit SAR ADCs (successive approximation register analog-to-digital converters).
=
dVIN
dt
1
( Vf − Vi ) • e−t
τ1
VOUT = Vf − ( Vf − Vi ) • e
τ1
−t τ 1
1
−t
+R2 • C2 • ( Vf − Vi ) • e
τ1
The closed loop gain of this stage
increases directly with frequency and is
inherently unstable. Frequency response
shaping is accomplished in Figure 2
via R3 and C3. The low frequency step
response is still dominated by R2 and C2.
τ1
If t2 (R2C2) is exactly equal
to t1 (R1C1) then:
VOUT = Vf − ( Vf − Vi ) • e
−t τ 1
+ ( Vf − Vi ) • e
The LTC6360 is available in a compact
3mm × 3mm, 8-pin leadless DFN package and an 8-pin MSOP package with
exposed pad and operates over a
–40°C to 125°C temperature range.
This look-ahead response drives the
duty cycle servo integrator in Figure 2 to
quickly change the 250kHz PWM generator
to its final value without waiting for the
500ms time constant filter to get there.
(TimerBlox, continued from page 42)
IC2( t) = C2 •
Input offset voltage is less than 250µV max,
and noise is only 2.3nV/√Hz, providing
excellent dynamic range. The device
settles to 16-bits in 150ns, and achieves a
closed loop –3dB bandwidth of 250MHz.
Harmonic distortion (HD2/HD3) is
–103dBc/–109dBc at fIN = 40kHz. The
LTC6360 is unity gain stable, allowing it to be used as a buffer to achieve
the lowest output noise. The output is
designed to drive a series 10Ω resistor and
330pF capacitor filter network, although
larger load capacitances can be driven.
−t τ 1
VOUT = Vf
When the input starts to change at an
exponential rate, the circuit extrapolates
the final value and jumps there instantly.
ULTRALOW NOISE AND SPURIOUS
0.37GHZ TO 5.7GHZ INTEGER-N
SYNTHESIZER WITH INTEGRATED VCO
The LTC6946 is a high performance, low
noise, 5.7GHz phase-locked loop (PLL)
with a fully integrated VCO, including
a reference divider, phase-frequency
detector (PFD) with phase-lock indicator, ultralow noise charge pump, integer
feedback divider, and VCO output divider.
The charge pump contains selectable
high and low voltage clamps useful for
VCO monitoring. The integrated low
noise VCO uses no external components. It is internally calibrated to the
correct output frequency with no external system support. The part features
a buffered, programmable VCO output
divider with a range of 1 through 6,
providing a wide frequency range. n
CONCLUSION
Generating control signals across an
isolation barrier from a low frequency
PWM control source can be implemented
by up-shifting the PWM frequency. The
LTC6992-2 PWM TimerBlox function
easily handles frequency scaling with
simple resistor programmability. Op
amp integrators ensure that the duty
cycle control information is accurately
reproduced on the isolated side. n
Figure 6 shows the quick response to a
step change in control signal duty cycle
from 10% to 90%. The anticipated output
arrives at the final voltage in about 200ms,
ten times faster than the two to three
seconds for the input signal to fully settle.
October 2011 : LT Journal of Analog Innovation | 43
highlights from circuits.linear.com
LOADPWR = I • V
0.1Ω
1%
MOTOR CONTROL VOLTAGE
0VDC TO 5VDC
0A TO ±2.2A
5V
MOTOR PROTECTION/REGULATION
The LTC2991 is used to monitor system temperatures, voltages and
currents. Through the I2C serial interface, the eight monitors can individually
measure supply voltages and can be paired for differential measurements
of current sense resistors or temperature sensing transistors. Additional
measurements include internal temperature and internal VCC.
circuits.linear.com/513
2-WIRE I2C
INTERFACE
VCC
V1
V2
SDA
SCL LTC2991
ADR0
ADR1
ADR2
MMBT3904
V3
V4
MOTOR
TMOTOR
GND V5 TO V8
4
TAMBIENT
OTHER APPS
VOLTAGE, CURRENT AND TEMPERATURE CONFIGURATION:
CONTROL REGISTER: 0x06: 0xA1
REG 1A, 1B: 0.0625°C/LSB
TAMBIENT
REG 0A, 0B: 305.18µV/LSB
VMOTOR
REG 0C, 0D: 194.18µA/LSB
IMOTOR
REG 1A, 1B: 0.0625°C/LSB
TMOTOR
REG 1C, 1D: 2.5V + 305.18µV/LSB
VCC
CIRCUIT FAULT PROTECTION WITH VERY FAST LATCHING LOAD DISCONNECT
The LT6108 is a complete high side current sense device that incorporates
a precision current sense amplifier, an integrated voltage reference and a
comparator. Two versions of the LT6108 are available. The LT6108-1 has a latching
comparator and the LT6108-2 has a non-latching comparator. In addition, the
current sense amplifier and comparator inputs and outputs are directly accessible.
The amplifier gain and comparator trip point are configured by external resistors.
circuits.linear.com/508
0.1Ω
12V
1k
6.2V*
IRF9640
TO LOAD
0.1µF
100Ω
SENSEHI SENSELO
V+
3.3V
1k
10k
VOUT
6.04k
EN/RST
RESET
250mA DISCONNECT
2N2700
OUTA
LT6108-1
OUTC
V–
INC
1.6k
*CMH25234B
TO LOAD
MPEXT
Li-Ion
+
C1
4.7µF
R1
2.21M
VIN
GATE
VOUT
CPO
PFI
LI-ION BACKUP SUPPLY
The LTC3226 is a 2-cell series supercapacitor charger with a backup
PowerPath controller. It includes a charge pump supercapacitor
charger with programmable output voltage, a low dropout regulator,
and a power-fail comparator for switching between normal and backup
modes. The constant input current supercapacitor charger is designed
to charge two supercapacitors in series to a resistor-programmable
output voltage from a 2.5V to 5.3V input supply. The charger input
current limit is programmable by an external resistor at up to 315mA.
circuits.linear.com/496
R2
1.21M
5V
CSC
1.2F
VMID
LTC3226
CFLY
2.2µF
H/L
RPROG
33.2k
C+
CPO_FB
C–
LDO_FB
RST_FB
RST
PFO
CAPGOOD
EN_CHG
PROG
GND
R4
3.83M
R6
1.21M
R3
255k
47µF
R4
80.6k
470k
470k
470k
µP
CSC: CAP-XX HS230
MPEXT: VISHAY Si2333
L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode, Hot Swap, LTspice, PolyPhase, TimerBlox and µModule are registered trademarks, and PowerPath, and Stage Shedding are trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
© 2011 Linear Technology Corporation/Printed in U.S.A./52.5K
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(408) 432-1900
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