IRFF120 Data Sheet March 1999 6.0A, 100V, 0.300 Ohm, N-Channel Power MOSFET 1563.3 Features • 6.0A, 100V This N-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFET designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. • rDS(ON) = 0.300Ω • Single Pulse Avalanche Energy Rated • SOA is Power Dissipation Limited • Nanosecond Switching Speeds • Linear Transfer Characteristics • High Input Impedance • Related Literature - TB334, “Guidelines for Soldering Surface Mount Components to PC Boards” Formerly developmental type TA09594. Ordering Information PART NUMBER File Number Symbol PACKAGE BRAND D IRFF120 TO-205AF IRFF120 NOTE: When ordering, use the entire part number. G S Packaging JEDEC TO-205AF SOURCE DRAIN (CASE) GATE 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 IRFF120 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg IRFF120 100 100 6.0 24 ±20 20 0.16 36 -55 to 150 UNITS V V A A V W W/oC mJ oC 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. TC = 25oC, Unless Otherwise Specified Electrical Specifications MIN TYP MAX UNITS Drain to Source Breakdown Voltage PARAMETER SYMBOL BVDSS ID = 250µA, VGS = 0V (Figure 10) 100 - - V Gate Threshold Voltage VGS(TH) VGS = VDS , ID = 250µA 2.0 - 4.0 V - - 25 µA - - 250 µA 6.0 - - A Zero Gate Voltage Drain Current IDSS TEST CONDITIONS VDS = Rated BVDSS , VGS = 0V VDS = 0.8 x Rated BVDSS , VGS = 0V, TC = 125oC On-State Drain Current (Note 2) ID(ON) Gate to Source Leakage Current IGSS Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time rDS(ON) gfs td(ON) Rise Time tr Turn-Off Delay Time td(OFF) Fall Time tf Total Gate Charge (Gate to Source + Gate to Drain) Qg(TOT) Gate to Source Charge Qgs VDS > ID(ON) x rDS(ON)MAX, VGS = 10V VGS = ±20V - - ±100 nA ID = 3.0A, VGS = 10V (Figures 8, 9) - 0.25 0.300 Ω VDS > ID(ON) x rDS(ON)MAX, ID = 3.0A (Figure 12) 1.5 2.9 - S VDD ≅ 0.5 x Rated BVDSS, ID = 6.0A, RG = 9.1Ω, VGS =10V (Figures 17, 18), RL = 8Ω for VDSS = 50V, RL = 6.3Ω for VDSS = 40V, MOSFET Switching Times are Essentially Independent of Operating Temperatures - 20 40 ns - 37 70 ns - 50 100 ns - 35 70 ns VGS = 10V, ID = 6.0A, VDS = 0.8 x Rated BVDSS (Figures 14, 19, 20) Gate Charge is Essentially Independent of Operating Temperature - 10 15 nC - 6.0 - nC - 4.0 - nC VDS = 25V, VGS = 0V, f = 1MHz (Figure 11) - 450 - pF Gate to Drain (“Miller”) Charge Qgd Input Capacitance CISS Output Capacitance COSS - 20 - pF Reverse Transfer Capacitance CRSS - 50 - pF - 5.0 - nH - 15 - nH - - 6.25 oC/W - - 175 oC/W Internal Drain Inductance LD Measured from the Drain Lead, 5.0mm (0.2in) from Header to Center of Die Internal Source Inductance LS Measured from the Source Lead, 5.0mm (0.2in) from Header to Source Bonding Pad Modified MOSFET Symbol Showing the Internal Devices Inductances D LD G LS S Thermal Resistance, Junction to Case RθJC Thermal Resistance, Junction to Ambient RθJA 2 Free Air Operation IRFF120 Source to Drain Diode Specifications PARAMETER SYMBOL Continuous Source to Drain Current ISD Pulse Source to Drain Current (Note 3) ISM TEST CONDITIONS MIN TYP MAX UNITS - - 6.0 A - - 24 A TJ = 25oC, ISD = 6.0A, VGS = 0V (Figure 13) - - 2.5 V TJ = 150oC, ISD = 6.0A, dISD/dt = 100A/µs TJ = 150oC, ISD = 6.0A, dISD/dt = 100A/µs - 230 - ns - 1.0 - µC Intrinsic Turn-on Time is Negligible, Turn-On Speed is Substantially controlled by LS + LD - - - - Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Rectifier D G S Source to Drain Diode Voltage (Note 2) VSD Reverse Recovery Time trr Reverse Recovery Charge QRR Forward Turn-On Time tON NOTES: 2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%. 3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 25V, starting TJ = 25oC, L = 1.5mH, RG = 25Ω, peak IAS = 6.0A (Figures 15, 16). Typical Performance Curves Unless Otherwise Specified 6.0 ID , DRAIN CURRENT (A) 1.0 0.8 0.6 0.4 0.2 0 0 50 100 4.8 3.6 2.4 1.2 0 25 150 50 TC , CASE TEMPERATURE (oC) 75 100 150 125 TC , CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 1.0 ZθJC, NORMALIZED THERMAL IMPEDANCE POWER DISSIPATION MULTIPLIER 1.2 0.5 0.2 PDM 0.1 0.1 0.05 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC 0.02 0.01 SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 t1, RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 3 1 10 IRFF120 Typical Performance Curves Unless Otherwise Specified (Continued) 20 50.0 VGS = 10V 80µs PULSE TEST ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 10µs 100µs 10.0 1ms 1.0 OPERATION IN THIS AREA IS LIMITED BY rDS(ON) 10ms 100ms 16 VGS = 8V 12 VGS = 7V 8 VGS = 6V VGS = 5V 4 DC TJ = MAX RATED 0.1 1.0 10.0 100.0 VGS = 4V 0 200.0 0 10 20 30 40 VDS, DRAIN TO SOURCE VOLTAGE (V) VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA 20 VGS = 8V 80µs PULSE TEST VGS = 7V VGS = 10V ID, DRAIN CURRENT (A) 8 VGS = 9V VGS = 6V 6 4 VGS = 5V 2 VGS = 4V VDS > ID(ON) x rDS(ON)MAX 2 1 4 3 16 25oC 12 -55oC 8 4 0 5 0 2 4 6 8 VGS , GATE TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 6. SATURATION CHARACTERISTICS 10 FIGURE 7. TRANSFER CHARACTERISTICS 2.50 2µs PULSE TEST NORMALIZED DRAIN TO SOURCE ON REISITANCE rDS(ON), DRAIN TO SOURCE ON RESISTANCE (Ω) 0.8 125oC 80µs PULSE TEST 0 0 50 FIGURE 5. OUTPUT CHARACTERISTICS ID(ON), ON-STATE DRAIN CURRENT (A) 10 VGS = 9V 0.6 VGS = 10V 0.4 VGS = 20V 0.2 0 VGS = 10V ID = 3A 2.00 1.50 1.00 0.50 0 0 10 20 ID , DRAIN CURRENT (A) 30 NOTE: Heating effect of 2µs pulse is minimal. FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 4 40 -40 0 40 80 120 TJ , JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE IRFF120 Typical Performance Curves Unless Otherwise Specified (Continued) 1.25 1000 1.15 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGD 800 C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250µA 1.05 0.95 0.85 600 CISS 400 COSS 200 CRSS 0.75 -40 0 40 80 0 120 0 10 TJ , JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE -55oC 25oC 3 125oC 2 1 0 0 4 40 50 100 80µs PULSE TEST 4 30 FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE ISD, SOURCE TO DRAIN CURRENT (A) gfs, TRANSCONDUCTANCE (S) 5 20 VDS , DRAIN TO SOURCE VOLTAGE (V) 8 12 16 5 2 10 150oC 5 25oC 2 1.0 0 20 1 ID , DRAIN CURRENT (A) FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE 20 VGS, GATE TO SOURCE (V) ID = 6A VDS = 50V 15 VDS = 20V VDS = 80V 10 5 0 0 4 8 12 16 20 Qg(TOT) , TOTAL GATE CHARGE (nC) FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE 5 2 VSD, SOURCE TO DRAIN VOLTAGE (V) 3 IRFF120 Test Circuits and Waveforms BVDSS VDS tP VDS L IAS VARY tP TO OBTAIN VDD + RG REQUIRED PEAK IAS - VDD DUT VGS 0 tP 0V IAS tAV 0.01Ω FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORM tON tOFF td(ON) td(OFF) tf tr VDS RL 90% + RG - 10% 10% 0 VDD 90% 90% DUT VGS 0 50% 50% PULSE WIDTH 10% VGS FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS VDS (ISOLATED SUPPLY) CURRENT REGULATOR VDD Qg(TOT) 12V BATTERY 0.2µF SAME TYPE AS DUT 50kΩ Qgd Qgs 0.3µF D IG(REF) VDS DUT G 0 S 0 IG CURRENT SAMPLING RESISTOR VDS ID CURRENT SAMPLING RESISTOR FIGURE 19. GATE CHARGE TEST CIRCUIT 6 VGS IG(REF) 0 FIGURE 20. GATE CHARGE WAVEFORMS IRFF120 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 7 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029