EL8100, EL8101 ® Data Sheet April 26, 2005 200MHz Rail-to-Rail Amplifiers Features The EL8100 and EL8101 represent single rail-to-rail amplifiers with a -3dB bandwidth of 200MHz and slew rate of 200V/µs. Running off a very low 2mA supply current, the EL8100 and EL8101 also feature inputs that go to 0.15V below the VS- rail. • 200MHz -3dB bandwidth The EL8100 includes a fast-acting disable/power-down circuit. With a 25ns disable and a 200ns enable, the EL8100 is ideal for multiplexing applications. • Rail-to-rail output The EL8100 and EL8101 are designed for a number of general purpose video, communication, instrumentation, and industrial applications. The EL8100 is available in 8-pin SO and 6-pin SOT-23 packages and the EL8101 is available in a 5-pin SOT-23 package. All are specified for operation over the -40°C to +85°C temperature range. Ordering Information PART NUMBER FN7103.7 • 200V/µs slew rate • Low supply current = 2mA • Supplies from 3V to 5.0V • Input to 0.15V below VS• Fast 25ns disable (EL8100 only) • Low cost • Pb-Free available (RoHS compliant) Applications • Video amplifiers • Portable/hand-held products PACKAGE TAPE & REEL PKG. DWG. # EL8100IS 8-Pin SO - MDP0027 EL8100IS-T7 8-Pin SO 7” MDP0027 EL8100IS-T13 8-Pin SO 13” MDP0027 EL8100ISZ (See Note) 8-Pin SO (Pb-Free) - MDP0027 EL8100ISZ-T7 (See Note) 8-Pin SO (Pb-Free) 7” EL8100ISZ-T13 (See Note) 8-Pin SO (Pb-Free) 13” MDP0027 EL8100IW-T7 6-Pin SOT-23 7” (3K pcs) MDP0038 EL8100IW-T7A 6-Pin SOT-23 7” (250 pcs) MDP0038 EL8100IWZ-T7 (See Note) 6-Pin SOT-23 (Pb-free) 7” (3K pcs) MDP0038 EL8100IWZ-T7A (See Note) 6-Pin SOT-23 (Pb-free) 7” (250 pcs) MDP0038 EL8101IW-T7 5-Pin SOT-23 7” (3K pcs) MDP0038 EL8101IW-T7A 5-Pin SOT-23 7” (250 pcs) MDP0038 EL8101IWZ-T7 (See Note) 5-Pin SOT-23 (Pb-Free) 7” (3K pcs) MDP0038 EL8101IWZ-T7A (See Note) 5-Pin SOT-23 (Pb-Free) 7” (250 pcs) MDP0038 • Communications devices Pinouts EL8100 (8-PIN SO) TOP VIEW NC 1 MDP0027 IN- 2 IN+ 3 8 ENABLE + VS- 4 1 6 OUT 5 NC EL8100 (6-PIN SOT-23) TOP VIEW OUT 1 NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C. 7 VS+ VS- 2 6 VS+ + - IN+ 3 5 ENABLE 4 IN- EL8101 (5-PIN SOT-23) TOP VIEW OUT 1 VS- 2 IN+ 3 5 VS+ + 4 IN- CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2003-2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. EL8100, EL8101 Absolute Maximum Ratings (TA = 25°C) Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +125°C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C Supply Voltage from VS+ to VS- . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . VS+ +0.3V to VS- -0.3V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VS+ = 5V, VS- = GND, TA = 25°C, VCM = 2.5V, RL to 2.5V, AV = 1, Unless Otherwise Specified DESCRIPTION CONDITIONS MIN TYP MAX UNIT -6 -0.8 +6 mV INPUT CHARACTERISTICS VOS Offset Voltage TCVOS Offset Voltage Temperature Coefficient Measured from TMIN to TMAX IB Input Bias Current VIN = 0V IOS Input Offset Current VIN = 0V TCIOS Input Bias Current Temperature Coefficient Measured from TMIN to TMAX CMRR Common Mode Rejection Ratio VCM = -0.15V to +3.5V CMIR Common Mode Input Range RIN Input Resistance CIN Input Capacitance AVOL Open Loop Gain -2.1 3 µV/°C -1.5 µA 0.2 70 µA 2 nA/°C 90 dB VS- -0.15 Common Mode 0.55 VS+ -1.5 V 16 MΩ 0.5 pF 90 dB VOUT = +1.5V to +3.5V, RL = 150Ω to GND 80 dB 30 mΩ VOUT = +1.5V to +3.5V, RL = 1kΩ to GND 75 OUTPUT CHARACTERISTICS ROUT Output Resistance AV = +1 VOP Positive Output Voltage Swing RL = 1kΩ 4.85 4.9 V RL = 150Ω 4.6 4.7 V VON Negative Output Voltage Swing RL = 150Ω 100 150 mV RL = 1kΩ 35 50 mV IOUT Linear Output Current 65 mA ISC (source) Short Circuit Current RL = 10Ω 60 70 mA ISC (sink) Short Circuit Current RL = 10Ω 120 140 mA VS+ = 4.5V to 5.5V 75 100 dB POWER SUPPLY PSRR Power Supply Rejection Ratio IS-ON Supply Current - Enabled 2 IS-OFF Supply Current - Disabled 30 µA 2.4 mA ENABLE (EL8100 ONLY) tEN Enable Time 200 ns tDS Disable Time 25 ns VIH-ENB ENABLE Pin Voltage for Power-up 0.8 V VIL-ENB ENABLE Pin Voltage for Shut-down 2 V 2 FN7103.7 April 26, 2005 EL8100, EL8101 Electrical Specifications PARAMETER VS+ = 5V, VS- = GND, TA = 25°C, VCM = 2.5V, RL to 2.5V, AV = 1, Unless Otherwise Specified (Continued) DESCRIPTION CONDITIONS MIN TYP MAX UNIT IIH-ENB ENABLE Pin Input Current High 8.6 µA IIL-ENB ENABLE Pin Input for Current Low 0.01 µA AV = +1, RF = 0Ω, CL = 5pF 200 MHz AV = -1, RF = 1kΩ, CL = 5pF 90 MHz AV = +2, RF = 1kΩ, CL = 5pF 90 MHz AV = +10, RF = 1kΩ, CL = 5pF 10 MHz AC PERFORMANCE BW -3dB Bandwidth BW ±0.1dB Bandwidth AV = +1, RF = 0Ω, CL = 5pF 20 MHz Peak Peaking AV = +1, RF = 1kΩ, CL = 5pF 1 dB GBWP Gain Bandwidth Product 100 MHz PM Phase Margin RL = 1kΩ, CL = 5pF 55 ° SR Slew Rate AV = 2, RL = 100Ω, VOUT = 0.5V to 4.5V 200 V/µs tR Rise Time 2.5VSTEP, 20% - 80% 8 ns tF Fall Time 2.5VSTEP, 20% - 80% 7 ns OS Overshoot 200mV step 10 % tPD Propagation Delay 200mV step 2 ns tS 0.1% Settling Time 200mV step 20 ns dG Differential Gain AV = +2, RF = 1kΩ, RL = 150Ω 0.035 % dP Differential Phase AV = +2, RF = 1kΩ, RL = 150Ω 0.05 ° eN Input Noise Voltage f = 10kHz 10 nV/√Hz iN+ Positive Input Noise Current f = 10kHz 1 pA/√Hz iN- Negative Input Noise Current f = 10kHz 0.8 pA/√Hz 160 Pin Descriptions PIN EL8100IS EL8100IW EL8101IW 1 NAME FUNCTION NC Not connected 2 4 4 IN- Inverting input 3 3 3 IN+ non-inverting input 4 2 2 VS- Negative power supply NC Not connected 5 6 1 1 OUT Amplifier output 7 6 5 VS+ Positive power supply 8 5 3 ENABLE Enable and disable input FN7103.7 April 26, 2005 EL8100, EL8101 Simplified Schematic Diagram VS+ I1 I2 Q5 Q7 R2 Q1 IN+ R8 VBIAS1 Q6 R3 R1 R7 R6 Q2 DIFFERENTIAL TO SINGLE ENDED DRIVE GENERATOR IN- VBIAS2 Q3 OUT Q4 Q8 R4 R5 R9 VS- Typical Performance Curves GAIN (dB) 2 4 VS=5V AV=1 RL=1kΩ CL=5pF 2 VOP-P=200mV GAIN (dB) 4 0 VOP-P=1V -2 -6 100K 1M 10M RL=330Ω 0 RL=1kΩ -2 RL=100Ω VOP-P=2V -4 VS=5V AV=1 CL=5pF -4 100M -6 100K 1G 1M 10M FIGURE 1. FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGE LEVELS 4 AV=2 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 2 AV=1 0 -2 AV=5 -4 -6 100K AV=10 1M 10M 100M 1G FREQUENCY (Hz) FIGURE 3. Small Signal Frequency Response for Various Non-Inverting Gains 4 1G FIGURE 2. Small Signal Frequency Response for Various RLOAD 4 VS=5V RL=1kΩ CL=5pF 100M FREQUENCY (Hz) FREQUENCY (Hz) 2 VS=5V RL=1kΩ CL=5pF RF=1kΩ AV=-5 0 AV=-2 -2 AV=-10 -4 -6 100K 1M 10M 100M 1G FREQUENCY (Hz) FIGURE 4. Small Signal Frequency Response for Various Inverting Gains FN7103.7 April 26, 2005 EL8100, EL8101 Typical Performance Curves (Continued) 10 CL=15pF CL=56pF 3 CL=11.5pF 1 CL=8.3pF 8 GAIN (dB) GAIN (dB) 5 CL=5pF -1 VS=5V -3 AV=1 RL=1kΩ VOP-P=200mV -5 100K 1M 6 CL=15pF 4 CL=1.5pF 10M CL=35pF 100M 0 100K 1G CL=5pF VS=5V AV=2 RL=1kΩ RF=RG=1kΩ 2 1M 10M 100M 1G FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 5. Small Signal Frequency Response for Various CL FIGURE 6. Small Signal Frequency Response for Various CL 10 110 8 70 GAIN (dB) GAIN (dB) 6 RF=RG=500Ω 4 VS=5V AV=2 RL=1kΩ CL=5pF 0 100K 315 RL=150Ω 30 225 RL=150Ω -10 RL=1kΩ -50 1M 10M 100M 1G 135 -90 1K 45 100K 10K FREQUENCY (Hz) 230 -30 190 BANDWIDTH (MHz) CMRR (dB) 210 -50 -70 -90 100M FREQUENCY (Hz) FIGURE 9. Common-Mode Rejection Ratio vs Frequency 5 -45 1G AV=1 170 150 130 110 90 RL=1kΩ CL=5pF 70 10M 100M FIGURE 8. Open Loop Gain and Phase vs Frequency -10 1M 10M 1M FREQUENCY (Hz) FIGURE 7. Small Signal Frequency Response for Various RF and RG -110 100K PHASE (°) RF=RG=1kΩ RF=RG=2kΩ 2 405 RL=1kΩ 50 3 3.5 AV=2 4.5 4 5 5.5 VS (V) FIGURE 10. Small Signal Bandwidth vs Supply Voltage FN7103.7 April 26, 2005 EL8100, EL8101 Typical Performance Curves (Continued) 2.5 2 10 PEAKING (dB) IMPEDANCE (Ω) 100 1 0.1 1.5 1 AV=1 RL=1kΩ CL=5pF 0.5 0.01 10K 100K 1M 10M 0 100M 3 4 3.5 FREQUENCY (Hz) -10 -45 -30 -55 PSRR- -70 5 5.5 FIGURE 12. Small Signal Peaking vs Supply Voltage DISTORTION (dBc) PSRR (dB) FIGURE 11. Output Impedance vs Frequency -50 4.5 VS (V) PSRR+ VS=5V RL=1kΩ CL=5pF AV=2 @1 HD2 MHz @10 HD3 Hz HD3@5M -65 -75 z HD2@5MH HD2@ -85 -90 z 0MH 1MHz HD3@1MHz -110 1K 10K 100K 1M 10M -95 100M 1 2 3 FIGURE 13. Power Supply Rejection Ratio vs Frequency GAIN (dB) -30 -30 VS=5V AV=1 RL=1kΩ CL=5pF VS=5V RL=1kΩ VO=1VP-P for AV=1 VO=2VP-P for AV=2 -40 -50 -70 -90 -110 1K -50 -60 =2 AV 2@ HD -70 -80 100K 1M 10M 100M 1G FREQUENCY (Hz) FIGURE 15. Disabled Output Isolation Frequency Response 6 -100 2@ HD =1 AV 2 AV= 3@ D H HD3@AV=1 -90 10K 5 FIGURE 14. Harmonic Distortion vs Output Voltage DISTORTION (dBc) -10 4 VOP-P (V) FREQUENCY (Hz) 1 10 40 FREQUENCY (MHz) FIGURE 16. Harmonic Distortion vs Frequency FN7103.7 April 26, 2005 EL8100, EL8101 Typical Performance Curves (Continued) -60 1K DISTORTION (dBc) -65 HD 3@ -70 -75 HD -80 AV = 2 HD2@A =1 V 3@ A V= AV =2 VOLTAGE NOISE (nV/√Hz) CURRENT NOISE (pA/√Hz) H D 2@ 1 -85 -90 VS=5V VO=1VP-P for AV=1 VO=2VP-P for AV=2 -95 -100 100 1K 2K 100 IN+ 1 IN0.1 10 100 1K 10K 100K 1M 10M FREQUENCY (Hz) RLOAD (Ω) FIGURE 17. Harmonic Distortion vs Load Resistance eN 10 FIGURE 18. Voltage and Current Noise vs Frequency VS=5V, AV=5, RL=1kΩ to 2.5V VS=5V, AV=1, RL=1kΩ to 2.5V 5 5 2.5 2.5 0 0 10ns/DIV 2µs/DIV FIGURE 19. Large Signal Transient Response FIGURE 20. Output Swing VS=5V, AV=1, RL=1kΩ to 2.5V CL=5pF VS=5V, AV=5, RL=1kΩ to 2.5V 5 2.6 2.5 2.5 2.4 0 10ns/DIV FIGURE 21. Small Signal Transient Response 7 2µs/DIV FIGURE 22. Output Swing FN7103.7 April 26, 2005 EL8100, EL8101 Typical Performance Curves (Continued) VS=±2.5V, AV=1, RL=1kΩ VS=±2.5V, AV=1, RL=1kΩ CH1 CH1 CH2 ENABLE INPUT CH2 VOUT OUTPUT CH1, CH2, 0.5V/DIV, M=20ns CH1, CH2, 1V/DIV, M=100ns FIGURE 23. Disabled Response FIGURE 24. Enabled Response JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1 0.9 1.2 POWER DISSIPATION (W) POWER DISSIPATION (W) 1.4 1 909mW 0.8 SO8 θJA=110°C/W 0.6 435mW 0.4 SOT23-5/6 θJA=230°C/W 0.2 0 ENABLE INPUT 0 25 0.8 0.7 625mW 0.6 0.5 0.3 0.2 SOT23-5/6 θJA=256°C/W 0.1 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 25. Package Power Dissipation vs Ambient Temperature Description of Operation and Application Information Product Description The EL8100, EL8101 are wide bandwidth, single supply, low power and rail-to-rail output voltage feedback operational amplifiers. Both amplifiers are internally compensated for closed loop gain of +1 of greater. Connected in voltage follower mode and driving a 1kΩ load, the EL8100, EL8101 have a -3dB bandwidth of 200MHz. Driving a 150Ω load, the bandwidth is about 130MHz while maintaining a 200V/us slew rate. The EL8100 is available with a power down pin to reduce power to 30µA typically while the amplifier is disabled. Input, Output and Supply Voltage Range The EL8100, EL8101 have been designed to operate with a single supply voltage from 3V to 5.0V. Split supplies can also be used as long as their total voltage is within 3V to 5.0V. 8 SO8 θJA=160°C/W 391mW 0.4 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 26. Package Power Dissipation vs Ambient Temperature The amplifiers have an input common mode voltage range from 0.15V below the negative supply (VS- pin) to within 1.5V of the positive supply (VS+ pin). If the input signal is outside the above specified range, it will cause the output signal to be distorted. The output of the EL8100, EL8101 can swing rail to rail. As the load resistance becomes lower, the ability to drive close to each rail is reduced. For the load resistor 1kΩ, the output swing is about 4.9V at a 5V supply. For the load resistor 150Ω, the output swing is about 4.6V. Choice of Feedback Resistor and Gain Bandwidth Product For applications that require a gain of +1, no feedback resistor is required. Just short the output pin to the inverting input pin. For gains greater than +1, the feedback resistor forms a pole with the parasitic capacitance at the inverting input. As this pole becomes smaller, the amplifier’s phase margin is reduced. This causes ringing in the time domain FN7103.7 April 26, 2005 EL8100, EL8101 and peaking in the frequency domain. Therefore, RF has some maximum value that should not be exceeded for optimum performance. If a large value of RF must be used, a small capacitor in the few Pico farad range in parallel with RF can help to reduce the ringing and peaking at the expense of reducing the bandwidth. As far as the output stage of the amplifier is concerned, the output stage is also a gain stage with the load. RF and RG appear in parallel with RL for gains other than +1. As this combination gets smaller, the bandwidth falls off. Consequently, RF also has a minimum value that should not be exceeded for optimum performance. For gain of +1, RF=0 is optimum. For the gains other than +1, optimum response is obtained with RF between 300Ω to 1kΩ. The EL8100, EL8101 have a gain bandwidth product of 100MHz. For gains ≥5, its bandwidth can be predicted by the following equation: Gain × BW = 100MHz on time is about 200ns. When disabled, the amplifier’s supply current is reduced to 30µA typically, thereby effectively eliminating the power consumption. The amplifier’s power down can be controlled by standard TTL or CMOS signal levels at the ENABLE pin. The applied logic signal is relative to VS- pin. Letting the ENABLE pin float or applying a signal that is less than 0.8V above VS- will enable the amplifier. The amplifier will be disabled when the signal at ENABLE pin is 2V above VS-. Output Drive Capability The EL8100, EL8101 do not have internal short circuit protection circuitry. They have a typical short circuit current of 70mA sourcing and 140mA sinking for the output is connected to half way between the rails with a 10Ω resistor. If the output is shorted indefinitely, the power dissipation could easily increase such that the part will be destroyed. Maximum reliability is maintained if the output current never exceeds ±40mA. This limit is set by the design of the internal metal interconnections. Video Performance Power Dissipation For good video performance, an amplifier is required to maintain the same output impedance and the same frequency response as DC levels are changed at the output. This is especially difficult when driving a standard video load of 150Ω, because the change in output current with DC level. Special circuitry has been incorporated in the EL8100, EL8101 to reduce the variation of the output impedance with the current output. This results in dG and dP specifications of 0.03% and 0.05°, while driving 150Ω at a gain of 2. Driving high impedance loads would give a similar or better dG and dP performance. With the high output drive capability of the EL8100, EL8101, it is possible to exceed the 125°C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if the load conditions or package types need to be modified for the amplifier to remain in the safe operating area. Driving Capacitive Loads and Cables The EL8100, EL8101 can drive 15pF loads in parallel with 1kΩ with less than 5dB of peaking at gain of +1. If less peaking is desired in applications, a small series resistor (usually between 5Ω to 50Ω) can be placed in series with the output to eliminate most peaking. However, this will reduce the gain slightly. If the gain setting is greater than 1, the gain resistor RG can then be chosen to make up for any gain loss which may be created by the additional series resistor at the output. When used as a cable driver, double termination is always recommended for reflection-free performance. For those applications, a back-termination series resistor at the amplifier’s output will isolate the amplifier from the cable and allow extensive capacitive drive. However, other applications may have high capacitive loads without a back-termination resistor. Again, a small series resistor at the output can help to reduce peaking. Disable/Power-Down The EL8100 can be disabled and placed its output in a high impedance state. The turn off time is about 25ns and the turn 9 The maximum power dissipation allowed in a package is determined according to: T JMAX – T AMAX PD MAX = -------------------------------------------θ JA Where: TJMAX = Maximum junction temperature TAMAX = Maximum ambient temperature θJA = Thermal resistance of the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or: For sourcing: V OUT PD MAX = V S × I SMAX + ( V S – V OUT ) × ---------------R L For sinking: PD MAX = V S × I SMAX + ( V OUT – V S - ) × I LOAD Where: VS = Total supply voltage ISMAX = Maximum quiescent supply current FN7103.7 April 26, 2005 EL8100, EL8101 VOUT = Maximum output voltage of the application RLOAD = Load resistance tied to ground ILOAD = Load current By setting the two PDMAX equations equal to each other, we can solve the output current and RLOAD to avoid the device overheat. and VIN2 is passed through to the output. The break-beforemake operation ensures that more than one amplifier isn’t trying to drive the bus at the same time. 5V VIN - 75Ω VOUT VS- 75Ω Power Supply Bypassing and Printed Circuit Board Layout 75Ω As with any high frequency device, a good printed circuit board layout is necessary for optimum performance. Lead lengths should be as sort as possible. The power supply pin must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to the ground plane, a single 4.7µF tantalum capacitor in parallel with a 0.1µF ceramic capacitor from VS+ to GND will suffice. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. In this case, the VS- pin becomes the negative supply rail. For good AC performance, parasitic capacitance should be kept to a minimum. Use of wire wound resistors should be avoided because of their additional series inductance. Use of sockets should also be avoided if possible. Sockets add parasitic inductance and capacitance that can result in compromised performance. Minimizing parasitic capacitance at the amplifier’s inverting input pin is very important. The feedback resistor should be placed very close to the inverting input pin. Strip line design techniques are recommended for the signal traces. VS+ + 1K 1K FIGURE 27. SYNC PULSE Remover 1V 0.5V VIN 0V 1V 0.5V VOUT 0V M = 10µs/DIV FIGURE 28. VIDEO SIGNAL +2.5V B 2MHz 1VP-P + 75Ω -2.5V Typical Applications VIDEO SYNC PULSE REMOVER Many CMOS analog to digital converters have a parasitic latch up problem when subjected to negative input voltage levels. Since the sync tip contains no useful video information and it is a negative going pulse, we can chop it off. Figure 27 shows a gain of 2 connections for EL8100, EL8101. Figure 28 shows the complete input video signal applied at the input, as well as the output signal with the negative going sync pulse removed. MULTIPLEXER Besides the normal power down usage, the ENABLE pin of the EL8100 can be used for multiplexing applications. Figure 29 shows two EL8100s with the outputs tied together, driving a back terminated 75Ω video load. A 2VP-P 2MHz sine wave is applied to Amp A and a 1VP-P 2MHz sine wave is applied to Amp B. Figure 30 shows the ENABLE signal and the resulting output waveform at VOUT. Observe the break-before-make operation of the multiplexing. Amp A is on and VIN1 is passed through to the output when the ENABLE signal is low and turns off in about 25ns when the ENABLE signal is high. About 200ns later, Amp B turns on 10 1K 1K 75Ω VOUT +2.5V A 2MHz 2VP-P 75Ω + - 75Ω -2.5V 1K 1K ENABLE FIGURE 29. TWO TO ONE MULTIPLEXER FN7103.7 April 26, 2005 EL8100, EL8101 RF 1kΩ 0V -0.5V ENABLE VIN -1.5V C1 RG 47µF 500Ω 5V RT 75Ω -2.5V 5V - R3 C3 470µF 75Ω VOUT + R1 10K 1V 75Ω 0V B A R2 10K -1V FIGURE 32. 5v SINGLE SUPPLY INVERTING VIDEO LINE DRIVER M = 50ns/DIV FIGURE 30. ENABLE SIGNAL SINGLE SUPPLY VIDEO LINE DRIVER 5V C1 47µF R1 10K RT 75Ω 4 3 2 1 AV = 2 0 -1 AV = -2 -2 -3 -4 -5 100K 1M 10M FREQUENCY (Hz) 100M 200M FIGURE 33. VIDEO LINE DRIVER FREQUENCY RESPONSE R3 C3 470µF 75Ω + 5 NORMALIZED GAIN (dB) The EL8100, EL8101 are wideband rail-to-rail output op amplifiers with large output current, excellent dG, dP, and low distortion that allow them to drive video signals in low supply applications. Figure 31 is the single supply non-inverting video line driver configuration and Figure 32 is the inverting video ling driver configuration. The signal is AC coupled by C1. R1 and R2 are used to level shift the input and output to provide the largest output swing. RF and RG set the AC gain. C2 isolates the virtual ground potential. RT and R3 are the termination resistors for the line. C1, C2 and C3 are selected big enough to minimize the droop of the luminance signal. VIN C2 220µF VOUT - R2 10K 75Ω RG 1kΩ RF 1kΩ C2 220µF FIGURE 31. 5v SINGLE SUPPLY NON INVERTING VIDEO LINE DRIVER All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 11 FN7103.7 April 26, 2005