HSP45102 ® Data Sheet September 6, 2005 12-Bit Numerically Controlled Oscillator Features The Intersil HSP45102 is Numerically Controlled Oscillator (NCO12) with 32-bit frequency resolution and 12-bit output. With over 69dB of spurious free dynamic range and worst case frequency resolution of 0.009Hz, the NCO12 provides significant accuracy for frequency synthesis solutions at a competitive price. • 33MHz, 40MHz Versions FN2810.8 • 32-Bit Frequency Control • BFSK, QPSK Modulation • Serial Frequency Load • 12-Bit Sine Output The frequency to be generated is selected from two frequency control words. A single control pin selects which word is used to determine the output frequency. Switching from one frequency to another occurs in one clock cycle, with a 6 clock pipeline delay from the time that the new control word is loaded until t3-he new frequency appears on the output. • Offset Binary Output Format • 0.009Hz Tuning Resolution at 40MHz • Spurious Frequency Components <-69dBc • Fully Static CMOS Two pins, P0-1, are provided for phase modulation. They are encoded and added to the top two bits of the phase accumulator to offset the phase in 90° increments. • Low Cost The 13-bit output of the Phase Offset Adder is mapped to the sine wave amplitude via the Sine ROM. The output data format is offset binary to simplify interfacing to D/A converters. Spurious frequency components in the output sinusoid are less than -69dBc. Applications The NCO12 has applications as a Direct Digital Synthesizer and modulator in low cost digital radios, satellite terminals, and function generators. • Related Products - HI5731 12-Bit, 100MHz D/A Converter • Pb-Free Plus Anneal Available (RoHS Compliant) • Direct Digital Synthesis • Modulation • PSK Communications Ordering Information PART NUMBER PART MARKING TEMP. RANGE (°C) PACKAGE PKG. DWG. # HSP45102SC-33 HSP45102SC-33 0 to 70 28 Ld SOIC M28.3 HSP45102SC-33Z (Note) HSP45102SC-33Z 0 to 70 28 Ld SOIC (Pb-free) M28.3 HSP45102SC-40 HSP45102SC-40 0 to 70 28 Ld SOIC M28.3 HSP45102SC-40Z (Note) HSP45102SC-40Z 0 to 70 28 Ld SOIC (Pb-free) M28.3 HSP45102SI-3396 28 Ld SOIC Tape and Reel M28.3 Block Diagram CLK PO-1 MSB/LSB SFTEN SD SCLK FREQUENCY CONTROL SECTION 32 32 PHASE ACCUMULATOR 13 PHASE OFFSET ADDER 13 SINE ROM 12 OUT0-11 LOAD TXFR ENPHAC SEL_L/M 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1999, 2004, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HSP45102 Pinout 28 LEAD PDIP, 28 LEAD SOIC TOP VIEW OUT6 1 28 OUT5 OUT7 2 27 OUT4 OUT8 3 26 OUT3 OUT9 4 25 OUT2 OUT10 5 24 OUT1 OUT11 6 23 OUT0 GND 7 22 VCC VCC 8 21 GND SEL_L/M 9 20 P0 SFTEN 10 19 P1 MSB/LSB 11 18 LOAD ENPHAC 12 17 TXFR SD 13 16 CLK SCLK 14 15 GND Pin Description NAME TYPE DESCRIPTION VCC +5V power supply pin. GND Ground P0-1 I Phase modulation inputs (become active after a pipeline delay of four clocks). A phase shift of 0, 90, 180, or 270 degrees can be selected as shown in Table 1. CLK I NCO clock. (CMOS level) SCLK I This pin clocks the frequency control shift register. SEL_L/M I A high on this input selects the least significant 32 bits of the 64-bit frequency register as the input to the phase accumulator; a low selects the most significant 32 bits. SFTEN I The active low input enables the shifting of the frequency register. MSB/LSB I This input selects the shift direction of the frequency register. A low on this input shifts in the data LSB first; a high shifts in the data MSB first. ENPHAC I This pin, when low, enables the clocking of the Phase Accumulator. This input has a pipeline delay of four clocks. SD I Data on this pin is shifted into the frequency register by the rising edge of SCLK when SFTEN is low. TXFR I This active low input is clocked onto the chip by CLK and becomes active after a pipeline delay of four clocks. When low, the frequency control word selected by SEL_L/M is transferred from the frequency register to the phase accumulator’s input register. LOAD I This input becomes active after a pipeline delay of five clocks. When low, the feedback in the phase accumulator is zeroed. OUT0-11 O Output data. OUT0 is LSB. Unsigned. All inputs are TTL level, with the exception of CLK. Overline designates active low signals. 2 HSP45102 PHASE OFFSET ADDER A D D E R R.P0-1 LOAD CLK / R.ENPHAC SINE ROM 12 / CLK 2-DLY R E G OUT0-11 R.TXFR R.LOAD CLK R E G / ‘0’ FREQUENCY CONTROL SECTION / 32 FRCTRL 0-31 32 FRCTRL 32-63 / 32 R.TXFR CLK SD SCLK A D D E R 1 32 ACCUMULATOR INPUT REGISTER MUX / / 32 R.LOAD 0 64-BIT SHIFT REG / 32 1 TXFR 4-DLY R E G 13 MSBs R E G 13 MUX ENPHAC R.P0-1 / 0 P0-1 R E G 13 / CLK R E G / 32 / 32 R.ENPHAC CLK SFTEN MSB/LSB R E G / 32 (HIGH SELECTS FRCTRL0-31, LOW SELECTS FRCTRL32-63) SEL_L/M PHASE ACCUMULATOR FIGURE 1. NCO-12 FUNCTIONAL BLOCK DIAGRAM Functional Description The NCO12 produces a 12-bit sinusoid whose frequency and phase are digitally controlled. The frequency of the sine wave is determined by one of two 32-bit words. Selection of the active word is made by SEL_L/M. The phase of the output is controlled by the two-bit input P0-1, which is used to select a phase offset of 0, 90, 180, or 270 degrees. As shown in the Block Diagram, the NCO12 consists of a Frequency Control Section, a Phase Accumulator, a Phase Offset Adder and a Sine ROM. The Frequency Control section serially loads the frequency control word into the frequency register. The Phase Accumulator and Phase Offset Adder compute the phase angle using the frequency control word and the two phase modulation inputs. The Sine ROM generates the sine of the computed phase angle. The format of the 12-bit output is offset binary. Frequency Control Section The Frequency Control Section shown in Figure 1 serially loads the frequency data into a 64-bit, bidirectional shift register. The shift direction is selected with the MSB/LSB input. When this input is high, the frequency control word on the SD input is shifted into the register MSB first. When MSB/LSB is low the data is shifted in LSB first. The register shifts on the rising edge of SCLK when SFTEN is low. The timing of these signals is shown in Figures 2A and 2B. the phase modulation bits P0-1. The architecture is shown in Figure 1. The most significant 13 bits of the 32-bit phase accumulator are summed with the two-bit phase offset to generate the 13-bit phase input to the Sine Rom. A value of 0 corresponds to 0o, a value of 1000 hexadecimal corresponds to a value of 180o. The phase accumulator advances the phase by the amount programmed into the frequency control register. The output frequency is equal to: F LO = ( N × F CLK ⁄ 2 32 ), or F OUT 32 , N = INT --------------- 2 F CLK (EQ. 1) (EQ. 2) where N is the 32 bits of frequency control word that is programmed. INT[•] is the integer of the computation. For example, if the control word is 20000000 hexadecimal and the clock frequency is 30MHz, then the output frequency would be FCLK/8, or 3.75MHz. Phase Accumulator Section The frequency control multiplexer selects the least significant 32 bits from the 64-bit frequency control register when SEL_L/M is high, and the most significant 32 bits when SEL_L/M is low. When only one frequency word is desired, SEL_L/M and MSB/LSB must be either both high or both low. This is due to the fact that when a frequency control word is loaded into the shift register LSB first, it enters through the most significant bit of the register. After 32 bits have been shifted in, they will reside in the 32 most significant bits of the 64-bit register. The phase accumulator and phase offset adder compute the phase of the sine wave from the frequency control word and When TXFR is asserted, the 32 bits selected by the frequency control multiplexer are clocked into the phase accumulator input The 64 bits of the frequency register are sent to the Phase Accumulator Section where 32 bits are selected to control the frequency of the sinusoidal output. 3 HSP45102 register. At each clock, the contents of this register are summed with the current contents of the accumulator to step to the new phase. The phase accumulator stepping may be inhibited by holding ENPHAC high. The phase accumulator may be loaded with the value in the input register by asserting LOAD, which zeroes the feedback to the phase accumulator. TABLE 1. PHASE MAPPING P0-1 CODING The phase adder sums the encoded phase modulation bits P0-1 and the output of the phase accumulator to offset the phase by 0, 90, 180 or 270 degrees. The two bits are encoded to produce the phase mapping shown in Table 1. This phase mapping is provided for direct connection to the in-phase and quadrature data bits for QPSK modulation. P1 P0 PHASE SHIFT (DEGREES) 0 0 0 0 1 90 1 0 270 1 1 180 ROM Section The ROM section generates the 12-bit sine value from the 13-bit output of the phase adder. The output format is offset binary and ranges from 001 to FFF hexadecimal, centered around 800 hexadecimal. SCLK SD 2 1 0 61 63 62 SFTEN MSB/LSB FIGURE 2A. FREQUENCY LOADING ENABLED BY SFTEN SCLK SD 2 1 0 61 62 63 SFTEN MSB/LSB FIGURE 2B. FREQUENCY LOADING CONTROLLED BY SCLK CLK 1 2 3 4 5 6 7 8 9 10 11 LOAD TXFR ENPHAC SEL_L/M OUT0-11 NEW DATA FIGURE 3. I/O TIMING 4 HSP45102 Absolute Maximum Ratings TA = 25°C Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V Input, Output or I/O Voltage Applied . . . . . GND -0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance (Typical, Note 1) θJA (°C/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . . 300°C (SOIC - Lead Tips Only) Operating Conditions Operating Voltage Range (Commercial, Industrial) . . +4.75V to +5.25V Operating Temperature Range (Commercial) . . . . . . . . 0°C to 70°C Operating Temperature Range (Industrial) . . . . . . . . .-40°C to 85°C Die Characteristics Backside Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS Logical One Input Voltage VIH VCC = 5.25V 2.0 - V Logical Zero Input Voltage VIL VCC = 4.75V - 0.8 V High Level Clock Input VIHC VCC = 5.25V 3.0 - V Low Level Clock Input VILC VCC = 4.75V - 0.8 V Output HIGH Voltage VOH IOH = -400µA, VCC = 4.75V 2.6 - V Output LOW Voltage VOL IOL = +2.0mA, VCC = 4.75V - 0.4 V -10 10 µA Input Leakage Current II VIN = VCC or GND, VCC = 5.25V Standby Power Supply Current ICCSB VIN = VCC or GND, VCC = 5.25V, Note 4 - 500 µA Operating Power Supply Current ICCOP f = 33MHz, VIN = VCC or GND VCC = 5.25V, Notes 2 and 4 - 99 mA MIN MAX UNITS - 10 pF - 10 pF Capacitance TA = 25°C, Note 3 PARAMETER SYMBOL Input Capacitance CIN Output Capacitance CO TEST CONDITIONS FREQ = 1MHz, VCC = Open. All measurements are referenced to device ground NOTES: 2. Power supply current is proportional to operating frequency. Typical rating for ICCOP is 3mA/MHz. 3. Not tested, but characterized at initial design and at major process/design changes. 4. Output load per test load circuit with switch open and CL = 40pF. 5 HSP45102 AC Electrical Specifications VCC = 5.0V ±5%, TA = 0°C to 70°C, TA = -40°C to 85°C (Note 5) -33 (33MHz) PARAMETER SYMBOL NOTES -40 (40MHz) MIN MAX MIN MAX UNITS Clock Period tCP 30 - 25 - ns Clock High tCH 12 - 10 - ns Clock Low tCL 12 - 10 - ns SCLK High/Low tSW 12 - 10 - ns Setup Time SD to SCLK Going High tDS 12 - 12 - ns Hold Time SD from SCLK Going High tDH 0 - 0 - ns Setup Time SFTEN, MSB/LSB to SCLK Going High tMS 15 - 12 - ns Hold Time SFTEN, MSB/LSB from SCLK Going High tMH 0 - 0 - ns Setup Time SCLK High to CLK Going High tSS 16 - 15 - ns Setup Time P0-1 to CLK Going High tPS 15 - 12 - ns Hold Time P0-1 from CLK Going High tPH 1 - 1 - ns Setup Time LOAD, TXFR, ENPHAC, SEL_L/M to CLK Going High tES 15 - 13 - ns Hold Time LOAD, TXFR, ENPHAC, SEL_L/M from CLK Going High tEH 1 - 1 - ns CLK to Output Delay tOH 2 15 2 13 ns Output Rise, Fall Time tRF 8 - 8 - ns Note 6 Note 7 NOTES: 5. AC testing is performed as follows: Input levels (CLK Input) 4.0V and 0V; Input levels (all other inputs) 0V and 3.0V; Timing reference levels (CLK) 2.0V; All others 1.5V. Output load per test load circuit with switch closed and CL = 40pF. Output transition is measured at VOH > 1.5V and VOL < 1.5V. 6. If TXFR is active, care must be taken to not violate setup and hold times as data from the shift registers may not have settled before CLK occurs. 7. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design changes. AC Test Load Circuit DUT S1 CL (NOTE) ± SWITCH S1 OPEN FOR ICCSB AND ICCOP IOH 1.5V EQUIVALENT CIRCUIT NOTE: Test head capacitance. 6 IOL HSP45102 Waveforms tCP tCH tCL CLK P0-1 LOAD, TXFR, tPS tPH tES tEH ENPHAC, SEL_L/M tRF tOH OUT0-11 tSW tSS tDS tDH tSW SCLK SD tMS tMH MSB/LSB, SFTEN FIGURE 4. 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