INTERSIL HA2-5002-5

HA-5002
®
Data Sheet
March 8, 2006
FN2921.11
110MHz, High Slew Rate, High Output
Current Buffer
Features
The HA-5002 is a monolithic, wideband, high slew rate, high
output current, buffer amplifier.
• High Input Impedance . . . . . . . . . . . . . . . . . . . . . .3000kΩ
Utilizing the advantages of the Intersil D.I. technologies, the
HA-5002 current buffer offers 1300V/µs slew rate with
110MHz of bandwidth. The ±200mA output current capability
is enhanced by a 3Ω output impedance.
• Very Wide Bandwidth . . . . . . . . . . . . . . . . . . . . . . 110MHz
• Voltage Gain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.995
The monolithic HA-5002 will replace the hybrid LH0002 with
corresponding performance increases. These characteristics
range from the 3000kΩ input impedance to the increased
output voltage swing. Monolithic design technologies have
allowed a more precise buffer to be developed with more than
an order of magnitude smaller gain error.
• Low Output Impedance . . . . . . . . . . . . . . . . . . . . . . . . 3Ω
• Very High Slew Rate . . . . . . . . . . . . . . . . . . . . . 1300V/µs
• High Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . ±200mA
• Pulsed Output Current . . . . . . . . . . . . . . . . . . . . . . 400mA
• Monolithic Construction
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Line Driver
The HA-5002 will provide many present hybrid users with a
higher degree of reliability and at the same time increase
overall circuit performance.
• Data Acquistion
For the military grade product, refer to the HA-5002/883
datasheet.
• High Power Current Booster
• 110MHz Buffer
• Radara Cable Driver
• High Power Current Source
• Sample and Holds
• Video Products
Ordering Information
PART NUMBER
PART MARKING
TEMP.
RANGE (°C)
PACKAGE
PKG.
DWG. #
HA2-5002-2
HA2-5002-2
-55 to 125
8 Pin Metal Can
T8.C
HA2-5002-5
HA2-5002-5
0 to 75
8 Pin Metal Can
T8.C
HA3-5002-5
HA3-5002-5
0 to 75
8 Ld PDIP
E8.3
HA3-5002-5Z (Note)
HA3-5002-5Z
0 to 75
8 Ld PDIP* (Pb-free)
E8.3
HA4P5002-5
HA4P5002-5
0 to 75
20 Ld PLCC
N20.35
HA4P5002-5Z (Note)
HA4P5002-5Z
0 to 75
20 Ld PLCC (Pb-free)
N20.35
HA9P5002-5
50025
0 to 75
8 Ld SOIC
M8.15
HA9P5002-5Z (Note)
50025Z
0 to 75
8 Ld SOIC (Pb-free)
M8.15
HA9P5002-9
50029
-40 to 85
8 Ld SOIC
M8.15
HA9P5002-9Z (Note)
50029Z
-40 to 85
8 Ld SOIC (Pb-free)
M8.15
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003-2006. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
HA-5002
Pinouts
V2-
2
7
V2+
NC
3
6
NC
4
5
V1-
NC
3
2
1
20
19
IN
8
V1+
NC 4
18 NC
V2- 5
17 V2+
NC 6
16 NC
NC 7
15 NC
NC 8
14 NC
V2+
1
7
2
NC
V1-
6
5
3
V2-
NC
4
OUT
2
10
11
12
13
NC
V1-
NC
NOTE: Case Voltage = Floating
9
IN
IN
OUT
OUT
NC
8
V1+
1
HA-5002 (METAL CAN)
TOP VIEW
NC
V1+
HA-5002 (PLCC)
TOP VIEW
NC
HA-5002 (PDIP, SOIC)
TOP VIEW
FN2921.11
March 8, 2006
HA-5002
Absolute Maximum Ratings
Thermal Information
Voltage Between V+ and V- Terminals. . . . . . . . . . . . . . . . . . . . 44V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V1+ to V1Output Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . ±200mA
Output Current (50ms On, 1s Off) . . . . . . . . . . . . . . . . . . . . ±400mA
Thermal Resistance (Typical, Note 2)
θJA (°C/W)
θJC (°C/W)
PDIP Package*. . . . . . . . . . . . . . . . . . .
92
N/A
Metal Can Package . . . . . . . . . . . . . . .
155
67
PLCC Package. . . . . . . . . . . . . . . . . . .
74
N/A
SOIC Package . . . . . . . . . . . . . . . . . . .
157
N/A
Max Junction Temperature (Hermetic Packages, Note 1) . . . . . . 175°C
Max Junction Temperature (Plastic Packages, Note 1) . . . . . . . . 150°C
Max Storage Temperature Range . . . . . . . . . . . . . . -65°C to 150°C
Max Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . 300°C
(PLCC and SOIC - Lead Tips Only)
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
Operating Conditions
Temperature Range
HA-5002-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to 125°C
HA-5002-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C
HA-5002-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Maximum power dissipation, including load conditions, must be designed to maintain the maximum junction temperature below 175°C for the
can packages, and below 150°C for the plastic packages.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
VSUPPLY = ±12V to ±15V, RS = 50Ω, RL = 1kΩ, CL = 10pF, Unless Otherwise Specified
Electrical Specifications
TEST
CONDITIONS
PARAMETER
HA-5002-2
HA-5002-5, -9
TEMP
(°C)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
25
-
5
20
-
5
20
mV
INPUT CHARACTERISTICS
Offset Voltage
Full
-
10
30
-
10
30
mV
Average Offset Voltage Drift
Full
-
30
-
-
30
-
µV/°C
Bias Current
25
-
2
7
-
2
7
µA
Full
-
3.4
10
-
2.4
10
µA
Full
1.5
3
-
1.5
3
-
MΩ
10Hz-1MHz
25
-
18
-
-
18
-
µVP-P
RL = 50Ω
25
-
0.900
-
-
0.900
-
V/V
RL = 100Ω
25
-
0.971
-
-
0.971
-
V/V
Input Resistance
Input Noise Voltage
TRANSFER CHARACTERISTICS
Voltage Gain
(VOUT = ±10V)
-3dB Bandwidth
RL = 1kΩ
25
-
0.995
-
-
0.995
-
V/V
RL = 1kΩ
Full
0.980
-
-
0.980
-
-
V/V
VIN = 1VP-P
25
-
110
-
-
110
-
MHz
25
-
40
-
-
40
-
A/mA
AC Current Gain
OUTPUT CHARACTERISTICS
Output Voltage Swing
RL = 100Ω
25
±10
±10.7
-
±10
±11.2
-
V
RL = 1kΩ, VS = ±15V
Full
±10
±13.5
-
±10
±13.9
-
V
RL = 1kΩ, VS = ±12V
Full
±10
±10.5
-
±10
±10.5
-
V
mA
VIN = ±10V, RL = 40Ω
Output Current
Output Resistance
VIN = 1VRMS, f = 10kHz
Harmonic Distortion
25
-
220
-
-
220
-
Full
-
3
10
-
3
10
Ω
25
-
<0.005
-
-
<0.005
-
%
TRANSIENT RESPONSE
Full Power Bandwidth (Note 3)
25
-
20.7
-
-
20.7
-
MHz
Rise Time
25
-
3.6
-
-
3.6
-
ns
ns
Propagation Delay
25
-
2
-
-
2
-
Overshoot
25
-
30
-
-
30
-
%
Slew Rate
25
1.0
1.3
-
1.0
1.3
-
V/ns
25
-
50
-
-
50
-
ns
Settling Time
To 0.1%
3
FN2921.11
March 8, 2006
HA-5002
VSUPPLY = ±12V to ±15V, RS = 50Ω, RL = 1kΩ, CL = 10pF, Unless Otherwise Specified (Continued)
Electrical Specifications
TEST
CONDITIONS
PARAMETER
HA-5002-2
HA-5002-5, -9
TEMP
(°C)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Differential Gain
RL = 500Ω
25
-
0.06
-
-
0.06
-
%
Differential Phase
RL = 500Ω
25
-
0.22
-
-
0.22
-
Degrees
POWER REQUIREMENTS
Supply Current
AV = 10V
Power Supply Rejection Ratio
25
-
8.3
-
-
8.3
-
mA
Full
-
-
10
-
-
10
mA
Full
54
64
-
54
64
-
dB
NOTE:
Slew Rate3. FPBW = -------------------------; V = 10V .
2πV P EAK P
Test Circuit and Waveforms
+15V
V2+
V1+
RS
IN
OUT
V2-
V1-15V
RL
FIGURE 1. LARGE AND SMALL SIGNAL RESPONSE
VIN
VIN
VOUT
VOUT
RS = 50Ω, RL = 100Ω
RS = 50Ω, RL = 1kΩ
SMALL SIGNAL WAVEFORMS
SMALL SIGNAL WAVEFORMS
4
FN2921.11
March 8, 2006
HA-5002
Test Circuit and Waveforms (Continued)
VIN
VIN
VOUT
VOUT
RS = 50Ω, RL = 100Ω
RS = 50Ω, RL = 1kΩ
LARGE SIGNAL WAVEFORMS
LARGE SIGNAL WAVEFORMS
Schematic Diagram
V1+
R8
R9
RN1
Q19
R4
Q26 Q20
Q25
R10
V2+
R1
Q18
Q12
Q3
Q9
Q1
Q27
Q6
Q10
R5
Q7
IN
R11
Q4
OUT
RN2
Q21
Q5
Q11
Q2
Q22
Q8
Q15
Q23
Q24
Q17
Q16
Q13
Q14
R7
R12
V2-
R6
R2
R3
RN3
V1-
Application Information
Layout Considerations
The wide bandwidth of the HA-5002 necessitates that high
frequency circuit layout procedures be followed. Failure to
follow these guidelines can result in marginal performance.
Probably the most crucial of the RF/video layout rules is the
use of a ground plane. A ground plane provides isolation and
minimizes distributed circuit capacitance and inductance
which will degrade high frequency performance.
5
Other considerations are proper power supply bypassing
and keeping the input and output connections as short as
possible which minimizes distributed capacitance and
reduces board space.
Power Supply Decoupling
For optimal device performance, it is recommended that the
positive and negative power supplies be bypassed with
capacitors to ground. Ceramic capacitors ranging in value
from 0.01 to 0.1µF will minimize high frequency variations in
supply voltage, while low frequency bypassing requires
FN2921.11
March 8, 2006
HA-5002
Capacitive Loading
larger valued capacitors since the impedance of the
capacitor is dependent on frequency.
The HA-5002 will drive large capacitive loads without oscillation
but peak current limits should not be exceeded. Following the
formula I = Cdv/dt implies that the slew rate or the capacitive
load must be controlled to keep peak current below the
maximum or use the current limiting approach as shown. The
HA-5002 can become unstable with small capacitive loads
(50pF) if certain precautions are not taken. Stability is
enhanced by any one of the following: a source resistance in
series with the input of 50Ω to 1kΩ; increasing capacitive load
to 150pF or greater; decreasing CLOAD to 20pF or less; adding
an output resistor of 10Ω to 50Ω; or adding feedback
capacitance of 50pF or greater. Adding source resistance
generally yields the best results.
It is also recommended that the bypass capacitors be
connected close to the HA-5002 (preferably directly to the
supply pins).
Operation at Reduced Supply Levels
The HA-5002 can operate at supply voltage levels as low as
±5V and lower. Output swing is directly affected as well as
slight reductions in slew rate and bandwidth.
Short Circuit Protection
The output current can be limited by using the following circuit:
VV+
R LIM = ------------------------- = -------------------------I OUTMAX
I OUTMAX
IOUTMAX = 200mA
(CONTINUOUS)
V+
V1+
RLIM
V2+
OUT
IN
V2-
V1-
RLIM
V1.8
MAXIMUM POWER DISSIPATION (W)
1.6
1.4
T JMAX – T A
P DMAX = ------------------------------------------θ JC + θ CS + θ SA
PLCC
PDIP
1.2
Where: TJMAX = Maximum Junction Temperature of the
Device
CAN
1.0
TA = Ambient
0.8
θJC = Junction to Case Thermal Resistance
SOIC
0.6
θCS = Case to Heat Sink Thermal Resistance
θSA = Heat Sink to Ambient Thermal Resistance
0.4
QUIESCENT POWER DISSIPATION
AT ±15V SUPPLIES
0.2
Graph is based on:
T JMAX – T A
P DMAX = ------------------------------θ JA
0.0
25
65
45
85
105
125
TEMPERATURE (°C)
FIGURE 2. MAXIMUM POWER DISSIPATION vs TEMPERATURE
6
FN2921.11
March 8, 2006
HA-5002
Typical Application
+12V
V1+
V2+
RS
RM
50Ω
50Ω
VIN
RG -58
VOUT
VIN
V1-
RL 50Ω
V2-12V
VOUT
FIGURE 3. COAXIAL CABLE DRIVER - 50Ω SYSTEM
Typical Performance Curves
9
VS = ±15V, RS = 50Ω
GAIN
0
-3
PHASE
-6
0°
-9
45°
-12
90°
-15
135°
-18
VOLTAGE GAIN (dB)
3
10
3
GAIN
0
-3
PHASE
-6
0°
-9
45°
-12
90°
-15
135°
180°
-18
180°
1
VS = ±15V, RS = 50Ω
6
PHASE SHIFT
VOLTAGE GAIN (dB)
6
1
100
10
FREQUENCY (MHz)
100
FREQUENCY (MHz)
FIGURE 4. GAIN/PHASE vs FREQUENCY (RL = 1kΩ)
FIGURE 5. GAIN/PHASE vs FREQUENCY (RL = 50Ω)
0.994
0.998
0.992
PHASE SHIFT
9
VS = ±15V
VS = ±15V
0.997
VOLTAGE GAIN (V/V)
VOLTAGE GAIN (V/V)
0.990
0.988
VOUT = -10V TO +10V
0.986
0.984
0.982
0.980
0.978
VOUT = 0 TO +10V
0.996
0.995
0.994
VOUT = 0 TO -10V
0.993
0.992
0.976
0.974
-60
-40
-20
0
20
40
60
TEMPERATURE (°C)
80
100
120
FIGURE 6. VOLTAGE GAIN vs TEMPERATURE (RL = 100Ω)
7
0.991
-60
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 7. VOLTAGE GAIN vs TEMPERATURE (RL = 1kΩ)
FN2921.11
March 8, 2006
HA-5002
3
2
1
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
-11
-60
(Continued)
7
VS = ±15V
VS = ±15V
6
BIAS CURRENT (µA)
OFFSET VOLTAGE (mV)
Typical Performance Curves
5
4
3
2
1
0
-40
-20
0
20
40
60
80
100
-60
120
-40
-20
20
40
60
80
100
120
FIGURE 9. BIAS CURRENT vs TEMPERATURE
FIGURE 8. OFFSET VOLTAGE vs TEMPERATURE
15
0
TEMPERATURE (°C)
TEMPERATURE (°C)
10
VS = ±15V, RLOAD = 100Ω
VS = ±15V, IOUT = 0mA
14
SUPPLY CURRENT (mA)
OUTPUT VOLTAGE (V)
9
+VOUT
-VOUT
13
12
8
7
6
5
4
11
-60
-40
-20
0
20
40
60
TEMPERATURE (°C)
80
100
3
-60
120
FIGURE 10. MAXIMUM OUTPUT VOLTAGE vs TEMPERATURE
-20
0
20
40
60
TEMPERATURE (°C)
80
100
120
FIGURE 11. SUPPLY CURRENT vs TEMPERATURE
10
VS = ±15V
IOUT = 0mA
125°C, 25°C
100K
8
IMPEDANCE (Ω)
SUPPLY CURRENT (mA)
-40
-55°C
6
4
ZIN
10K
1000
100
2
10
0
0
2
4
6
8
10
12
14
16
SUPPLY VOLTAGE (±V)
FIGURE 12. SUPPLY CURRENT vs SUPPLY VOLTAGE
8
18
1
100K
ZOUT
1M
10M
100M
FREQUENCY (Hz)
FIGURE 13. INPUT/OUTPUT IMPEDANCE vs FREQUENCY
FN2921.11
March 8, 2006
HA-5002
(Continued)
80
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
15
RLOAD = 100Ω
70
60
PSRR (dB)
VOUT MAX, VP-P AT 100kHz
Typical Performance Curves
TA = 25°C
TA = 125°C,
TA = -55°C
50
40
30
20
10
12
8
SUPPLY VOLTAGE (±V)
0
10K
5
1M
FREQUENCY (Hz)
100M
10M
FIGURE 15. PSRR vs FREQUENCY
FIGURE 14. VOUT MAXIMUM vs VSUPPLY
1500
150
1400
100
VOUT - VIN (mV)
SLEW RATE (V/µs)
100K
1300
1200
1100
VS = ±15V
TA = 25°C
RL = 100
50
RL = 1K
0
-50
RL = 600
1000
-100
900
6
8
10
12
14
SUPPLY VOLTAGE (±V)
16
FIGURE 16. SLEW RATE vs SUPPLY VOLTAGE
18
-150
-10
-8
-6
-4
-2
0
2
4
INPUT VOLTAGE (VOLTS)
6
8
10
FIGURE 17. GAIN ERROR vs INPUT VOLTAGE
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
V1TRANSISTOR COUNT:
27
PROCESS:
Bipolar Dielectric Isolation
9
FN2921.11
March 8, 2006
HA-5002
Metallization Mask Layout
HA-5002
IN
V1-
V1- (ALT)
V1+ (ALT)
V2+
V2-
V1+
OUT
10
FN2921.11
March 8, 2006
HA-5002
Dual-In-Line Plastic Packages (PDIP)
E8.3 (JEDEC MS-001-BA ISSUE D)
N
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
-B-
-AD
E
BASE
PLANE
-C-
A2
SEATING
PLANE
A
L
D1
e
B1
D1
A1
eC
B
0.010 (0.25) M
C A B S
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.045
0.070
1.15
1.77
8, 10
eA
C
0.008
0.014
0.204
C
D
0.355
0.400
9.01
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
0.005
-
0.13
-
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
e
0.100 BSC
eA
0.300 BSC
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
eB
-
L
0.115
5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
5
D1
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.
0.355
10.16
N
8
2.54 BSC
7.62 BSC
0.430
-
0.150
2.93
10.92
3.81
8
6
7
4
9
Rev. 0 12/93
7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
11
FN2921.11
March 8, 2006
HA-5002
Metal Can Packages (Can)
T8.C MIL-STD-1835 MACY1-X8 (A1)
REFERENCE PLANE
A
8 LEAD METAL CAN PACKAGE
e1
L
L2
L1
INCHES
SYMBOL
ØD2
0.185
4.19
4.70
-
0.019
0.41
0.48
1
Øb1
0.016
0.021
0.41
0.53
1
N
Øb2
0.016
0.024
0.41
0.61
-
ØD
0.335
0.375
8.51
9.40
-
α
ØD1
0.305
0.335
7.75
8.51
-
ØD2
0.110
0.160
2.79
4.06
-
1
β
Øb
k
C
L
e
BASE AND
SEATING PLANE
Q
BASE METAL
Øb1
NOTES
0.165
k1
Øb1
MAX
0.016
Øe
F
MIN
A
A
2
MILLIMETERS
MAX
Øb
A
ØD ØD1
MIN
e1
LEAD FINISH
Øb2
SECTION A-A
NOTES:
1. (All leads) Øb applies between L1 and L2. Øb1 applies between
L2 and 0.500 from the reference plane. Diameter is uncontrolled
in L1 and beyond 0.500 from the reference plane.
2. Measured from maximum diameter of the product.
3. α is the basic spacing from the centerline of the tab to terminal 1
and β is the basic spacing of each lead or lead position (N -1
places) from α, looking at the bottom of the package.
0.200 BSC
5.08 BSC
0.100 BSC
-
2.54 BSC
-
F
-
0.040
-
1.02
-
k
0.027
0.034
0.69
0.86
-
k1
0.027
0.045
0.69
1.14
2
12.70
19.05
1
1.27
1
L
0.500
0.750
L1
-
0.050
-
L2
0.250
-
6.35
-
1
Q
0.010
0.045
0.25
1.14
-
α
β
45o BSC
45o BSC
45o BSC
45o BSC
N
8
8
3
3
4
Rev. 0 5/18/94
4. N is the maximum number of terminal positions.
5. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
6. Controlling dimension: INCH.
12
FN2921.11
March 8, 2006
HA-5002
Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07)
0.048 (1.22)
PIN (1) IDENTIFIER
N20.35 (JEDEC MS-018AA ISSUE A)
0.042 (1.07)
0.056 (1.42)
0.004 (0.10)
C
0.025 (0.64)
R
0.045 (1.14)
0.050 (1.27) TP
C
L
D2/E2
C
L
E1 E
D2/E2
VIEW “A”
0.020 (0.51)
MIN
A1
A
D1
D
20 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.165
0.180
4.20
4.57
-
A1
0.090
0.120
2.29
3.04
-
D
0.385
0.395
9.78
10.03
-
D1
0.350
0.356
8.89
9.04
3
D2
0.141
0.169
3.59
4.29
4, 5
E
0.385
0.395
9.78
10.03
-
E1
0.350
0.356
8.89
9.04
3
E2
0.141
0.169
3.59
4.29
4, 5
N
20
20
6
Rev. 2 11/97
SEATING
-C- PLANE
0.020 (0.51) MAX
3 PLCS
0.026 (0.66)
0.032 (0.81)
0.013 (0.33)
0.021 (0.53)
0.025 (0.64)
MIN
0.045 (1.14)
MIN
VIEW “A” TYP.
NOTES:
1. Controlling dimension: INCH. Converted millimeter dimensions are
not necessarily exact.
2. Dimensions and tolerancing per ANSI Y14.5M-1982.
3. Dimensions D1 and E1 do not include mold protrusions. Allowable
mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1
and E1 include mold mismatch and are measured at the extreme
material condition at the body parting line.
4. To be measured at seating plane -C- contact point.
5. Centerline to be determined where center leads exit plastic body.
6. “N” is the number of terminal positions.
13
FN2921.11
March 8, 2006
HA-5002
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
INDEX
AREA
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
H
0.25(0.010) M
B M
INCHES
E
SYMBOL
-B1
2
A
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
B S
MIN
MAX
MIN
MAX
NOTES
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
e
α
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
N
α
NOTES:
MILLIMETERS
8
0°
1.27
8
8°
0°
6
7
8°
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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14
FN2921.11
March 8, 2006