ICL7665S Data Sheet CMOS Micropower Over/Under Voltage Detector The ICL7665S Super CMOS Micropower Over/Under Voltage Detector contains two low power, individually programmable Voltage detectors on a single CMOS chip. Requiring typically 3µA for operation, the device is intended for battery-operated systems and instruments which require high or low voltage warnings, settable trip points, or fault monitoring and correction. The trip points and hysteresis of the two voltage detectors are individually programmed via external resistors. An internal bandgap-type reference provides an accurate threshold voltage while operating from any supply in the 1.6V to 16V range. The ICL7665S, Super Programmable Over/Under Voltage Detector is a direct replacement for the industry standard ICL7665B offering wider operating voltage and temperature ranges, improved threshold accuracy (ICL7665SA), and temperature coefficient, and guaranteed maximum supply current. All improvements are highlighted in the electrical characteristics section. All critical parameters are guaranteed over the entire commercial and industrial temperature ranges. April 1999 File Number 3182.4 Features • Guaranteed 10µA Maximum Quiescent Current Over Temperature • Guaranteed Wider Operating Voltage Range Over Entire Operating Temperature Range • 2% Threshold Accuracy (ICL7665SA) • Dual Comparator with Precision Internal Reference • 100ppm/oC Temperature Coefficient of Threshold Voltage • 100% Tested at 2V • Output Current Sinking Ability . . . . . . . . . . . . Up to 20mA • Individually Programmable Upper and Lower Trip Voltages and Hysteresis Levels Applications • Pocket Pagers • Portable Instrumentation • Charging Systems • Memory Power Back-Up • Battery Operated Systems Ordering Information PART NUMBER TEMP. RANGE (oC) • Portable Computers • Level Detectors PACKAGE PKG. NO. ICL7665SCBA 0 to 70 8 Ld SOIC (N) M8.15 ICL7665SCPA 0 to 70 8 Ld PDIP E8.3 ICL7665SACBA 0 to 70 8 Ld SOIC (N) M8.15 ICL7665SACPA 0 to 70 8 Ld PDIP E8.3 ICL7665SIBA -40 to 85 8 Ld SOIC (N) M8.15 ICL7665SIPA -40 to 85 8 Ld PDIP E8.3 ICL7665SAIBA -40 to 85 8 Ld SOIC (N) M8.15 ICL7665SAIPA -40 to 85 3-62 8 Ld PDIP E8.3 Pinout ICL7665S (SOIC, PDIP) TOP VIEW OUT 1 1 8 V+ HYST 1 2 7 OUT 2 SET 1 3 6 SET 2 GND 4 5 HYST 2 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 ICL7665S Absolute Maximum Ratings Thermal Information Supply Voltage (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +18V Output Voltages OUT1 and OUT2 . . . . . . . . . . . . . . . . . -0.3V to 18V (with respect to GND) (Note 2) Output Voltages HYST1 and HYST2 . . . . . . . . . . . . . . -0.3V to +18V (with respect to V+) (Note 2) Input Voltages SET1 and SET2 . . . . . (GND -0.3V) to (V+ V- +0.3V) (Note 2) Maximum Sink Output OUT1 and OUT2 . . . . . . . . . . . . . . . . . 25mA Maximum Source Output Current HYST1 and HYST2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25mA Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 150 N/A Plastic SOIC Package . . . . . . . . . . . . . 180 N/A Maximum Junction Temperature (Plastic) . . . . . . . . . . . . . . . .150oC Maximum Junction Temperature (CERDIP). . . . . . . . . . . . . . .175oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range ICL7665SC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC ICL7665SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured with the component mounted on an evaluation PC board in free air. 2. Due to the SCR structure inherent in the CMOS process used to fabricate these devices, connecting any terminal to voltages greater than (V+ +0.3V) or less than (GND - 0.3V) may cause destructive device latchup. For these reasons, it is recommended that no inputs from external sources not operating from the same power supply be applied to the device before its supply is established, and that in multiple supply systems, the supply to the ICL7665S be turned on first. If this is not possible, current into inputs and/or outputs must be limited to ±0.5mA and voltages must not exceed those defined above. The specifications below are applicable to both the ICL7665S and ICL7665SA. V+ = 5V, TA = 25oC, Test Circuit Figure 7. Unless Otherwise Specified Electrical Specifications PARAMETER SYMBOL Operating Supply Voltage V+ TEST CONDITIONS MIN TYP MAX UNITS 1.6 - 16 V 1.8 - 16 V 1.8 - 16 V 1.8 - 16 V 1.8 - 16 V V+ = 2V - 2.5 10 µA V+ = 9V - 2.6 10 µA V+ = 15V - 2.9 10 µA V+ = 2V - 2.5 10 µA V+ = 9V - 2.6 10 µA V+ = 15V - 2.9 10 µA 1.20 1.30 1.40 V 1.20 1.30 1.40 V 1.275 1.30 1.325 V 1.275 1.30 1.325 V ICL7665S - 200 - ppm ICL7665SA - 100 - ppm ROUT1, ROUT2, RHYST1, R2HYST2 = 1MΩ, 2V ≤ V+ ≤ 10V - 0.03 - %/V ICL7665S ICL7665SA Supply Current I+ GND ≤ VSET1, VSET2 ≤ V+, All Outputs Open Circuit 0oC ≤ TA ≤ 70oC -40oC ≤ TA ≤ 85oC Input Trip Voltage VSET1 TA = 25oC 0oC ≤ TA ≤ 70oC -25oC ≤ TA ≤ 85oC 0oC ≤ TA ≤ 70oC -25oC ≤ TA ≤ 85oC ICL7665S VSET2 VSET1 ICL7665SA VSET2 Temperature Coefficient of VSET ∆VSET Supply Voltage Sensitivity of VSET1, VSET2 ∆VSET ∆T ∆VS 3-63 ICL7665S The specifications below are applicable to both the ICL7665S and ICL7665SA. V+ = 5V, TA = 25oC, Test Circuit Figure 7. Unless Otherwise Specified (Continued) Electrical Specifications PARAMETER SYMBOL Output Leakage Currents of OUT and HYST IOLK TEST CONDITIONS MIN TYP MAX UNITS - 10 200 nA - -10 -100 nA - - 2000 nA - - -500 nA V+ = 2V - 0.2 0.5 V V+ = 5V - 0.1 0.3 V V+ = 15V - 0.06 0.2 V V+ = 2V - -0.15 -0.30 V V+ = 5V - -0.05 -0.15 V V+ = 15V - -0.02 -0.10 V V+ = 2V - 0.2 0.5 V V+ = 5V - 0.15 0.3 V V+ = 15V - 0.11 0.25 V V+ = 2V, IHYST2 = -0.2mA - -0.25 -0.8 V V+ = 5V, IHYST2 = -0.5mA - -0.43 -1.0 V V+ = 15V, IHYST2 = -0.5mA - -0.35 -0.8 V - 0.01 10 nA ICL7665S - 1.0 - mV ICL7665SA - 0.1 - mV - ±5 ±50 mV ICL7665S - ±1 - mV ICL7665SA - ±0.1 - mV VSET = 0V or VSET ≥ 2V IHLK IOLK V+ = 15V, TA = 70oC IHLK Output Saturation Voltages VOUT1 Output Saturation Voltages VHYST1 Output Saturation Voltages VOUT2 Output Saturation Voltages VHYST2 VSET1 = 2V, IOUT1 = 2mA VSET1 = 2V, IHYST1 = -0.5mA VSET2 = 0V, IOUT2 = 2mA VSET2 = 2V VSET Input Leakage Current ISET GND ≤ VSET ≤ V+ ∆ Input for Complete Output Change ∆VSET ROUT = 4.7kΩ, RHYST = 20kΩ, VOUTLO = 1% V+, VOUTHI = 99% V+ Difference in Trip Voltages VSET1 VSET2 Output/Hysteresis Difference ROUT, RHYST = 1mW ROUT, RHYST = 1mW NOTES: 3. Derate above 25oC ambient temperature at 4mW/oC 4. All significant improvements over the industry standard ICL7665 are highlighted. AC Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS - 85 - µs - 90 - µs t SO2D - 55 - µs t SH2D - 55 - µs - 75 - µs - 80 - µs t SO2D - 60 - µs t SH2D - 60 - µs OUTPUT DELAY TIMES Input Going HI t SO1D t SH1D Input Going LO t SO1D t SH1D 3-64 VSET Switched between 1.0V to 1.6V ROUT = 4.7kΩ, CL = 12pF RHYST = 20kΩ, CL = 12pF VSET Switched between 1.6V to 1.0V ROUT = 4.7kΩ, CL = 12pF RHYST = 20kΩ, CL = 12pF ICL7665S AC Electrical Specifications PARAMETER Output Rise Times (Continued) SYMBOL MIN TYP MAX UNITS - 0.6 - µs - 0.8 - µs t H1R - 7.5 - µs t H2R - 0.7 - µs - 0.6 - µs - 0.7 - µs t H1F - 4.0 - µs t H2F - 1.8 - µs t O1R t O2R Output Fall Times t O1F t O2F TEST CONDITIONS VSET Switched between 1.0V to 1.6V ROUT = 4.7kΩ, CL = 12pF RHYST = 20kΩ, CL = 12pF VSET Switched between 1.0V to 1.6V ROUT = 4.7kΩ, CL = 12pF RHYST = 20kΩ, CL = 12pF Functional Block Diagram V+ SET1 + HYST2 HYST1 REF + - SET2 OUT2 OUT1 GND CONDITIONS (Note 5) VSET1 > 1.3V, OUT1 Switch ON, HYST1 Switch ON VSET1 < 1.3V, OUT1 Switch OFF, HYST1 Switch OFF VSET2 > 1.3V, OUT2 Switch OFF, HYST2 Switch ON VSET2 < 1.3V, OUT2 Switch ON, HYST2 Switch OFF NOTE: 5. See Electrical Specifications for exact thresholds. 3-65 ICL7665S Typical Performance Curves 2.0 2.0 V+ = 2V VOLTAGE SATURATION (V) VOLTAGE SATURATION (V) V+ = 2V 1.5 V+ = 5V 1.0 V+ = 9V 0.5 V+ = 15V 1.5 1.0 V+ = 5V V+ = 9V 0.5 V+ = 15V 0 0 5 10 15 0 20 5 IOUTOUT1 (mA) FIGURE 1. OUT1 SATURATION VOLTAGE AS A FUNCTION OF OUTPUT CURRENT -16 -12 -8 -4 0 -5.0 0 TA = 25oC -0.4 V+ = 15V -0.8 -1.2 V+ = 9V -1.6 V+ = 2V V+ = 5V -2.0 -4.0 -1.0 0 0 V+ = 15V -2.0 V+ = 9V -3.0 -4.0 V+ = 2V V+ = 5V -5.0 FIGURE 4. HYST2 OUTPUT SATURATION VOLTAGE vs HYST2 OUTPUT CURRENT 5.0 0V ≤ VSET1, VSET2 ≤ V+ 4.5 4.0 V+ = 15V 0V ≤ VSET1, VSET2 ≤ V+ 4.5 SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) -2.0 -1.0 5.0 V+ = 9V 3.0 2.5 V+ = 2V 1.5 TA = -20oC 4.0 3.5 TA = 25oC 3.0 2.5 2.0 TA = 70oC 1.5 1.0 1.0 0.5 0.5 0 -25 -3.0 HYST2 OUTPUT CURRENT (mA) FIGURE 3. HYST1 OUTPUT SATURATION VOLTAGE vs HYST1 OUTPUT CURRENT 2.0 20 TA = 25oC HYST1 OUTPUT CURRENT (mA) 3.5 15 FIGURE 2. OUT2 SATURATION VOLTAGE AS A FUNCTION OF OUTPUT CURRENT HYST1 OUTPUT SATURATION VOLTAGE (V) -20 10 IOUTOUT2 (mA) HYST2 OUTPUT SATURATION VOLTAGE (V) 0 0 0 +20 +40 +60 AMBIENT TEMPERATURE (oC) FIGURE 5. SUPPLY CURRENT AS A FUNCTION OF AMBIENT TEMPERATURE 3-66 0 2 4 6 8 10 12 14 16 SUPPLY VOLTAGE (V+) FIGURE 6. SUPPLY CURRENT AS A FUNCTION OF SUPPLY VOLTAGE ICL7665S Detailed Description As shown in the Functional Diagram, the ICL7665S consists of two comparators which compare input voltages on the SET1 and SET2 terminals to an internal 1.3V bandgap reference. The outputs from the two comparators drive opendrain N-channel transistors for OUT1 and OUT2, and opendrain P-channel transistors for HYST1 and HYST2 outputs. Each section, the Under Voltage Detector and the Over Voltage Detector, is independent of the other, although both use the internal 1.3V reference. The offset voltages of the two comparators will normally be unequal so VSET1 will generally not quite equal VSET2. The input impedance of the SET1 and SET2 pins are extremely high, and for most practical applications can be ignored. The four outputs are open-drain MOS transistors, and when ON behave as low resistance switches to their respective supply rails. This minimizes errors in setting up the hysteresis, and maximizes the output flexibility. The operating currents of the bandgap reference and the comparators are around 100nA each. V+ INPUT OUT1 1.6V 1.0V t O1R t SO1D t O1F V+ (5V) GND t SO1D t H1F HYST1 V+ (5V) GND t SH1D t SO2D t O2R t SO2D t O2F t SH2D t H2R t SH2D t H2F V+ (5V) GND V+ (5V) GND HYST2 4.7 kΩ V+ 8 VSET1, VSET2 t SH1D t H1R OUT1 HYST1 INPUT If the SET voltages must be applied before the supply voltage V+, the input current should be limited to less than 0.5mA by appropriate external resistors, usually required for voltage setting anyway. A similar precaution should be taken with the outputs if it is likely that they will be driven by other circuits to levels outside the supplies at any time. OUT2 4.7kΩ 1 OUT1 in battery applications. In line operated systems, the rate-ofrise of the supply is limited by other considerations, and is normally not a problem. FIGURE 8. SWITCHING WAVEFORMS OUT2 2 HYST1OUT2 7 3 SET1 SET2 6 HYST2 4 GND HYST2 5 20 kΩ 20 kΩ 12 pF 12 pF 12 pF 12 pF 1.6V 1.0V FIGURE 7. TEST CIRCUITS Simple Threshold Detector Figure 9 shows the simplest connection of the ICL7665S for threshold detection. From the graph 9B, it can be seen that at low input voltage OUT1 is OFF, or high, while OUT2 is ON, or low. As the input rises (e.g., at power-on) toward VNOM (usually the eventual operating voltage), OUT2 goes high on reaching VTR2. If the voltage rises above VNOM as much as VTR1, OUT1 goes low. The equation giving VSET1 and VSET2 are from Figure 9A: VSET1 = VIN Precautions Junction isolated CMOS devices like the ICL7665S have an inherent SCR or 4-layer PNPN structure distributed throughout the die. Under certain circumstances, this can be triggered into a potentially destructive high current mode. This latchup can be triggered by forward-biasing an input or output with respect to the power supply, or by applying excessive supply voltages. In very low current analog circuits, such as the ICL7665S, this SCR can also be triggered by applying the input power supply extremely rapidly (“instantaneously”), e.g., through a low impedance battery and an ON/OFF switch with short lead lengths. The rate-of-rise of the supply voltage can exceed 100V/µs in such a circuit. A low impedance capacitor (e.g., 0.05µF disc ceramic) between the V+ and GND pins of the ICL7665S can be used to reduce the rate-of-rise of the supply voltage 3-67 R11 ; VSET2 = (R11 + R21) VIN R12 (R12 + R22) Since the voltage to trip each comparator is nominally 1.3V, the value VIN for each trip point can be found from VTR1 = VSET1 (R11 + R21) R11 = 1.3 (R11 + R21) R11 for detector 1 and VTR2 = VSET2 (R12 + R22) R12 = 1.3 (R12 + R22) R12 for detector 2 ICL7665S VIN OUT ON RP2 RP1 V+ R21 OUT1 OUT2 SET1 SET2 R22 R11 R12 OFF VL2 VU2 VL1 VU1 VIN VNOM DETECTOR 2 DETECTOR 1 FIGURE 9A. CIRCUIT CONFIGURATION FIGURE 10B. TRANSFER CHARACTERISTICS FIGURE 10. THRESHOLD DETECTOR WITH HYSTERESIS VOUT OFF Either detector may be used alone, as well as both together, in any of the circuits shown here. When VIN is very close to one of the trip voltage, normal variations and noise may cause it to wander back and forth across this level, leading to erratic output ON and OFF conditions. The addition of hysteresis, making the trip points slightly different for rising and falling inputs, will avoid this condition. ON VNOM VTR2 DETECTOR 2 VTR1 DETECTOR 1 Threshold Detector with Hysteresis FIGURE 9B. TRANSFER CHARACTERISTICS FIGURE 9. SIMPLE THRESHOLD DETECTOR VIN R31 R32 V+ HYST1 HYST2 R21 R22 SET1 SET2 OUT1 OUT2 OVERVOLTAGE OVERVOLTAGE R11 R12 FIGURE 10A. CIRCUIT CONFIGURATION Figure 10A shows how to set up such hysteresis, while Figure 10B shows how the hysteresis around each trip point produces switching action at different points depending on whether VIN is rising or falling (the arrows indicated direction of change. The HYST outputs are basically switches which short out R31 or R32 when VIN is above the respective trip point. Thus if the input voltage rises from a low value, the trip point will be controlled by R1N, R2N, and R3N, until the trip point is reached. As this value is passed, the detector changes state, R3N is shorted out, and the trip point becomes controlled by only R1N and R2N, a lower value. The input will then have to fall to this new point to restore the initial comparator state, but as soon as this occurs, the trip point will be raised again. An alternative circuit for obtaining hysteresis is shown in Figure 11. In this configuration, the HYST pins put the extra resistor in parallel with the upper setting resistor. The values of the resistors differ, but the action is essentially the same. The governing equations are given in Table 1. These ignore the effects of the resistance of the HYST outputs, but these can normally be neglected if the resistor values are above about 100kΩ. VTR2 = VSET2 3-68 (R12 + R22) R12 = 1.3 (R12 + R22) R12 for detector 2 ICL7665S Applications VIN Single Supply Fault Monitor RP RP V+ R21 OUT1 R22 OUT2 R32 R31 HYST1 SET1 HYST2 SET2 R11 Figure 12 shows an over/under voltage fault monitor for a single supply. The over voltage trip point is centered around 5.5V and the under voltage trip point is centered around 4.5V. Both have some hysteresis to prevent erratic output ON and OFF conditions. The two outputs are connected in a wired OR configuration with a pullup resistor to generate a power OK signal. R12 +5V SUPPLY NO HYSTERESIS R11 + R21 Over-Voltage VTRIP = R11 R12 + R22 Over-Voltage VTRIP = R12 HYSTERESIS PER FIGURE 10A VU1 = R11 + R21 + R31 R11 x VSET1 x VSET2 V+ 324KΩ HYST1 13MΩ 5% 249KΩ R31 100KΩ OPEN VOLTAGE DETECTOR VU = 5.55V VL = 5.45V R22 HYST2 R32 VSET1 VSET2 OUT1 OUT2 R12 TABLE 1. SET-POINT EQUATIONS R21 R11 FIGURE 11. AN ALTERNATIVE HYSTERESIS CIRCUIT 7.5MΩ 5% 100KΩ V+ OPEN VOLTAGE DETECTOR VU = 4.55V VL = 4.45V 1MΩ POWER OK x VSET1 FIGURE 12. FAULT MONITOR FOR A SINGLE SUPPLY Over-Voltage VTRIP R11 + R21 VL1 = x VSET1 R11 VU2 = R12 + R22 + R32 R12 x VSET2 Under-Voltage VTRIP R12 + R22 VL2 = x VSET2 R12 HYSTERESIS PER FIGURE 11 R11 + R21 VU1 = x VSET1 R11 Over-Voltage VTRIP R21R31 VL1 = R11 + R21 + R31 x VSET1 R11 VU2 = R12 + R22 R12 x VSET2 Over-Voltage VTRIP R22R32 VL2 = R12 + R22 + R32 x VSET2 R12 3-69 Multiple Supply Fault Monitor The ICL7665S can simultaneously monitor several supplies when connected as shown in Figure 13. The resistors are chosen such that the sum of the currents through R21A, R21B, and R31 is equal to the current through R11 when the two input voltage are at the desired low voltage detection point. The current through R11 at this point is equal to 1.3V/R11. The voltage at the VSET input depends on the voltage of both supplies being monitored. The trip voltage of one supply while the other supply is at the nominal voltage will be different that the trip voltage when both supplies are below their nominal voltages. The other side of the ICL7665S can be used to detect the absence of negative supplies. The trip points for OUT1 depend on both the negative supply voltages and the actual voltage of the +5V supply. ICL7665S VSET1 is greater than 1.3V, OUT1 is low, but when VSET1 drops below 1.3V, OUT1 goes high shutting off the ICL7663S. OUT2 is used for low battery warning. When VSET2 is greater than 1.3V, OUT2 is high and the low battery warning is on. When VSET2 drops below 1.3V, OUT2 is low and the low battery warning goes off. The trip voltage for low battery warning can be set higher than the trip voltage for shutdown to give advance low battery warning before the battery is disconnected. +5V 274kΩ R21A V+ HYST1 22MΩ +5V 22 MΩ R21 49.9kΩ R11 +15V HYST2 VSET1 VSET2 OUT1 OUT2 1.02MΩ R21B 301 kΩ -5V 100kΩ 787 kΩ +5V 1 MΩ -15V Power Fail Warning and Powerup/Powerdown Reset Figure 15 shows a power fail warning circuit with powerup/powerdown reset. When the unregulated DC input is above the trip point, OUT1 is low. When the DC input drops below the trip point, OUT1 shuts OFF and the power fail warning goes high. The voltage on the input of the 7805 will continue to provide 5V out at 1A until VIN is less than 7.3V, this circuit will provide a certain amount of warning before the 5V output begins to drop. POWER OK FIGURE 13. MULTIPLE SUPPLY FAULT MONITOR Combination Low Battery Warning and Low Battery Disconnect When using rechargeable batteries in a system, it is important to keep the batteries from being overdischarged. The circuit shown in Figure 14 provides a low battery warning and also disconnects the low battery from the rest of the system to prevent damage to the battery. OUT1 is used to shutdown the ICL7663S when the battery voltage drops to the value where the load should be disconnected. As long as R31 The ICL7665S OUT2 is used to prevent a microprocessor from writing spurious data to a CMOS battery backup memory by causing OUT2 to go low when the 7805 5V output drops below the ICL7665S trip point. 100Ω R32 V+ HYST1 + R21 1MΩ HYST2 V+ R22 ICL7665S SET1 SET2 OUT1 OUT2 ICL7663S SENSE V+ - SHUTDOWN R11 GND VSET GND R12 OUT1 +5V 1A OUT2 1MΩ LOW BATTERY SHUTDOWN FIGURE 14. LOW BATTERY WARNING AND LOW BATTERY DISCONNECT 3-70 LOW BATTERY WARNING ICL7665S UNREGULATED DC INPUT 4700µF 7805 5V REGULATOR 470µF BACKUP BATTERY V+ HYST1 5.86kΩ HYST2 22MΩ ICL7665S VSET1 VSET2 OUT1 OUT2 715kΩ 2.2MΩ 130kΩ 1MΩ 1MΩ 1MΩ RESET OR WRITE ENABLE POWER FAIL WARNING FIGURE 15. POWER FAIL WARNING AND POWERUP/POWERDOWN RESET Simple High/Low Temperature Alarm AC Power Fail and Brownout Detector Figure 16 illustrates a simple high/low temperature alarm which uses the ICL7665S with an NPN transistor. The voltage at the top of R1 is determined by the VBE of the transistor and the position of R1’s wiper arm. This voltage has a negative temperature coefficient. R1 is adjusted so that VSET2 equals 1.3V when the NPN transistor’s temperature reaches the temperature selected for the high temperature alarm. When this occurs, OUT2 goes low. R2 is adjusted so that VSET1 equals 1.3V when the NPN transistor’s temperature reaches the temperature selected for the low temperature alarm. When the temperature drops below this limit, OUT1 goes low. Figure 17 shows a circuit that detects AC undervoltage by monitoring the secondary side of the transformer. The capacitor, C1, is charged through R1 when OUT1 is OFF. With a normal 100 VAC input to the transformer, OUT1 will discharge C1 once every cycle, approximately every 16.7ms. When the AC input voltage is reduced, OUT1 will stay OFF, so that C1 does not discharge. When the voltage on C1 reaches 1.3V, OUT2 turns OFF and the power fail warning goes high. The time constant, R1C1, is chosen such that it takes longer than 16.7ms to charge C1 1.3V. 3-71 ICL7665S + 5V TEMPERATURE SENSOR (GENERAL PURPOSE NPN TRANSISTOR) 470kΩ R3 LOW TEMPERATURE LIMIT ADJUST V+ HYST1 R4 22kΩ 27kΩ HYST2 22MΩ R6 ICL7665S R2 VSET1 VSET2 OUT1 OUT2 1MΩ R5 R1 10KΩ HIGH TEMPERATURE LIMIT ADJUST R7 1.5MΩ V+ ALARM SIGNAL FOR DRIVING LEDS, BELLS, ETC. 1MΩ FIGURE 16. SIMPLE HIGH/LOW TEMPERATURE ALARM 7805 5V REGULATOR 110VAC 60Hz 5V, 1A 4700µF 20V CENTERED TAPPED TRANS. +5V HYST1 601kΩ HYST2 R1 1MΩ ICL7665S VSET1 VSET2 OUT1 OUT2 100kΩ 1MΩ 1MΩ POWER FAIL WARNING C1 FIGURE 17. AC POWER FAIL AND BROWNOUT DETECTOR All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 3-72