ISL84521, ISL84522, ISL84523 ® Data Sheet August 2004 Low-Voltage, Single and Dual Supply, Quad SPST, Analog Switches Features • Drop-in Replacements for MAX4521 - MAX4523 The Intersil ISL84521, ISL84523, ISL84523 devices are CMOS, precision, quad analog switches designed to operate from a single +2V to +12V supply or from a ±2V to ±6V supply. Targeted applications include battery powered equipment that benefit from the devices’ low power consumption (<1µW), low leakage currents (1nA max), and fast switching speeds (tON = 45ns, tOFF = 15ns). A12Ω maximum RON flatness ensures signal fidelity, while channel-to-channel mismatch is guaranteed to be less than 4Ω. The ISL84521, ISL84522, ISL84523 are quad single-pole/ single-throw (SPST) devices. The ISL84521 has four normally closed (NC) switches; the ISL84522 has four normally open (NO) switches; the ISL84523 has two NO and two NC switches and can be used as a dual SPDT, or a dual 2:1 multiplexer. Table summarizes the performance of this family. For higher performance, pin compatible versions and 3mm x 3mm Quad No-Lead Flatpack (QFN) package see the ISL43140, ISL43142 data sheet. TABLE 1. FEATURES AT A GLANCE ISL84521 ISL84522 ISL84523 Number of Switches 4 4 4 Configuration All NC All NO 2 NC/2 NO ±5V RON 65Ω 65Ω 65Ω ±5V tON/tOFF 45ns/15ns 45ns/15ns 45ns/15ns 5V RON 125Ω 125Ω 125Ω 5V tON/tOFF 60ns/20ns 60ns/20ns 60ns/20ns 3V RON 260Ω 260Ω 260Ω 3V tON/tOFF 120ns/40ns 120ns/40ns 120ns/40ns Packages 16 Ld SOIC (N), 16 Ld TSSOP FN6031.3 • Four Separately Controlled SPST Switches • Pin Compatible with DG411, DG412, DG413 • ON Resistance (RON Max.) . . . . . . . . . . . . . . . . . . . 100Ω • RON Matching Between Channels. . . . . . . . . . . . . . . . . . <1Ω • Low Power Consumption (PD) . . . . . . . . . . . . . . . . . . . .<1µW • Low Leakage Current (Max at 85oC) . . . . . . . . . . . . 10nA • Fast Switching Action - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15ns • Break before Make Timing • Minimum 2000V ESD Protection per Method 3015.7 • TTL, CMOS Compatible • Pb-free available Applications • Battery Powered, Handheld, and Portable Equipment - Cellular/Mobile Phones - Pagers - Laptops, Notebooks, Palmtops • Communications Systems - Military Radios - RF “Tee” Switches • Test Equipment - Ultrasound - Electrocardiograph • Heads-Up Displays • Audio and Video Switching • General Purpose Circuits - +3V/+5V DACs and ADCs - Digital Filters - Operational Amplifier Gain Switching Networks - High Frequency Analog Switching - High Speed Multiplexing Related Literature • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” • Application Note AN557 “Recommended Test Procedures for Analog Switches” 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003, 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL84521, ISL84522, ISL84523 Pinouts (Note 1) ISL84521 (SOIC, TSSOP) TOP VIEW ISL84522 (SOIC, TSSOP) TOP VIEW 16 IN2 IN1 1 14 NC2 NC1 3 15 COM2 14 NO2 NO1 3 13 V+ V- 4 13 V+ V- 4 16 IN2 IN1 1 COM1 2 15 COM2 COM1 2 GND 5 12 N.C. GND 5 12 N.C. NC4 6 11 NC3 NO4 6 11 NO3 10 COM3 COM4 7 10 COM3 COM4 7 9 IN3 IN4 8 9 IN3 IN4 8 ISL84523 (SOIC, TSSOP) TOP VIEW IN1 1 COM1 2 NO1 3 V- 4 16 IN2 15 COM2 14 NC2 13 V+ GND 5 12 N.C. NO4 6 11 NC3 COM4 7 IN4 8 10 COM3 9 IN3 NOTE: 1. Switches Shown for Logic “0” Input. Truth Table Ordering Information ISL84521 ISL84522 LOGIC SW 1, 2, 3, 4 SW 1, 2, 3, 4 SW 1, 4 SW 2, 3 0 On Off Off On ISL84521IB 1 Off On On Off NOTE: ISL84523 Logic “0” ≤ 0.8V. Logic “1” ≥ 2.4V. Pin Descriptions PIN FUNCTION V+ Positive Power Supply Input V- Negative Power Supply Input. Connect to GND for Single Supply Configurations. GND IN COM Ground Connection Digital Control Input PART NO. TEMP. RANGE (oC) PACKAGE PKG. DWG. # -40 to 85 16 Ld SOIC (N) M16.15 ISL84521IBZ (Note 2) -40 to 85 16 Ld SOIC (N) (Pb-free) M16.15 ISL84521IV -40 to 85 16 Ld TSSOP M16.173 ISL84521IVZ (Note 2) -40 to 85 16 Ld TSSOP (Pb-free) M16.173 ISL84522IB -40 to 85 16 Ld SOIC (N) M16.15 ISL84522IBZ (Note 2) -40 to 85 16 Ld SOIC (N) (Pb-free) M16.15 ISL84522IV -40 to 85 16 Ld TSSOP M16.173 ISL84522IVZ (Note 2) -40 to 85 16 Ld TSSOP (Pb-free) M16.173 ISL84523IB -40 to 85 16 Ld SOIC (N) M16.15 ISL84523IBZ (Note 2) -40 to 85 16 Ld SOIC (N) (Pb-free) M16.15 ISL84523IV -40 to 85 16 Ld TSSOP M16.173 ISL84523IVZ (Note 2) -40 to 85 16 Ld TSSOP (Pb-free) M16.173 Analog Switch Common Pin *Add “-T” suffix to part number for tape and reel packaging. NO Analog Switch Normally Open Pin NC Analog Switch Normally Closed Pin N.C. No Internal Connection NOTE: 2. Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B. 2 ISL84521, ISL84522, ISL84523 Absolute Maximum Ratings Thermal Information V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15 to 0.3V All Other Pins (Note 3) . . . . . . . . . . . . . .((V-) - 0.3V) to ((V+) + 0.3V) Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 10mA Peak Current, IN, NO, NC, or COM (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . 20mA ESD Rating (Per MIL-STD-883 Method 3015). . . . . . . . . . . . . > 2kV Thermal Resistance (Typical, Note 4) θJA (oC/W) 16 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . 115 16 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 150 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Moisture Sensitivity (See Technical Brief TB363) All Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1 Maximum Storage Temperature Range . . . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (Lead Tips Only) Operating Conditions Temperature Range ISL8452XIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 3. Signals on NC, NO, COM, or IN exceeding V+ or V- are clamped by internal diodes. Limit forward diode current to maximum current ratings. 4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications +5V Supply PARAMETER Test Conditions: VSUPPLY = ±4.5V to ±5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 5), Unless Otherwise Specified TEST CONDITIONS TEMP (oC) (NOTE 6) MIN Full V- - V+ V 25 - 65 100 Ω TYP (NOTE 6) MAX UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON VS = ±5V, ICOM = 1.0mA, VNO or VNC = ±3V (Figure 5) RON Matching Between Channels, ∆RON VS = ±5V, ICOM = 1.0mA, VNO or VNC = ±3V RON Flatness, RFLAT(ON) VS = ±5V, ICOM = 1.0mA, VNO or VNC = ±3V (Note 8) NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) VS = ±5.5V, VCOM = ±4.5V, VNO or VNC = +4.5V (Note 7) COM OFF Leakage Current, ICOM(OFF) VS = ±5.5V, VCOM = ±4.5V, VNO or VNC = +4.5V (Note 7) COM ON Leakage Current, ICOM(ON) VS = ±5.5V, VCOM = VNO or VNC = ±4.5V (Note 7) Full - - 125 Ω 25 - 1 4 Ω Full - - 6 Ω 25 - 7 12 Ω Full - - 15 Ω nA 25 -1 0.01 1 Full -10 - 10 nA 25 -1 0.01 1 nA Full -10 - 10 nA 25 -2 0.01 2 nA Full -20 - 20 nA Full - 1.6 2.4 V DIGITAL INPUT CHARACTERISTICS Input Voltage High, VINH Input Voltage Low, VINL Input Current, IINH, IINL Full 0.8 1.6 - V VS = ±5.5V, VIN = 0V or V+ Full -1 0.03 1 µA VS = ±4.5V, VNO or VNC = ±3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V (Figure 1) 25 - 45 80 ns Full - - 100 ns VS = ±4.5V, VNO or VNC = ±3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V (Figure 1) 25 - 15 30 ns Full - - 40 ns DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF Break-Before-Make Time Delay (ISL84523), tD VS = ±5.5V, VNO or VNC = ±3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V (Figure 3) 25 5 20 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω (Figure 2) 25 - 1 5 pC NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V (Figure 7) 25 - 2 - pF COM OFF Capacitance, CCOM(OFF) f = 1MHz, VNO or VNC = VCOM = 0V (Figure 7) 25 - 2 - pF COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V (Figure 7) 25 - 5 - pF 3 ISL84521, ISL84522, ISL84523 Electrical Specifications +5V Supply PARAMETER Test Conditions: VSUPPLY = ±4.5V to ±5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 5), Unless Otherwise Specified (Continued) TEST CONDITIONS OFF Isolation RL = 50Ω, CL = 15pF, f = 100kHz, VNO or VNC = 1VRMS, (See Figures 4 and 6) Crosstalk, (Note 9) TEMP (oC) (NOTE 6) MIN TYP (NOTE 6) MAX UNITS 25 - >90 - dB 25 - <-90 - dB Full ±2 - ±6 V 25 -1 0.05 1 µA Full -1 - 1 µA 25 -1 0.05 1 µA Full -1 - 1 µA POWER SUPPLY CHARACTERISTICS Power Supply Range VS = ±5.5V, VIN = 0V or V+, Switch On or Off Positive Supply Current, I+ Negative Supply Current, INOTES: 5. VIN = Input voltage to perform proper function. 6. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 7. Leakage parameter is 100% tested at high temp, and guaranteed by correlation at 25oC. 8. Flatness is defined as the delta between the maximum and minimum RON values over the specified voltage range. 9. Between any two switches. Electrical Specifications 5V Supply PARAMETER Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 5), Unless Otherwise Specified TEST CONDITIONS TEMP (oC) MIN (NOTE 6) TYP Full 0 - V+ V MAX (NOTE 6) UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG V+ = 4.5V, ICOM = 1.0mA, VNO or VNC = 3.5V (Figure 5) 25 - 125 200 Ω Full - - 250 Ω RON Matching Between Channels, ∆RON V+ = 5V, ICOM = 1.0mA, VNO or VNC = 3.5V 25 - 2 8 Ω NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) V+ = 5.5V, VCOM = 1V, 4.5V, VNO or VNC = 4.5V, 1V (Note 7) COM OFF Leakage Current, ICOM(OFF) V+ = 5.5V, VCOM = 1V, 4.5V, VNO or VNC = 4.5V, 1V (Note 7) COM ON Leakage Current, ICOM(ON) V+ = 5.5V, VCOM = 1V, 4.5V (Note 7) ON Resistance, RON Full - - 10 Ω 25 -1 0.01 1 nA Full -10 - 10 nA 25 -1 0.01 1 nA Full -10 - 10 nA 25 -2 - 2 nA Full -20 - 20 nA DIGITAL INPUT CHARACTERISTICS Input Voltage High, VINH Full - 1.6 2.4 V Input Voltage Low, VINL Full 0.8 1.6 - V V+ = 5.5V, VIN = 0V or V+ Full -1 0.03 1 µA Turn-ON Time, tON V+ = 4.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V (Figure 1) 25 - 60 100 ns Turn-OFF Time, tOFF V+ = 4.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V (Figure 1) Input Current, IINH, IINL DYNAMIC CHARACTERISTICS Full - - 150 ns 25 - 20 50 ns Full - - 75 ns Break-Before-Make Time Delay (ISL84523), tD V+ = 5.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V (Figure 3) 25 10 30 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω (Figure 2) 25 - 1 5 pC 4 ISL84521, ISL84522, ISL84523 Electrical Specifications 5V Supply Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 5), Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS TEMP (oC) MIN (NOTE 6) TYP MAX (NOTE 6) UNITS POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = 5.5V, VIN = 0V or V+, Switch On or Off Negative Supply Current, I- Electrical Specifications 3V Supply 25 -1 0.05 1 µA Full -1 - 1 µA 25 -1 0.05 1 µA Full -1 - 1 µA Test Conditions: V+ = +2.7V to +3.6V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 5), Unless Otherwise Specified PARAMETER TEST CONDITIONS TEMP (oC) MIN (NOTE 6) TYP Full 0 - V+ V 25 - 260 500 Ω Full - - 600 Ω MAX (NOTE 6) UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG V+ = 2.7V, ICOM = 0.1mA, VNO or VNC = 1V ON Resistance, RON DIGITAL INPUT CHARACTERISTICS Input Voltage High, VINH Full - 1.6 2.4 V Input Voltage Low, VINL Full 0.8 1.6 - V V+ = 3.6V, VIN = 0V or V+ Full -1 0.03 1 µA V+ = 2.7V, VNO or VNC = 1.5V, RL = 300Ω, CL = 35pF, VIN = 0 to V+ (Figure 1) 25 - 120 250 ns Full - - 300 ns 25 - 40 80 ns Input Current, IINH, IINL DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF V+ = 2.7V, VNO or VNC = 1.5V, RL = 300Ω, CL = 35pF, VIN = 0 to V+ (Figure 1) Full - - 100 ns Break-Before-Make Time Delay (ISL84523), tD V+ = 3.6V, VNO or VNC = 1.5V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V (Figure 3) 25 15 50 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω (Figure 2) 25 - 0.5 5 pC POWER SUPPLY CHARACTERISTICS V+ = 3.6V, VIN = 0V or V+, Switch On or Off Positive Supply Current, I+ Negative Supply Current, I- 25 -1 0.05 1 µA Full -1 - 1 µA 25 -1 0.05 1 µA Full -1 - 1 µA Test Circuits and Waveforms 3V LOGIC INPUT V+ tr < 20ns tf < 20ns 50% 0V C SWITCH INPUT tOFF VOUT 90% SWITCH OUTPUT VOUT NO OR NC VNX SWITCH VNX INPUT C COM IN 90% RL 300Ω GND 0V LOGIC INPUT tON V- Logic input waveform is inverted for switches that have the opposite logic sense. Repeat test for all switches. CL includes fixture and stray capacitance. RL V OUT = V (NO or NC) -----------------------------R L + R ( ON ) FIGURE 1B. TEST CIRCUIT FIGURE 1A. MEASUREMENT POINTS FIGURE 1. SWITCHING TIMES 5 C CL 35pF ISL84521, ISL84522, ISL84523 Test Circuits and Waveforms (Continued) V+ SWITCH OUTPUT VOUT ∆VOUT RG C NO OR NC VOUT COM 3V ON ON LOGIC INPUT VG OFF GND IN 0V Q = ∆VOUT x CL LOGIC INPUT C V- Logic input waveform is inverted for switches that have the opposite logic sense. FIGURE 2A. MEASUREMENT POINTS CL Repeat test for all switches. CL includes fixture and stray capacitance. FIGURE 2B. TEST CIRCUIT FIGURE 2. CHARGE INJECTION V+ C C 3V LOGIC INPUT VOUT1 NO1 VNX COM1 VOUT2 RL1 300Ω NC2 0V COM2 CL1 35pF IN1 IN2 0V LOGIC INPUT 90% SWITCH OUTPUT VOUT2 RL2 300Ω 90% 90% SWITCH OUTPUT VOUT1 0V CL2 35pF GND 90% C tD tD V- CL includes fixture and stray capacitance. Reconfigure accordingly to test SW3 and SW4. FIGURE 3B. TEST CIRCUIT FIGURE 3A. MEASUREMENT POINTS FIGURE 3. BREAK-BEFORE-MAKE TIME (ISL84523 ONLY) V+ V+ C C RON = V1/1mA SIGNAL GENERATOR NO OR NC NO OR NC VNX IN 0V OR 2.4V 1mA COM ANALYZER 0.8V OR 2.4V IN V1 COM GND GND RL C C V- V- Repeat test for all switches. Repeat test for all switches. FIGURE 4. OFF ISOLATION TEST CIRCUIT 6 FIGURE 5. RON TEST CIRCUIT ISL84521, ISL84522, ISL84523 Test Circuits and Waveforms (Continued) V+ C SIGNAL GENERATOR NO1 OR NC1 V+ 50Ω COM1 NO OR NC IN2 IN 0V or 2.4V IN2 0V OR 2.4V COM2 ANALYZER NO CONNECTION NO2 OR NC2 0V OR 2.4V IMPEDANCE ANALYZER COM GND GND RL C V- V- FIGURE 6. CROSSTALK TEST CIRCUIT Detailed Description The ISL84521, ISL84522, ISL84523 quad analog switches offer precise switching capability from a bipolar ±2V to ±6V or a single 2V to 12V supply with low on-resistance (65Ω) and high speed switching (tON = 45ns, tOFF = 15ns). The devices are especially well suited to portable battery powered equipment thanks to the low operating supply voltage (2V), low power consumption (1µW) and low leakage currents (1nA max). High frequency applications also benefit from the wide bandwidth, and the very high OFF isolation and crosstalk rejection. Supply Sequencing And Overvoltage Protection As with any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and to V- (Figure 8). To prevent forward biasing these diodes, V+ and V- must be applied before any input signals, and input signal voltages must remain between V+ and V-. If these conditions cannot be guaranteed, then one of the following two protection methods should be employed. Logic inputs can easily be protected by adding a 1kΩ resistor in series with the input (Figure 8). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. Adding a series resistor to the switch input defeats the purpose of using a low RON switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (Figure 8). These additional diodes limit the analog signal from 1V below V+ to 1V above V-. The low leakage current performance is 7 FIGURE 7. CAPACITANCE TEST CIRCUIT unaffected by this approach, but the switch resistance may increase, especially at low supply voltages. OPTIONAL PROTECTION DIODE V+ OPTIONAL PROTECTION RESISTOR INX VNO OR NC VCOM VOPTIONAL PROTECTION DIODE FIGURE 8. OVERVOLTAGE PROTECTION Power-Supply Considerations The ISL8452X construction is typical of most CMOS analog switches, in that they have three supply pins: V+, V-, and GND. V+ and V- drive the internal CMOS switches and set their analog voltage limits, so there are no connections between the analog signal path and GND. Unlike switches with a 13V maximum supply voltage, the ISL8452X 15V maximum supply voltage provides plenty of room for the 10% tolerance of 12V supplies (±6V or 12V single supply), as well as room for overshoot and noise spikes. This family of switches performs equally well when operated with bipolar or single voltage supplies, and bipolar supplies need not be symmetrical. The minimum recommended supply voltage is 2V or ±2V. It is important to note that the input signal range, switching times, and ON-resistance degrade at lower supply voltages. Refer to the electrical specification tables and Typical Performance Curves for details. ISL84521, ISL84522, ISL84523 V+ and GND power the internal logic (thus setting the digital switching point) and level shifters. The level shifters convert the logic levels to switched V+ and V- signals to drive the analog switch gate terminals, so switch parameters especially RON - are strong functions of both supplies. Logic-Level Thresholds V+ and GND power the internal logic stages, so V- has no affect on logic thresholds. This switch family is TTL compatible (0.8V and 2.4V) over a V+ supply range of 2.5V to 10V. At 12V the VIH level is about 2.7V, so for best results use a logic family the provides a VOH greater than 3V. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation. High-Frequency Performance In 50Ω systems, signal response is reasonably flat even past 300MHz (Figure 15), with a small signal -3dB bandwidth in excess of 400MHz, and a large signal bandwidth exceeding 300MHz. An off switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feedthrough from a switch’s input to its output. OFF Isolation is the resistance to this feedthrough, while Crosstalk indicates the amount of feedthrough from one switch to another. Figure 16 details the high OFF Isolation and Crosstalk rejection provided by this family. At 10MHz, OFF isolation is about 50dB in 50Ω systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease OFF Isolation and Crosstalk rejection due to the voltage divider action of the switch OFF impedance and the load impedance. Leakage Considerations Reverse ESD protection diodes are internally connected between each analog-signal pin and both V+ and V-. One of these diodes conducts if any analog signal exceeds V+ or V-. Virtually all the analog leakage current comes from the ESD diodes to V+ or V-. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V+ or V- and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and V- pins constitutes the analog-signalpath leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and GND. Typical Performance Curves TA = 25oC, Unless Otherwise Specified 90 300 70 60 50 40 250 85oC 200 25oC 150 -40oC 100 V- = 0V 200 85oC 150 25oC 85oC 25oC -40oC -40oC V+ = 2.7V V- = 0V 50 225 85oC 175 125 75 140 100 50 ICOM = 1mA 250 RON (Ω) RON (Ω) VCOM = (V+) - 1V ICOM = 1mA V- = -5V 80 85oC 110 V+ = 5V 25oC V+ = 3.3V -40oC V- = 0V V- = 0V 25oC 80 0 3 4 5 6 7 8 V+ (V) 9 10 11 FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE 8 12 50 -40oC 0 1 2 3 VCOM (V) 4 FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE 5 ISL84521, ISL84522, ISL84523 Typical Performance Curves TA = 25oC, Unless Otherwise Specified (Continued) 180 5 VS = ±2V ICOM = 1mA 140 85oC 25oC 2.5 100 -40oC V+ = 3.3V VS = ±3V 100 85oC 0 25oC 80 Q (pC) RON (Ω) 60 120 -40oC 60 V+ = 5V 2.5 40 VS = ±5V 90 VS = ±5V 85oC 70 -5 25oC 50 -7.5 -40oC 30 -5 -4 -3 -2 -1 0 1 2 3 4 -5 -2.5 0 VCOM (V) 5 VCOM (V) 250 200 50 tOFF (ns) V- = 0V 250 85oC 25 -40oC 0 300 25oC 50 85oC -40oC 0 50 V- = 0V 40 200 85oC 150 25oC 0 10 2 3 25oC 20 -40oC 50 85oC 30 100 4 5 6 7 8 9 10 11 V+ (V) FIGURE 13. TURN - ON TIME vs SUPPLY VOLTAGE 9 12 VCOM = (V+) - 1V V- = -5V -40oC 75 25oC 100 25oC 100 -40oC 150 tON (ns) 125 VCOM = (V+) - 1V V- = -5V 5 FIGURE 12. CHARGE INJECTION vs SWITCH VOLTAGE FIGURE 11. ON RESISTANCE vs SWITCH VOLTAGE 25oC 2.5 -40oC 2 3 4 5 6 7 8 9 10 11 V+ (V) FIGURE 14. TURN - OFF TIME vs SUPPLY VOLTAGE 12 ISL84521, ISL84522, ISL84523 -10 VIN = 0.2VP-P GAIN -30 VIN = 5VP-P -3 0 PHASE 45 VIN = 0.2VP-P 90 VIN = 5VP-P 135 180 RL = 50Ω 10 100 FREQUENCY (MHz) FIGURE 15. FREQUENCY RESPONSE Die Characteristics SUBSTRATE POTENTIAL (POWERED UP): VTRANSISTOR COUNT: ISL84521: 188 ISL84522: 188 ISL84523: 188 PROCESS: Si Gate CMOS 10 600 CROSSTALK (dB) 0 20 RL = 50Ω 30 -40 40 -50 50 -60 60 ISOLATION -70 70 -80 80 OFF ISOLATION (dB) 3 1 10 V+ = 3V to 12V or -20 VS = ±2V to ±5V VS = ±5V PHASE (DEGREES) NORMALIZED GAIN (dB) Typical Performance Curves TA = 25oC, Unless Otherwise Specified (Continued) CROSSTALK -90 90 -100 100 -110 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 16. CROSSTALK AND OFF ISOLATION 110 500M ISL84521, ISL84522, ISL84523 Small Outline Plastic Packages (SOIC) M16.15 (JEDEC MS-012-AC ISSUE C) 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE N INCHES INDEX AREA H 0.25(0.010) M B M SYMBOL E -B- 1 2 3 L SEATING PLANE -A- h x 45o A D -C- e B 0.25(0.010) M C 0.10(0.004) C A M B S MILLIMETERS MAX MIN MAX NOTES A 0.053 0.069 1.35 1.75 - A1 0.004 0.010 0.10 0.25 - B 0.014 0.019 0.35 0.49 9 C 0.007 0.010 0.19 0.25 - D 0.386 0.394 9.80 10.00 3 E 0.150 0.157 3.80 4.00 4 e µα A1 MIN 0.050 BSC 1.27 BSC - H 0.228 0.244 5.80 6.20 - h 0.010 0.020 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 8o 0o N α 16 0o 16 7 8o Rev. 1 02/02 NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 11 ISL84521, ISL84522, ISL84523 Thin Shrink Small Outline Plastic Packages (TSSOP) M16.173 N 16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INDEX AREA E 0.25(0.010) M 2 INCHES E1 GAUGE PLANE -B1 B M MIN MAX MIN MAX NOTES A - 0.043 - 1.10 - 0.05 0.15 - 0.85 0.95 - A2 L 0.05(0.002) -A- SYMBOL A1 3 A D -C- e α c 0.10(0.004) C A M B S 0.002 0.037 0.0075 0.012 0.19 0.30 9 c 0.0035 0.008 0.09 0.20 - D 0.193 0.201 4.90 5.10 3 E1 0.169 0.177 4.30 4.50 4 0.026 BSC E 0.246 L 0.020 N α NOTES: 0.006 0.033 b e A2 A1 b 0.10(0.004) M 0.25 0.010 SEATING PLANE MILLIMETERS 0.65 BSC 0.256 6.25 0.028 0.50 16 0o 6.50 0.70 16 8o 0o 6 7 8o 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AB, Issue E. Rev. 1 2/02 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12