RF1K49157 Data Sheet August 1999 6.3A, 30V, 0.030 Ohm, Single N-Channel LittleFET™ Power MOSFET File Number 4012.5 Features • 6.3A, 30V This Single N-Channel power MOSFET is manufactured using an advanced MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits, gives optimum utilization of silicon, resulting in outstanding performance. It was designed for use in applications such as switching regulators, switching convertors, motor drivers, relay drivers, and low voltage bus switches. This device can be operated directly from integrated circuits. • rDS(ON) = 0.030Ω • Temperature Compensating PSPICE™ Model • Peak Current vs Pulse Width Curve • UIS Rating Curve • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Formerly developmental type TA49157. Symbol Ordering Information PART NUMBER RF1K49157 PACKAGE MS-012AA NC (1) DRAIN (8) SOURCE (2) DRAIN (7) SOURCE (3) DRAIN (6) GATE (4) DRAIN (5) BRAND RF1K49157 NOTE: When ordering, use the entire part number. For ordering in tape and reel, add the suffix 96 to the part number, i.e., RF1K4915796. Packaging JEDEC MS-012AA BRANDING DASH 5 1 2 3 8-122 4 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. LittleFET™ is a trademark of Intersil Corporation. PSPICE™ is a trademark of MicroSim Corporation. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 RF1K49157 Absolute Maximum Ratings TA = 25oC Unless Otherwise Specified Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (Pulse width = 1s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Pulsed (Figure 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating (Figure 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation TA = 25oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg RF1K49157 30 30 ±20 UNITS V V V 6.3 Refer to Peak Current Curve Refer to UIS Curve A 2 0.016 -55 to 150 W W/oC oC 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications TA = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V, (Figure 12) 30 - - V Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA, (Figure 11) 1 - 3 V TA = 25oC - - 1 µA TA = 150oC - - 50 µA - - ±100 nA VGS = 10V - - 0.030 Ω VGS = 4.5V - - 0.060 Ω - - 85 ns Zero Gate Voltage Drain Current IDSS Gate to Source Leakage Current Drain to Source On Resistance IGSS rDS(ON) Turn-On Time tON Turn-On Delay Time td(ON) ID = 6.3A (Figures 9, 10) VDD = 15V, ID ≈ 6.3A, RL = 2.38Ω, VGS = 10V, RGS = 25Ω - 22 - ns - 43 - ns td(OFF) - 125 - ns tf - 85 - ns tOFF - - 265 ns - 70 88 nC - 38 48 nC - 2.8 3.5 nC - 1575 - pF - 700 - pF - 200 - pF Fall Time Turn-Off Time Total Gate Charge VGS = ±20V tr Rise Time Turn-Off Delay Time VDS = 30V, VGS = 0V Qg(TOT) VGS = 0V to 20V Gate Charge at 10V Qg(10) VGS = 0V to 10V Threshold Gate Charge Qg(TH) VGS = 0V to 2V Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS RθJA Thermal Resistance Junction-to-Ambient VDD = 24V, ID = 6.3A, RL = 3.81Ω (Figure 14) VDS = 25V, VGS = 0V, f = 1MHz (Figure 13) - - 62.5 oC/W MIN TYP MAX UNITS ISD = 6.3A - - 1.25 V ISD = 6.3A, dISD/dt = 100A/µs - - 60 ns Pulse width = 1s Device mounted on FR-4 material Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage Reverse Recovery Time SYMBOL VSD trr 8-123 TEST CONDITIONS RF1K49157 1.2 7 1.0 6 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER Typical Performance Curves 0.8 0.6 0.4 0.2 5 4 3 2 1 0 0 25 125 50 75 100 TA , AMBIENT TEMPERATURE (oC) 0 25 150 FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE 50 75 100 125 TA, AMBIENT TEMPERATURE (oC) 150 FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs AMBIENT TEMPERATURE ZθJA, NORMALIZED THERMAL IMPEDANCE 10 1 0.5 PDM 0.2 0.1 0.1 t1 t2 0.05 0.02 0.01 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA SINGLE PULSE 0.01 10-3 10-2 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) 102 103 FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE TJ = MAX RATED, TA = 25oC 10 5ms 10ms 1 100ms 0.1 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 0.01 0.1 1s VDSS(MAX) = 30V DC 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA 8-124 100 300 IDM, PEAK CURRENT CAPABILITY (A) ID, DRAIN CURRENT (A) 100 VGS = 20V VGS = 10V TA = 25oC 100 10 THERMAL IMPEDANCE MAY LIMIT CURRENT IN THIS REGION FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I 1 10-5 = I25 10-4 150 - TA 125 10-3 10-2 10-1 t, PULSE WIDTH (s) 100 FIGURE 5. PEAK CURRENT CAPABILITY 101 RF1K49157 Typical Performance Curves If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 50 ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) 50 (Continued) STARTING TJ = 25oC 10 STARTING TJ = 150oC 1 0.1 40 VGS = 5V 30 VGS = 4V 20 10 1 10 tAV, TIME IN AVALANCHE (ms) NOTE: 100 0 0 1 Refer to Intersil Application Notes AN9321 and AN9322. -55oC 25oC VDD = 15V 150oC 40 30 20 10 0 0 1.5 3.0 4.5 6.0 VGS, GATE TO SOURCE VOLTAGE (V) 250 200 5 ID = 6.3A ID = 3.5A ID = 1.75A 150 100 50 0 2 8 6 4 VGS, GATE TO SOURCE VOLTAGE (V) 10 FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 2.0 2.0 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 6.3A VGS = VDS, ID = 250µA NORMALIZED GATE THRESHOLD VOLTAGE NORMALIZED ON RESISTANCE 4 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDD = 15V ID = 15A 7.5 FIGURE 8. TRANSFER CHARACTERISTICS 3 FIGURE 7. SATURATION CHARACTERISTICS rDS(ON), ON-STATE RESISTANCE (mΩ) ID(ON), ON-STATE DRAIN CURRENT (A) PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 2 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY 50 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX TA = 25oC VGS = 20V VGS = 10V VGS = 7V 1.5 1.0 0.5 0 -80 -40 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 8-125 160 1.5 1.0 0.5 0 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE RF1K49157 Typical Performance Curves (Continued) 2500 ID = 250µA 2000 1.5 C, CAPACITANCE (pF) 1.0 0.5 CISS 1500 1000 COSS 500 0 -80 -40 0 40 80 120 TJ , JUNCTION TEMPERATURE (oC) 0 160 FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE CRSS 0 5 10 15 20 VDS, DRAIN TO SOURCE VOLTAGE (V) 25 FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 10.0 30 VDS , DRAIN-SOURCE VOLTAGE (V) VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD 22.5 7.5 VDD = BVDSS RL = 4.76Ω IG(REF) = 0.8mA VGS = 10V 15 5.0 PLATEAU VOLTAGES IN DESCENDING ORDER: VDD = BVDSS VDD = 0.75 BVDSS VDD = 0.50 BVDSS VDD = 0.25 BVDSS 7.5 0 I G ( REF ) 20 ---------------------I G ( ACT ) t, TIME (µs) 2.5 VGS , GATE-SOURCE VOLTAGE (V) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 2.0 0 I G ( REF ) 80 ---------------------I G ( ACT ) NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 14. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS tP + RG VDS IAS VDD VDD - VGS DUT 0V tP IAS 0.01Ω tAV FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT 8-126 FIGURE 16. UNCLAMPED ENERGY WAVEFORMS RF1K49157 Test Circuits and Waveforms (Continued) tON tOFF td(ON) td(OFF) tf tr VDS RL + RG - 90% 10% 10% 0 VDD 90% 90% DUT VGS 0 50% 50% PULSE WIDTH 10% VGS FIGURE 18. RESISTIVE SWITCHING WAVEFORMS FIGURE 17. SWITCHING TIME TEST CIRCUIT VDS VDD RL Qg(TOT) VDS VGS = 20V VGS Qg(10) + VDD VGS = 10V VGS - VGS = 2V DUT 0 IG(REF) Qg(TH) IG(REF) 0 FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORM Soldering Precautions The soldering process creates a considerable thermal stress on any semiconductor component. The melting temperature of solder is higher than the maximum rated temperature of the device. The amount of time the device is heated to a high temperature should be minimized to assure device reliability. Therefore, the following precautions should always be observed in order to minimize the thermal stress to which the devices are subjected. 1. Always preheat the device. 2. The delta temperature between the preheat and soldering should always be less than 100oC. Failure to preheat the device can result in excessive thermal stress which can damage the device. 8-127 3. The maximum temperature gradient should be less than 5oC per second when changing from preheating to soldering. 4. The peak temperature in the soldering process should be at least 30oC higher than the melting point of the solder chosen. 5. The maximum soldering temperature and time must not exceed 260oC for 10 seconds on the leads and case of the device. 6. After soldering is complete, the device should be allowed to cool naturally for at least three minutes, as forced cooling will increase the temperature gradient and may result in latent failure due to mechanical stress. 7. During cooling, mechanical stress or shock should be avoided. RF1K49157 PSPICE Electrical Model SUBCKT RF1K49157 2 1 3 ; rev 3/14/95 CA 12 8 1.834e-9 CB 15 14 1.72e-9 CIN 6 8 1.416e-9 DRAIN 2 RLDRAIN DBREAK RDRAIN 11 6 8 ESG 16 EVTHRESH + 19 - + LGATE GATE 1 LDRAIN 2 5 1.0e-9 LGATE 1 9 1.04e-9 LSOURCE 3 7 0.237e-9 MOS1 16 6 8 8 MSTRONG M = 0.99 MOS2 16 21 8 8 MWEAK M = 0.01 RBREAK 17 18 RBREAKMOD 1 RDRAIN 5 16 RDRAINMOD 4.39e-3 RGATE 9 20 1.53 RIN 6 8 1e9 RLDRAIN 2 5 1.0 RLGATE 1 9 10.4 RLSOURCE 3 7 0.237 RSOURCE 8 7 RSOURCEMOD 4.44e-3 RTHRESH 22 8 RTHRESMOD 1 RZTEMPCO 18 19 RZTEMPCOMOD 1 S1A S1B S2A S2B 5 10 EBREAK 11 7 17 18 34.89 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRESH 6 21 19 8 1 EZTEMPCO 20 6 18 22 1 IT 8 17 1 LDRAIN DPLCAP DBODY 7 5 DBDMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD EZTEMPCO 9 20 + 18 22 RGATE RLGATE EBREAK 21 8 6 + DBODY 17 18 - MOS2 MOS1 CIN RIN LSOURCE 8 RSOURCE SOURCE 3 7 RLSOURCE S1A 12 13 8 S1B S2A RBREAK 15 14 13 18 17 S2B RZTEMPCO 13 CB + CA + 6 8 EGS - 14 IT 5 8 EDS VBAT + - 22 RVTHRESH 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD VBAT 22 19 DC 1 .MODEL DBDMOD D (IS = 1.14e-12 RS = 6.01e-3 TRS1 = 1.05e-4 TRS2 = -2.46e-5 CJO = 2.62e-9 TT = 2.44e-8) .MODEL DBREAKMOD D (RS = 4.89e-1 TRS1 = 2.11e-3 TRS2 = -3.19e-6) .MODEL DPLCAPMOD D (CJO = 1.007e-9 IS = 1e-30 N = 10) .MODEL MSTRONG NMOS (VTO = 2.567 KP = 33.21 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAK NMOS (VTO=2.0225 KP = 33.21 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL RBREAKMOD RES (TC1 = 9.59e-4 TC2 = -2.87e-7) .MODEL RDRAINMOD RES (TC1 = 8.08e-3 TC2 = 1.6e-5) .MODEL RSOURCEMOD RES (TC1=0 TC2=0) .MODEL RTHRESHMOD RES (TC1=-6.4e-4 TC2=-8.1e-6) .MODEL RZTEMPCOMOD RES (TC1 = -2.43e-3 TC2 = 1.57e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6.47 VOFF= -4.47) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.47 VOFF= -6.47) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.3 VOFF= 1.7) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 1.7 VOFF= -3.3) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991. 8-128 19 - RF1K49157 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. 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