Datasheet

UTC MC14511
CMOS IC
BCD-TO-SEVEN SEGMENT
LATCH/DECODER/DRIVER
DESCRIPTION
The UTC MC14511 BCD–to–seven segment
latch/decoder/driver is constructed with complementary
MOS (CMOS) enhancement mode devices and NPN
bipolar output drivers in a single monolithic structure. The
circuit provides the functions of a 4-bit storage latch, an
8421 BCD-to-seven segment decoder, and an output
drive capability. Lamp test (LT), blanking (BI), and latch
enable (LE) inputs are used to test the display, to turn-off
or pulse modulate the brightness of the display, and to
store a BCD code, respectively. It can be used with
seven-segment light-emitting diodes (LED),
incandescent, fluorescent, gas discharge, or liquid crystal
readouts either directly or indirectly.
Applications include instrument (e.g., counter, DVM,
etc.) display driver, computer/calculator display driver,
cockpit display driver, and various clock, watch, and
timer uses.
SOP-16
DIP-16
FEATURES
* Low Logic Circuit Power Dissipation
* High–Current Sourcing Outputs (Up to 25 mA)
* Latch Storage of Code
* Blanking Input
* Lamp Test Provision
* Readout Blanking on all Illegal Input Combinations
* Lamp Intensity Modulation Capability
* Time Share (Multiplexing) Facility
* Supply Voltage Range = 3.0 V ~ 18 V
* Capable of Driving Two Low-power TTL Loads, One
Low-power Schottky TTL Load or Two HTL Loads Over
the Rated Temperature Range
* Chip Complexity: 216 FETs or 54 Equivalent Gates
* Triple Diode Protection on all Inputs
UTC
UNISONIC TECHNOLOGIES CO., LTD.
1
QW-R502-021,B
UTC MC14511
CMOS IC
PIN CONFIGURATION
B
1
16
VDD
C
2
15
f
LT
3
14
g
BI
4
13
a
LE
5
12
b
D
6
11
c
A
7
10
d
Vss
8
9
e
a
g
f
e
b
c
d
DISPLAY
0
1
2
3
4
5
6
7
c
1
0
1
1
0
1
1
1
1
1
1
1
0
0
0
0
0
0
d
1
0
1
0
1
1
0
1
1
0
1
0
0
0
0
0
0
0
*
8
9
TRUTH TABLE
Inputs
LE
BI
LT
D C B A
a
b
X
X
0
X X X X
1
1
X
0
1
X X X X
0
0
0
1
1
0 0 0 0
1
1
0
1
1
0 0 0 1
0
1
0
1
1
0 0 1 0
1
1
0
1
1
0 0 1 1
1
1
0
1
1
0 1 0 0
0
1
0
1
1
0 1 0 1
1
0
0
1
1
0 1 1 0
0
0
0
1
1
0 1 1 1
1
1
0
1
1
1 0 0 0
1
1
0
1
1
1 0 0 1
1
1
0
1
1
1 0 1 0
0
0
0
1
1
1 0 1 1
0
0
0
1
1
1 1 0 0
0
0
0
1
1
1 1 0 1
0
0
0
1
1
1 1 1 0
0
0
0
1
1
1 1 1 1
0
0
1
1
1
X X X X
X=Don’t Care
*Depends upon the BCD code previously applied when LE=0
UTC
Outputs
e
1
0
1
0
1
0
0
0
1
0
1
0
0
0
0
0
0
0
f
1
0
1
0
0
0
1
1
1
0
1
1
0
0
0
0
0
0
g
1
0
0
0
1
1
1
1
1
0
1
1
0
0
0
0
0
0
UNISONIC TECHNOLOGIES CO., LTD.
Display
8
Blank
0
1
2
3
4
5
6
7
8
9
Blank
Blank
Blank
Blank
Blank
Blank
*
2
QW-R502-021,B
UTC MC14511
CMOS IC
This device contains protection circuitry to protect the inputs against damage due to high static voltages or electric
fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than
maximum rated voltages to this high-impedance circuit. A destructive high current mode may occur if Vin and Vout are
not constrained to the range:
VSS ≤ (Vin or Vout) ≤ VDD.
Due to the sourcing capability of this circuit, damage can occur to the device if VDD is applied, and the outputs are
shorted to VSS and are at a logical 1 (See Maximum Ratings).
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD).
BLOCK DIAGRAM
BI 4
13 a
A
7
12 b
11 c
B
1
10 d
9 e
15 f
C
2
14 g
LT 3
D
6
LE 5
UTC
VDD=PIN 16
Vss=PIN 8
UNISONIC TECHNOLOGIES CO., LTD.
3
QW-R502-021,B
UTC MC14511
CMOS IC
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to Vss) (Note 1)
PARAMETER
SYMBOL
RATINGS
UNIT
DC Supply Voltage Range
VDD
-0.5 ~ +18.0
Input Voltage Range, All Inputs
Vin
-0.5 ~ VDD+0.5
DC Current Drain per Input Pin
I
10
Power Dissipation, per Package
PD
500
(Note 2)
Maximum Output Drive Current
IOHmax
25
(Source) per Output
Maximum Continuous Output
POHmax
50
Power (Source) per Output (Note 3)
Operating Temperature Range
Ta
-55 ~ +125
Storage Temperature Range
Tstg
-65 ~ +150
Note 1: Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Temperature Derating:
Plastic “P and D/DW” Packages: - 7.0 mW/℃ From 65℃ ~ 125℃
Note 3: POHmax = IOH (VDD – VOH)
V
V
mA
mW
mA
mA
℃
℃
ELECTRICAL CHARACTERISTICS (Voltages Referenced to Vss)
PARAMETER
SYMBOL
Output Voltage
VOL
VOH
VDD
Vdc
5.0
10
15
5.0
10
15
Input Voltage #
VIL
VIH
Output Drive Voltage
VOH
UTC
5.0
10
15
5.0
10
15
5.0
10
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.05
0.05
0.05
V
4.1
9.1
14.1
0
0
0
4.57
9.58
14.59
2.25
4.50
6.75
1.5
3.0
4.0
“0” Level
Vin=VDD or 0
“1” Level
Vin=0 or VDD
“0” Level
Vo=3.8 or 0.5 V
Vo=8.8 or 1.0 V
Vo=13.8 or 1.5V
“1” Level
Vo=0.5 or 3.8 V
Vo=1.0 or 8.8 V
Vo=1.5 or 13.8 V
IOH=0mA
IOH=5.0mA
IOH=10mA
IOH=15mA
IOH=20mA
IOH=25mA
IOH=0mA
IOH=5.0mA
IOH=10mA
IOH=15mA
IOH=20mA
IOH=25mA
Source
3.5
7.0
11
4.1
3.9
3.4
Source
9.1
9.0
8.6
V
2.75
5.50
8.25
4.57
4.24
4.12
3.94
3.70
3.54
9.58
9.26
9.17
9.04
8.90
8.70
V
V
V
V
UNISONIC TECHNOLOGIES CO., LTD.
4
QW-R502-021,B
UTC MC14511
PARAMETER
SYMBOL
CMOS IC
VDD
Vdc
15
Output Drive Voltage
VOH
Output Drive Current
IOL
Input Current
Input Capacitance
Quiescent Current
Iin
Cin
IDD
Total Supply Current
(Notes 5 & 6)
5.0
10
15
15
5.0
10
15
5.0
10
15
TEST CONDITIONS
IOH=0mA
IOH=5.0mA
IOH=10mA
IOH=15mA
IOH=20mA
IOH=25mA
VOL=0.4V
VOL=0.5V
VOL=1.5V
Source
MIN
TYP
14.1
14.59
14.27
14.18
14.07
13.95
13.70
0.88
2.25
8.8
±0.00001
±0.1
μA
5.0
0.005
0.010
0.015
7.5
5.0
10
20
pF
14
13.6
Sink
(Per Package) Vin=0 or
VDD,
Iout=0μA
0.51
1.3
3.4
MAX
V
mA
(Dynamic plus Quiescent,
IT=(1.9μA/kHz) f+IDD
Per Package)
IT=(3.8μA/kHz) f+IDD
IT
(CL=50pF on all outputs, all
IT=(5.7μA/kHz) f+IDD
buffers switching)
Note 4: Noise immunity specified for worst–case input combination.
Noise Margin for both “1” and “0” level =
1.0 V min @ VDD = 5.0 V
2.0 V min @ VDD = 10 V
2.5 V min @ VDD = 15 V
Note 5: The formulas given are for the typical characteristics only at 25℃.
Note 6: To calculate total supply current at loads other than 50 pF:
IT (CL) = IT(50 pF) + 3.5 x 10–3 (CL – 50) VDDf
Where: IT is inμA (per package), CL in pF, VDD in Vdc, and f in kHz is input frequency.
UTC
UNIT
UNISONIC TECHNOLOGIES CO., LTD.
μA
μA
5
QW-R502-021,B
UTC MC14511
CMOS IC
SWITCHING CHARACTERISTICS (Note 7) (CL=50pF, Ta=25℃)
VDD
Vdc
TEST CONDITIONS
5.0
10
15
5.0
10
15
5.0
10
15
TYP
MAX
tTLH=(0.40 ns/pF) CL+20 ns
tTLH=(0.25 ns/pF) CL+17.5 ns
tTLH=(0.20 ns/pF) CL+15 ns
tTHL=(1.5 ns/pF) CL+50 ns
tTHL=(0.75 ns/pF) CL+37.5 ns
tTHL=(0.55 ns/pF) CL+37.5 ns
tPLH=(0.40 ns/pF) CL+620 ns
tPLH=(0.25 ns/pF) CL+237.5 ns
tPLH=(0.20 ns/pF) CL+165 ns
40
30
25
125
75
65
640
250
175
80
60
50
250
150
130
1280
500
350
5.0 tPHL=(1.3 ns/pF) CL+655 ns
tPHL
10 tPHL=(0.60 ns/pF) CL+260 ns
15 tPHL=(0.35 ns/pF) CL+182.5 ns
Blank Propagation Delay
5.0 tPLH=(0.30 ns/pF) CL+585 ns
Time
tPLH
10 tPLH=(0.25 ns/pF) CL+187.5 ns
15 tPLH=(0.15 ns/pF) CL+142.5 ns
5.0 tPHL=(0.85 ns/pF) CL+442.5 ns
10 tPHL=(0.45 ns/pF) CL+177.5 ns
tPHL
15 tPHL=(0.35 ns/pF) CL+142.5 ns
Lamp Test Propagation
5.0 tPLH=(0.45 ns/pF) CL+290.5 ns
tPLH
Delay Time
10 tPLH=(0.25 ns/pF) CL+112.5 ns
15 tPLH=(0.20 ns/pF) CL+80 ns
5.0 tPHL=(1.3 ns/pF) CL+248 ns
tPHL
10 tPHL=(0.45 ns/pF) CL+102.5 ns
15 tPHL=(0.35 ns/pF) CL+72.5 ns
Setup Time
5.0
tsu
10
15
Hold Time
5.0
10
th
15
Latch Enable Pulse Width
5.0
tWL
10
15
Note 7: The formulas given are for the typical characteristics only.
720
290
200
600
200
150
485
200
160
313
125
90
313
125
90
1440
580
400
750
300
220
970
400
320
625
250
180
625
250
180
PARAMETER
SYMBOL
Output Rise Time
tTLH
Output Fall Time
tTHL
Data Propagation Delay
Time
UTC
tPLH
Min
100
40
30
60
40
30
520
220
130
UNIT
ns
ns
ns
ns
ns
ns
ns
260
110
65
UNISONIC TECHNOLOGIES CO., LTD.
ns
6
QW-R502-021,B
UTC MC14511
CMOS IC
SWITCHING TIME WAVEFORMS
20 ns
20 ns
VDD
90%
A, B, AND C
50%
1
10%
2f
50% DUTY CYCLE
ANY OUTPUT
Vss
VOH
50%
VOL
Input LE low, and Inputs D, BI and LT high.
f in respect to a system clock.
All outputs connected to respective C L loads.
Figure 1. Dynamic Power Dissipation Signal Waveforms
20 ns
VDD
90%
LE
50%
10%
20 ns
th
20 ns
VDD
90%
tsu
Vss
VDD
50%
INPUT C
INPUT C
10%
90%
OUTPUT g
50%
Vss
Vss
VOH
tPHL
tPLH
50%
VOH
10%
VOL
tTLH
tTHL
OUTPUT g
VOL
(a) Inputs D and LE low, and Inputs A, B, BI
and LT high
(b) Input D low, Inputs A, B, BI and LT high
20 ns
20 ns
90%
VDD
50%
LE
10%
Vss
tWL
(c) Data DCBA strobed into Iatches.
Figure 2. Dynamic Signal Waveforms
UTC
UNISONIC TECHNOLOGIES CO., LTD.
7
QW-R502-021,B
UTC MC14511
CMOS IC
CONNECTIONS TO VARIOUS DISPLAY READOUTS
LIGHT EMITTING DIODE (LED) READOUT
VDD
VDD
COMMON
ANODE LED
COMMON
CATHODE LED
〜
〜1.7V
〜 1.7V
~
Vss
Vss
INCANDESCENT READOUT
VDD
VDD
FLUORESCENT READOUT
VDD
**
DIRECT
(LOW BRIGHTNESS)
FILAMENT
SUPPLY
Vss
Vss
Vss OR APPROPRIATE
VOLTAGE BELOW Vss.
(CAUTION: Maximum working voltage=18.0V)
GAS DISCHARGE READOUT
VDD
APPROPRIATE
VOLTAGE
LIQUID CRYSTAL(LCD) READOUT
VDD
EXCITATION
(SQUARE WAVE, Vss TO V DD)
1/4 OF MC14070B
Vss
Vss
** A filament pre-warm resistor is recommended to reduce filament
thermal shock and increase the effective cold resistance of the
filament.
UTC
,
Direct dc drive of LCD s not recommended for life of
LCD readouts.
UNISONIC TECHNOLOGIES CO., LTD.
8
QW-R502-021,B
UTC MC14511
CMOS IC
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
UTC
UNISONIC TECHNOLOGIES CO., LTD.
9
QW-R502-021,B
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