UNISONIC TECHNOLOGIES CO., LTD M3000 Preliminary LINEAR INTEGRATED CIRCUIT PIR INFRARED REMOTE CONTROL CIRCUIT DESCRIPTION The M3000 is a passive infra-red controller using analog mixing digital design technique and is manufactured by CMOS process. The M3000 needs only few external components in application circuit. It can be applied in controller of light, electric switching, burglar alarm, and so on. FEATURES * Low Power CMOS Technology * CMOS High Input Impedance Operational Amplifiers * Bi-Directional Level Detector / Excellent noise Immunity * Built-in Power up Disable & Output Pulse Control Logic * Dual Mode : Retriggerable & Non-Retriggerable ORDERING INFORMATION Ordering Number M3000G-S16-R Package SOP-16 www.unisonic.com.tw Copyright © 2010 Unisonic Technologies Co., Ltd Packing Tape Reel 1 of 6 QW-R502-473.a M3000 CMOS IC PIN CONFIGURATIONS A 1 16 1OUT VOUT 2 15 1IN- RR1 3 14 1IN+ RC1 4 13 2IN- RC2 5 12 2OUT RR2 6 11 VDD VSS 7 10 IB 8 9 VC VRF/RESET PIN DESCRIPTIONS PIN NO. 1 2 3 4 5 6 7 PIN NAME A VOUT RR1 RC1 RC2 RR2 VSS I/O I O 8 VRF I 9 VC I 10 11 12 13 14 15 16 IB VDD 2OUT 2IN1IN+ 1IN1OUT O I I I O PIN DESCRIPTION Retriggerable & non-retriggerable mode select Detector output pin (active high) Output pulse width control (Tx) Output pulse width control (Tx) Trigger inhibit control (Ti) Trigger inhibit control (Ti) Ground RESET & voltage reference input (normally high. Low=reset) Trigger disable input (VC>0.2Vdd=enable; VC<0.2Vdd=disable) Op-amp input bias current setting Supply voltage 2nd stage Op-amp output 2nd stage Op-amp inverting input 1st stage Op-amp non-inverting input 1st stage Op-amp inverting input 1st stage Op-amp output UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 2 of 6 QW-R502-473.a M3000 CMOS IC BLOCK DIAGRAM A 1IN+ 1IN1OUT 2IN2OUT VC 1 14 15 16 VM 13 12 + - OP1 + - OP2 VH VL V2 9 VR VREF/RESET + - COP1 VS + - COP2 + - 8 VH VM VL UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw VR VDD 12 IB 2 STATES CONTROL COP3 11 VOUT Tx 3 4 RR1 RC1 Ti 6 5 RR2 RC2 7 Vss 3 of 6 QW-R502-473.a M3000 CMOS IC ABSOLUTE MAXIMUM RATINGS PARAMETER DC Supply Voltage Input/ Output Voltage Max. Output Current (VDD=5.0V) SYMBOL VDD VIN /VOUT IOUT TOPR TSTG Operating Temperature Storage Temperature RATINGS -0.3~6.0 VSS-0.3~VDD+0.3 10 -20~+70 -40~+125 UNIT V V mA °C °C DC ELECTRICAL CHARACTERISTICS (TA =+25°C,unless otherwise specified) PARAMETER DC Supply Voltage Average Supply Current Op-Amp Input Offset Voltage Op-Amp Input Offset Current Op-Amp Gain Op-Amp Common Mode Rejection Ration Op-Amp HIGH Level Output Voltage Op-Amp LOW Level Output Voltage VC High Level Input Voltage VC Low Level Input Voltage VOUT High Level Output Voltage VOUT Low Level Output Voltage Pin A High Level Input Voltage Pin A Low Level Input Voltage SYMBOL VDD IDD VOS IOS AVO CMRR VYH VYL VRH VRL VOH VOL VAH VAL TEST CONDITIONS No Load www.unisonic.com.tw VDD=3V VDD=5V VDD=5V VDD=5V VDD=5V, RL=1.5MΩ VDD=5V, RL=1.5MΩ VDD=5V, RL=500KΩ connect to 1/2VDD VRF＝VDD=5V VDD=5V, IOH=0.5mA VDD=5V, IOH=0.1mA VDD=5V VDD=5V UNISONIC TECHNOLOGIES CO., LTD MIN 3 TYP MAX 5 50 100 50 50 60 60 4.25 0.75 1.1 0.9 4 0.4 3.5 1.5 UNIT V μA mV nA dB dB V V V V V V V V 4 of 6 QW-R502-473.a M3000 CMOS IC FUNCTIONAL DESCRIPTIONS 1. Re-Triggerable Mode Re-Triggerable Waveform Operational amplifier OP1 composed sensor signal pre-processing circuit. The amplified signal coupled to the operational amplifier OP2, and elevated DC level to VM (≈0.5VDD), The output signal V2 input to Bi-directional level detector(COP1&COP2), detected the effective signal Vs. As the VH≈0.7VDD, VL≈0.3VDD, while VDD=5V, it is immune to the ±1V noise interference and can improve system reliability. COP3 is a condition comparator. When the input voltage Vc<VR(≈0.2VDD), COP3 output is low, it disabled the Vs transmission to State Control circuit; When Vc>VR, COP3 output is high, chip access to extension time period. When pin A connect to "0", any change of V2 have been ignored until the end of Tx period, which called non-retriggerable mode. When the Tx period ended, Vo jump back to the low level, chip access to the lock period Ti. During the Ti period, any changes of V2 can not make Vo jumping to valid state (high level), it can inhibit a variety of interference when the load changed. 2. Non-Retriggerable mode V2 VH VL VS A VC VOUT Tx Ti Tx Ti Non-Retriggerable Waveform During the time of Vc="0", A="0"，signal Vs can not trigger Vo to a valid state; When Vc="1", A="1", Vs can repeatable trigger Vo to the valid state, and keep the state in Tx period. In the Tx period, if Vs jump to "1", then Vo extend to an another Tx; if Vs keep "1" state, Vo maintains the valid state; if Vs keep "0 "state, after the period of Tx, Vo change to invalid state, and in the Ti time, any change of Vs can not trigger Vo to a valid state. UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 5 of 6 QW-R502-473.a M3000 473 R3 TYPICAL APPLICATIONS CIRCUIT 105 CMOS IC NOTE: R3 is a light dependent resistor which has low resistance under strong ambient light. This cause the detector to be operational only when the detection area is sufficient dark. UTC assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all UTC products described or contained herein. UTC products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 6 of 6 QW-R502-473.a