NCP4303A/B Secondary Side Synchronous Rectification Driver for High Efficiency SMPS Topologies The NCP4303A/B is a full featured controller and driver tailored to control synchronous rectification circuitry in switch mode power supplies. Thanks to its versatility, it can be used in various topologies such as flyback, forward and Half Bridge Resonant LLC. The combination of externally adjustable minimum on and off times helps to fight the ringing induced by the PCB layout and other parasitic elements. Therefore, a reliable and noise less operation of the SR system is insured. The extremely low turn off delay time, high sink current capability of the driver and automatic package parasitic inductance compensation system allow to maximize synchronous rectification MOSFET conduction time that enables further increase of SMPS efficiency. Finally, a wide operating VCC range combined with two versions of driver voltage clamp eases implementation of the SR system in 24 V output applications. http://onsemi.com MARKING DIAGRAM 8 8 1 SOIC−8 D SUFFIX CASE 751 xx A WL, L YY, Y WW, W G or G Features • Self−Contained Control of Synchronous Rectifier in CCM, DCM, • • • • • • • • • • • • • • • and QR Flyback Applications Precise True Secondary Zero Current Detection with Adjustable Threshold Automatic Parasitic Inductance Compensation Input Typically 40 ns Turn off Delay from Current Sense Input to Driver Zero Current Detection Pin Capability up to 200 V Ultrafast Trigger Interface to External Signal for CCM operation Disable Input to Enter Standby or Low Consumption Mode Adjustable Minimum On Time Independent of VCC Level Adjustable Minimum Off Time Independent of VCC Level 5 A / 2.5 A Peak Current Sink / Source Drive Capability Operating Voltage Range up to 30 V Gate Drive Clamp of Either 12 V (NCP4303A) or 6 V (NCP4303B) Low Startup and Standby Current Consumption Maximum Frequency of Operation up to 500 kHz SOIC−8 Package These are Pb−Free Devices 1 XXXXX ALYWX G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package PINOUT INFORMATION VCC Min_Toff Min_Ton Trig/Disable 1 2 3 4 8 7 6 5 DRV GND COMP CS ORDERING INFORMATION Package Shipping† NCP4303ADR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel NCP4303BDR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Typical Applications • • • • Notebook Adapters High Power Density AC/DC Power Supplies Gaming Consoles All SMPS with High Efficiency Requirements © Semiconductor Components Industries, LLC, 2010 April, 2010 − Rev. 1 1 Publication Order Number: NCP4303/D NCP4303A/B Figure 1. Typical Application Example – LLC Converter Figure 2. Typical Application Example − DCM or QR Flyback Converter http://onsemi.com 2 NCP4303A/B PIN FUNCTION DESCRIPTION Pin No. Pin Name Function 1 VCC Supplies the driver Pin Description 2 Min_toff Minimum off time adjust Adjust the minimum off time period by connecting resistor to ground. 3 Min_ton Minimum on time adjust Adjust the minimum on time period by connecting resistor to ground. 4 TRIG/Disable Forced reset input This ultrafast input turns off the SR MOSFET in CCM applications. Activates sleep mode if pulled up for more than 100 ms. 5 CS Current sense of the SR MOSFET This pin detects if the current flows through the SR MOSFET and/or its body diode. Basic turn off detection threshold is 0 mV. A resistor in series with this pin can modify the turn off threshold if needed. 6 COMP Compensation inductance connection 7 GND IC ground 8 DRV Gate driver output VCC supply terminal of the controller. Accepts up to 30 V continuously. Use as a Kelvin connection to auxiliary compensation inductance. If SR MOSFET package parasitic inductance compensation is not used (like for SMT MOSFETs), connect this pin directly to GND pin. Ground connection for the SR MOSFET driver and VCC decoupling capacitor. Ground connection for minimum ton, toff adjust resistors and trigger input. GND pin should be wired directly to the SR MOSFET source terminal/soldering point using Kelvin connection. Driver output for the SR MOSFET. Figure 3. Internal Circuit Architecture http://onsemi.com 3 NCP4303A/B MAXIMUM RATINGS Symbol Value Unit VCC IC supply voltage Rating −0.3 to 30 V VDRV Driver output voltage −0.3 to 17 V VCS Current sense input dc voltage −4 to 200 V VCsdyn Current sense input dynamic voltage (tpw = 200 ns) −10 to 200 V VTRIG Trigger input voltage −0.3 to 10 V VMin_ton, VMin_toff Min_Ton and Min_Toff input voltage −0.3 to 10 V I_Min_Toff, I_Min_Toff Min_Ton and Min_Toff current −10 to +10 mA Static voltage difference between GND and COMP pins (internally clamped) −3 to 10 V Dynamic voltage difference between GND and COMP pins (tpw = 200 ns) −10 to 10 V −5 to 5 mA 180 °C/W VGND−COMP VGND−COMP_dyn ICOMP Current into COMP pin RqJA Thermal Resistance Junction−to−Air, SOIC version, A/B version TJmax Maximum junction temperature TSmax Storage Temperature Range TLmax Lead temperature (Soldering, 10 s) ESD Capability, Human Body Model except pin VCS – pin 5, HBM ESD Capability on pin 5 is 650 V ESD Capability, Machine Model 150 °C −60 to +150 °C 300 °C 2 kV 200 V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device series contains ESD protection and exceeds the following tests: Pin 1*8: Human Body Model 2000 V per JEDEC Standard JESD22−A114E. Machine Model Method 200 V pre JEDEC Standard JESD22−A115−A 2. This device meets latchup tests defined by JEDEC Standard JESD78. http://onsemi.com 4 NCP4303A/B ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V, Cload = 0 nF, R_min_ton = R_min_toff = 10 kW, Vtrig = 0 V, f_CS = 100 kHz, DC_CS = 50%, VCS_high = 4 V, VCS_low=−1 V unless otherwise noted) Symbol Rating Pin Min Typ Max Unit SUPPLY SECTION VCC_on Turn−on threshold level (VCC going up) 1 9.3 9.9 10.5 V VCC_off Minimum operating voltage after turn−on (VCC going down) 1 8.3 8.9 9.5 V VCC hysteresis 1 0.8 1.0 1.3 V ICC1_A ICC1_B Internal IC consumption (no output load on pin 8, Fsw = 500 kHz, RTon_min = RToff_min = 5 kW) 1 − − 4.7 4 − − mA ICC2_A ICC2_B Internal IC consumption (Cload = 1 nF on pin 8, Fsw = 400 kHz, RTon_min = RToff_min = 5 kW) 1 − − 9.3 6.4 − − mA ICC3_A ICC3_B Internal IC consumption (Cload = 10 nF on pin 8, Fsw = 400 kHz, RTon_min = RToff_min = 5 kW) 1 − − 54 34 − − mA ICC_SDM Startup current consumption (VCC = VCC_on − 0.1 V) and consumption during light load (disable) mode, (Fsw = 500 kHz, Vtrig = 5 V) 1 − 390 550 mA ICC_SDM NS Startup current consumption (VCC = VCC_on − 0.1 V) and consumption during light load (disable) mode, (Vcs = 0 V, Vtrig = 5 V) 1 − 280 450 mA tr_A Output voltage rise−time for A version (Cload = 10 nF), (Note 3) 8 − 120 − ns tr_B Output voltage rise−time for B version (Cload = 10 nF), (Note 3) 8 − 80 − ns tf_A Output voltage fall−time for A version (Cload = 10 nF), (Note 3) 8 − 50 − ns tf_B Output voltage fall−time for B version (Cload = 10 nF), (Note 3) 8 − 35 − ns Roh Driver source resistance (Note 3) 8 − 1.8 7 W Rol Driver sink resistance 8 − 1 2 W Output source peak current (Note 3) 8 − 2.5 − A VCC_hyste DRIVE OUTPUT IDRV_pk(source) IDRV_pk(sink) Output sink peak current (Note 3) 8 − 5 − A VDRV(H)_A Driver high level output voltage on A version (Cload = 1 nF) 8 10 − − V VDRV(H)_A Driver high level output voltage on A version (Cload = 10 nF) 8 11.8 − − V VDRV(H)_B Driver high level output voltage on B version (Cload = 1 nF) 8 5 − − V VDRV(H)_B Driver high level output voltage on B version (Cload = 10 nF) 8 6 − − V VDRV(min_A) Minimum drive output voltage for A version (VCC = VCC_off + 200 mV) 8 8.3 − − V VDRV(min_B) Minimum drive output voltage for B version (VCC = VCC_off + 200 mV) 8 4.5 − − V VDRV(CLMP_A) Driver clamp voltage for A version, (12 V < VCC < 28 V, minimum Cload = 1 nF) 8 − 12 16 V VDRV(CLMP_B) Driver clamp voltage for B version, (12 V < VCC < 28 V, minimum Cload = 1 nF) 8 − 7 8.3 V CS INPUT Tpd_on The total propagation delay from CS input to DRV output turn on (VCS goes down from 4 V to −1 V, tf_CS = 5 ns, COMP pin connected to GND) 5, 8 − 60 90 ns Tpd_off The total propagation delay from CS input to DRV output turn off (VCS goes up from −1 V to 4 V, tr_CS = 5 ns, COMP pin connected to GND), (Note 3) 5, 8 − 40 55 ns Ishift_CS Current sense input current source (VCS = 0 V) 5 95 100 105 mA Vth_cs_on Turn on current sense input threshold voltage 5, 8 −120 −85 −50 mV Vth_cs_off Current sense pin turn off threshold voltage, COMP pin connected to GND (Note 3) 5, 8 −1 − 0 mV Compensation inverter gain (Note 3) 5,6,8 − −1 − − Gcomp 3. Guaranteed by design. http://onsemi.com 5 NCP4303A/B ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V, Cload = 0 nF, R_min_ton = R_min_toff = 10 kW, Vtrig = 0 V, f_CS = 100 kHz, DC_CS = 50%, VCS_high = 4 V, VCS_low=−1 V unless otherwise noted) Symbol Rating Pin Min Typ Max Unit 5 − − 1 mA Minimum trigger pulse duration 4 30 − − ns Vtrig Trigger input threshold voltage (Vtrig goes up) 4 1.5 − 2.5 V tp_trig Propagation delay from trigger input to the DRV output (Vtrig goes up from 0 to 5 V tr_trig = 5 ns) 4 − − 30 ns Light load turn off filter duration 4 − 100 − ms 4 − − 550 ns 4 − 10 − uA CS INPUT ICS_Leakage CS input leakage current, VCS = 200 Vdc TRIGGER/DISABLE INPUT Ttrig_pw ttrig_light_load ttrig_light_load_rec IC operation recovery time when leaving light load disable mode (Vtrig goes down from 5 to 0 V tf_trig = 5 ns) Itrig Trigger input pull down current (Vtrig = 5 V) MINIMUM Ton AND Toff ADJUST Ton_min Minimum Ton period (RT_on_min = 0 W) 3 − 300 − ns Toff_min Minimum Toff period (RT_off_min = 0 W) 2 − 620 − ns Ton_min Minimum Ton period (RT_on_min = 10 kW) 3 0.9 1.0 1.1 ms Toff_min Minimum Toff period (RT_off_min = 10 kW) 2 0.9 1.0 1.1 ms Ton_min Minimum Ton period (RT_on_min = 50 kW) 3 − 4.8 − ms Toff_min Minimum Toff period (RT_off_min = 50 kW) 2 − 4.8 − ms 3. Guaranteed by design. http://onsemi.com 6 NCP4303A/B 9.96 8.9 9.94 8.88 9.92 8.86 9.9 8.84 VCCoff (V) VCCon (V) TYPICAL CHARACTERISTICS 9.88 9.86 8.82 8.8 9.84 8.78 9.82 8.76 9.8 −40 −25 −10 5 20 35 50 65 80 95 110 125 8.74 −40 −25 −10 5 50 65 80 95 TEMPERATURE (°C) Figure 4. VCC Startup Voltage Figure 5. VCC Turn−off Voltage 420 1.065 410 ICC_SDM (mA) 1.06 VCC_Hyste (V) 35 TEMPERATURE (°C) 1.07 1.055 1.05 1.045 110 125 400 390 380 370 1.04 1.035 −40 −25 −10 5 20 35 50 65 80 95 360 −40 −25 −10 5 110 125 20 35 50 65 80 TEMPERATURE (°C) TEMPERATURE (°C) Figure 6. VCC Hysteresis Figure 7. Startup Current 11.8 95 110 125 95 110 125 12.06 12.04 11.6 12.02 VDRV(H)_A (V) 11.4 VDRV(H)_A (V) 20 11.2 11 10.8 12 11.98 11.96 11.94 11.92 10.6 11.9 10.4 −40 −25 −10 5 20 35 50 65 80 TEMPERATURE (°C) 95 11.88 −40 −25 −10 5 110 125 Figure 8. Driver High Level – A Version, VCC = 12 V and Cload = 1 nF 20 35 50 65 80 TEMPERATURE (°C) Figure 9. Driver High Level− A Version, VCC = 12 V and Cload = 10 nF http://onsemi.com 7 NCP4303A/B 5.95 7.02 5.9 7 5.85 6.98 5.8 6.96 VDRV(H)_B (V) VDRV(H)_B (V) TYPICAL CHARACTERISTICS 5.75 5.7 5.65 6.92 6.9 5.6 6.88 5.55 6.86 5.5 −40 −25 −10 5 20 35 50 65 80 95 6.84 −40 −25 −10 5 110 125 35 50 65 80 95 110 125 TEMPERATURE (°C) Figure 10. Driver High Level – B Version, VCC = 12 V and Cload = 1 nF Figure 11. Driver High Level – B Version, VCC = 12 V and Cload = 10 nF 9.96 5.9 9.94 5.8 9.92 5.7 9.9 9.88 9.86 9.84 5.6 5.5 5.4 5.3 9.82 5.2 9.8 9.78 −40 −25 −10 5 20 35 50 65 80 95 110 125 5.1 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 12. Minimal Driver High Level – A Version, VCC = VCC_OFF + 0.2 V and Cload = 0 nF Figure 13. Minimal Driver High Level – B Version, VCC = VCC_OFF + 0.2 V and Cload = 0 nF 12.8 14.2 14 12.6 13.8 VDRV(CLMP_A) (V) 12.4 VDRV(CLMP_A) (V) 20 TEMPERATURE (°C) VDRV(min_B) (V) VDRV(min_A) (V) 6.94 12.2 12 11.8 11.6 13.6 13.4 13.2 13 12.8 12.6 11.4 12.4 11.2 −40 −25 −10 5 20 35 50 65 80 95 110 125 12.2 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 14. Driver Clamp Level – A Version, VCC = 28 V and Cload = 1 nF Figure 15. Driver Clamp Level – A Version, VCC = 28 V and Cload = 10 nF http://onsemi.com 8 NCP4303A/B TYPICAL CHARACTERISTICS 7.35 6.15 7.3 6.1 7.25 6.05 VDRV(CLMP_B) (V) VDRV(CLMP_B) (V) 6.2 6 5.95 5.9 5.85 5.8 7 6.95 6.9 5.7 6.85 20 35 50 65 80 95 6.8 −40 −25 −10 5 110 125 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 16. Driver Clamp Level – B Version, VCC = 28 V and Cload = 1 nF Figure 17. Driver Clamp Level – B Version, VCC = 28 V and Cload = 10 nF 70 45 40 60 35 50 30 TPD_off (ns) TPD_on (ns) 7.1 7.05 5.75 5.65 −40 −25 −10 5 40 30 20 25 20 15 10 10 5 0 −40 −25 −10 5 20 35 50 65 80 95 110 125 0 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 18. CS to DRV Turn−on Propagation Delay Figure 19. CS to DRV Turn−off Propagation Delay 100.5 −40 100 −50 −60 Vth_CS_on (mV) 99.5 Ishift_CS (mA) 7.2 7.15 99 98.5 98 −70 −80 −90 −100 97.5 −110 97 −40 −25 −10 5 20 35 50 65 80 TEMPERATURE (°C) 95 110 125 −120 −40 −25 −10 5 20 35 50 65 80 TEMPERATURE (°C) 95 Figure 21. CS Turn−on Threshold Figure 20. CS Pin Shift Current http://onsemi.com 9 110 125 NCP4303A/B TYPICAL CHARACTERISTICS 18 2.15 16 14 12 2.05 Tp_trig (ns) Vtrig (V) 2.1 2 10 8 6 4 1.95 2 1.9 −40 −25 −10 5 20 35 50 65 80 95 110 125 0 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 22. Trigger Input Threshold Voltage Figure 23. Propagation Delay from Trigger Input to DRV Turn−off 117 485 116.5 480 Ttrig−light_load_rec (ns) Ttrig−light_load (ms) 116 115.5 115 114.5 114 475 470 465 113.5 113 −40 −25 −10 5 20 35 50 65 80 TEMPERATURE (°C) 95 110 125 460 −40 −25 −10 5 Figure 24. Light Load Transition Timer Duration 95 110 125 Figure 25. Light Load to Normal Operation Recovery Time 12 290 10 285 Ton_min (ns) 8 Itrig (mA) 20 35 50 65 80 TEMPERATURE (°C) 6 4 280 275 270 2 0 −40 −25 −10 5 20 35 50 65 80 95 110 125 265 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 26. Trigger Input Pulldown Current Figure 27. Minimum on Time @ Rt_on_min = 0 W http://onsemi.com 10 NCP4303A/B TYPICAL CHARACTERISTICS 1047 976 1046 975 974 1044 Toff_min (ns) Ton_min (ns) 1045 1043 1042 973 972 971 1041 970 1040 1039 −40 −25 −10 5 20 35 50 65 80 95 110 125 969 −40 −25 −10 5 20 35 50 65 80 95 TEMPERATURE (°C) TEMPERATURE (°C) Figure 28. Minimum on Time @ Rt_on_min = 10 kW Figure 29. Minimum Off Time @ Rt_off_min = 10 kW 5340 110 125 5050 5320 5000 Toff_min (ns) 5280 5260 5240 5220 4950 4900 4850 5200 5180 −40 −25 −10 5 20 35 50 65 80 95 110 125 4800 −40 −25 −10 5 20 35 50 65 80 95 TEMPERATURE (°C) TEMPERATURE (°C) Figure 30. Minimum on Time @ Rt_on_min = 53 kW Figure 31. Minimum Off Time @ Rt_off_min = 53 kW 640 635 630 Toff_min (ns) Ton_min (ns) 5300 625 620 615 610 605 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) Figure 32. Minimum Off Time @ Rt_off_min = 0 W http://onsemi.com 11 110 125 NCP4303A/B APPLICATION INFORMATION General Description To overcome issues after turn on and off events, the NCP4303 provides adjustable minimum on time and off time blanking periods. Blanking times can be adjusted independently of IC VCC using resistors connected to GND. If needed, blanking periods can be modulated using additional components. An ultrafast trigger input helps to implement synchronous rectification systems in CCM applications (like CCM flyback or forward). The time delay from trigger input to driver turn off event is 12 ns (typically). Additionally, the trigger input can be used to disable the IC and activate a low consumption standby mode. This feature can be used to decrease standby consumption of an SMPS. Finally, the NCP4303 features a special input that can be used to automatically compensate for SR MOSFET parasitic inductance effect. This technique achieves the maximum available on−time and thus optimizes efficiency when a MOSFET in standard package (like TO220 or TO247) is used. If a SR MOSFET in SMT package with negligible inductance is used, the compensation input is connected to GND pin. The NCP4303 is designed to operate either as a standalone IC or as a companion IC to a primary side controller to help achieve efficient synchronous rectification in switch mode power supplies. This controller features a high current gate driver along with high−speed logic circuitry to provide appropriately timed drive signals to a synchronous rectification MOSFET. With its novel architecture, the NCP4303 has enough versatility to keep the synchronous rectification system efficient under any operating mode. The NCP4303 works from an available bias supply with voltage range from 10.4 V to 28 V (typical). The wide VCC range allows direct connection to the SMPS output voltage of most adapters such as notebook and LCD TV adapters. As a result, the NCP4303 simplifies circuit operation compared to other devices that require specific bias power supply (e.g. 5 V). The high voltage capability of the VCC pin is also a unique feature designed to allow operation for a broader range of applications. Precise turn off threshold of the current sense comparator together with accurate offset current source allows the user to adjust for any required turn off current threshold of the SR MOSFET switch using a single resistor. Compared to other SR controllers that provide turn off thresholds in the range of −10 mV to −5 mV, the NCP4303 offers a turn off threshold of 0 mV that in combination with a low RDS(on) SR MOSFET significantly reduces the turn off current threshold and improves efficiency. Zero Current Detection and parasitic inductance compensation Figure 33 shows the internal connection of the ZCD circuitry on the current sense input. The synchronous rectification MOSFET is depicted with it’s parasitic inductances to demonstrate operation of the compensation system. http://onsemi.com 12 NCP4303A/B Figure 33. ZCD Sensing Circuitry Functionality When the voltage on the secondary winding of the SMPS reverses, the body diode of M1 starts to conduct current and the voltage of M1’s drain drops approximately to −1 V. The CS pin sources current of 100 mA that creates a voltage drop on the Rshift_cs resistor. Once the voltage on the CS pin is lower than Vth_cs_on threshold, M1 is turned on. Because of parasitic impedances, significant ringing can occur in the application. To overcome sudden turn−off due to mentioned ringing, the minimum conduction time of the SR MOSFET is activated. Minimum conduction time can be adjusted using R_Min_Ton resistor. The SR MOSFET is turned−off as soon as the voltage on the CS pin is higher than Vth_cs_off. For the same ringing reason, a minimum off time timer is asserted once the turn−off is detected. The minimum off time can be externally adjusted using R_Min_Toff resistor. MOSFET M1 channel conducts when the secondary current decreases, therefore the turn−off time depends on its RDS(on). The 0 mV threshold provides an optimum switching period usage while keeping enough time margin for the gate turn off. The Rshift_cs resistor provides the designer with the possibility to modify (increase) the actual turn−off current threshold. http://onsemi.com 13 NCP4303A/B Figure 34. ZCD Comparators Thresholds and Blanking Periods Timing If no Rshift_cs resistor is used, the turn−on and turn−off thresholds are fully given by the CS input specification (please refer to parametric table). Once non−zero Rshift_cs resistor is used, both thresholds move down (i.e. higher MOSFET turn off current) as the CS pin offset current causes a voltage drop that is equal to: V_Rshift_cs + Rshift_cs * Ishift_cs Note that Rshift_cs impact on turn−on threshold is less critical compare to turn−off threshold. If using a SR MOSFET in TO220 package (or other package which features leads), the parasitic inductance of the package leads causes a turn−off current threshold increase. This is because current that flows through the SR MOSFET has quite high di(t)/dt that induces error voltage on the SR MOSFET leads inductance. This error voltage, that is proportional to the secondary current derivative, shifts the CS input voltage to zero when significant current still flows through the channel. Zero current threshold is thus detected when current still flows through the SR MOSFET channel – please refer to Figure 35 for better understanding. As a result, the SR MOSFET is turned−off prematurely and the efficiency of the SMPS is not optimized. (eq. 1) Final turn−on and turn off thresholds can be then calculated as: VCS_turn_on + Vth_CS_on * (Rshift_cs * Ishift_cs) (eq. 2) VCS_turn_off + Vth_CS_off * (Rshift_cs * Ishift_cs) (eq. 3) http://onsemi.com 14 NCP4303A/B Figure 35. Waveforms from SR System Using MOSFET in TO220 Package without Parasitic Inductance Compensation – SR MOSFET Channel Conduction Time is Reduced Note that the efficiency impact of the error caused by parasitic inductance increases with lower RDS(on) MOSFETs and/or higher operating frequency. The NCP4303 offers a way to compensate for MOSFET parasitic inductances effect − refer to Figure 36. Figure 36. Package Parasitic Inductances Compensation Principle Dedicated input (COMP) offers the possibility to use an external compensation inductance (wire strap or PCB). If the value of this compensation inductance is Lcomp = Ldrain + Lsource, the compensation voltage created on this inductance is exactly the same as the sum of error voltages created on drain and source parasitic inductances i.e. VLdrain + VLsource. The internal analog inverter (Figure 33) inverts compensation voltage Vl_comp and offsets the current sense comparator turn−off threshold. The current sense comparator thus “sees” between its terminals a voltage that would be seen on the SR MOSFET channel resistance in case the lead inductances wouldn’t exist. The current sense comparator of the NCP4303 is thus able to detect the secondary current zero crossing very precisely. More over, the secondary current turn−off threshold is then di(t)/t independent thus the NCP4303 allows to increase operating frequency of the SR system. One should note that the parasitic resistance of compensation inductance should be as low as possible compared to the SR MOSFET channel and leads resistance otherwise compensation is not efficient. http://onsemi.com 15 NCP4303A/B Typical value of compensation inductance for a TO220 package is 7 nH. The parasitic inductance can differ depends on how much are the leads shortened during the assembly process. The compensation inductance design has to be done with enough margin to overcome situation that the system will become overcompensated due to packaging and assembly process variations. Waveforms from the application with compensated SR system can be seen in Figure 37. One can see the conduction time has been significantly increased and turn−off current reduced. Figure 37. Waveforms from SR System Using MOSFET in TO220 Package with Parasitic Inductance Compensation – SR MOSFET Channel Conduction Time Optimized comparator. Ideally the CS turn–off comparator should detect voltage that is caused by secondary current directly on the SR MOSFET channel resistance. Practically this is not possible because of the bonding wires, leads and soldering. To assure the best efficiency results, a Kelvin connection of the SR controller to the power circuitry should be implemented (i.e. GND pin should be connected to the SR MOSFET source soldering point and current sense pin should be connected to the SR MOSFET drain soldering point). Any impact of PCB parasitic elements on the SR controller functionality is then avoided. Figures 38 and 39 show examples of SR system layouts using parasitic inductance compensation (i.e. for low RDS(on) MOSFET in TO220 package ) and not using compensation (i.e. for higher RDS(on) MOSFET in TO220 package or SMT package MOSFETs ). Note that using the compensation system is only beneficial in applications that are using a low RDS(on) MOSFET in non−SMT package. Using the compensation method allows for optimized efficiency with a standard TO220 package that in turn results in reduced costs, as the SMT MOSFETs usually require reflow soldering process and more expensive PCB. From the above paragraphs and parameter tables it is evident that turn−off threshold precision is quite critical. If we consider a SR MOSFET with RDS(on) of 1 mW, the 1 mV error voltage on the CS pin results in a 1 A turn−off current threshold difference. Thus the PCB layout is very critical when implementing the SR system. Note that the CS turn−off comparator as well as compensation inputs are referred to the GND pin. Any parasitic impedance (resistive or inductive − talking about mW and nH values) can cause a high error voltage that is then evaluated by the CS http://onsemi.com 16 NCP4303A/B Figure 38. Recommended Layout When Parasitic Inductance Compensation is Used Figure 39. Recommended Layout When Parasitic Inductance Compensation is Not Used Trigger/Disable input disabled from the end of the minimum off time period to the end of the minimum on time period. This technique is used to: a) Overcome false turn−off of the gate driver in case the synchronization pulse is too wide and comes twice per switching period (in HB and HB LLC applications). b) Increase trigger input noise immunity against the parasitic ringing that is present in the SMPS layout during the turn on process. The NCP4303 features an ultrafast trigger input that exhibits a typically of 12 ns delay from its activation to the turn−off of the SR MOSFET. The main purpose of this input is to turn−off the SR MOSFET in applications operating in CCM mode via a signal coming from the primary side. The primary trigger signal rising edge should come to the trigger input before the secondary voltage reverses. Thus the driver signal for primary switch should be delayed – refer to figure 46 for one possible method of delaying the primary driving signal in CCM flyback topology. The trigger signal is Figure 40. Trigger Input Internal Connection http://onsemi.com 17 NCP4303A/B Figure 41. Trigger Input Functionality Waveforms standby mode. The IC consumption is reduced to 390 mA during the standby mode. When trigger input voltage is decreased again the device recovers operation in 500 ns. If the IC is enabled in the time the current sense input voltage is negative (secondary current flows through the Shottky or body diode) the IC waits for another switching cycle to turn−on the SR MOSFET – refer to Figures 42, 43 and 44. The NCP4303 operation can be disabled using the trigger/disable input. If the trigger/disable input is pulled up (above 1.5 V) the driver is disabled immediately. In some cases, the driver is activated one more time by the current sense because the trigger signal is still blanked. This final drive pulse lasts only for the minimum on time period. If the trigger signal is high for more than 100 ms, the driver enters Figure 42. Operating Waveforms for the Trig/Disable Input – Device Sleep Mode Transition – Case 1 http://onsemi.com 18 NCP4303A/B Figure 43. Operating Waveforms for the Trig/Disable Input – Device Sleep Mode Transition – Case 2 Figure 44. Operating Waveforms for the Trig/Disable Input –Wake−up from Sleep Mode If the trigger signal comes periodically and the trigger pulse overlaps the SR MOSFET drain positive voltage (i.e. overlaps the whole SR MOSFET body diode off time period), the driver is disabled for the next cycle – refer to Figure 45. Figure 45. Operating Waveforms for the Trig/Disable Input with a Trigger Signal that is Periodical and Overlaps CS (SR MOSFET Vds) High Level Note that the trigger input is an ultrafast input that doesn’t feature any internal filtering and reacts even on very narrow voltage pulses. Thus it is wise to keep this input on a low impedance path and provide it with a clean triggering signal. http://onsemi.com 19 NCP4303A/B A typical application schematic of a CCM flyback converter with the NCP4303 driver can be seen in Figure 46. In this application the trigger signal is taken directly from the flyback controller driver output and transmitted to the secondary side by pulse transformer TR2. Because the trigger input is rising edge sensitive, it is not necessary to transmit the entire primary driver pulse to the secondary. The coupling capacitor C5 is used to allow pulse transformer core reset and also to prepare a needle pulse (a pulse with width lower than 100 ns) to be transmitted to the NCP4303 trigger input. The advantage of needle trigger pulse usage is that the required volt−second product of the pulse transformer is very low and that allows the designer to use very small and cheap magnetics. The trigger transformer can be for instance prepared on a small toroidal ferrite core with diameter of 8 mm. Proper safety insulation between primary and secondary sides can be easily assured by using triple insulated wire for one or even both windings. The primary MOSFET gate voltage rising edge is delayed by external circuitry consisting of transistors Q1, Q2 and surrounding components. The primary MOSFET is thus turned−on with a slight delay so that the secondary controller turns−off the SR MOSFET by trigger signal prior to the primary switching. This method reduces the commutation losses and the SR MOSFET drain voltage spike, which results in improved efficiency. It is also possible to use capacitive coupling (use additional capacitor with safety insulation) between the primary and secondary to transmit the trigger signal. We do not recommend this technique as the parasitic capacitive currents between primary and secondary may affect the trigger signal and thus overall system functionality. Figure 46. Typical Application Schematic When NCP4303 is Used in CCM Flyback Converter Minimum Ton and Toff Adjustment timers avoid false triggering on the CS input after the MOSFET is turned on or off. The adjustment is based on an internal timing capacitance and external resistors connected to the GND pin – refer to Figure 47 for better understanding. The NCP4303 offers adjustable minimum ON and OFF time periods that ease the implementation of the synchronous rectification system in a power supply. These http://onsemi.com 20 NCP4303A/B Figure 47. Internal Connection of the Min_Ton Generator (the Min_Toff Works in the Same Way) Current through the Min_Ton adjust resistor can be calculated as: I R_Ton_min + V ref internal capacitor size would be too high if we would use directly IR_Ton_min current thus this current is decreased by the internal current mirror ratio. One can then calculate the minimum Ton and Toff blanking periods using below equations: (eq. 4) R Ton_min As the same current is used for the internal timing capacitor (Ct) charging, one can calculate the minimum on−time duration using this equation. T on_min + C t @ V ref I R_Ton_min + Ct + V ref V ref T on_min + 9.82 * 10 −11 * R T_on_min ) 4.66 * 10 −8 [ms] (eq. 6) T off_min + 9.56 * 10 −11 * R T_off_min ) 5.397 * 10 −8 [ms] (eq. 7) R Ton_min Note that the internal timing comparator delay affects the accuracy of Equations 6 and 7 when Ton/Toff times are selected near to their minimum possible values. Please refer to Figure 48 and 49 for measured minimum on and off time charts. (eq. 5) + C t @ R Ton_min 6 6 5 5 4 4 Toff_MIN (ms) Ton_MIN (ms) As can be seen from Equation 5, the minimum ON and OFF times are independent of the Vref or VCC level. The 3 2 1 0 3 2 1 0 10 20 30 40 50 0 60 0 10 20 30 40 50 Rmin_Ton (kW) Rmin_Toff (kW) Figure 48. Min Ton Adjust Characteristic Figure 49. Min Toff Adjust Characteristic The absolute minimum Ton duration is internally clamped to 300 ns and minimum Toff duration to 600 ns in order to prevent any potential issues with the minimum Ton and/or Toff input being shorted to GND. 60 Some applications may require adaptive minimum on and off time blanking periods. With NCP4303 it is possible to modulate blanking periods by using an external NPN transistor – refer to Figure 50. The modulation signal can be http://onsemi.com 21 NCP4303A/B derived based on the load current or feedback regulator voltage. Figure 50. Possible Connection for Min Ton and Toff Modulation In LLC applications with a very wide operating frequency range it is necessary to have very short minimum on time and off time periods in order to reach the required maximum operating frequency. However, when a LLC converter operates under low frequency, the minimum off time period may then be too short. To overcome possible issues with the LLC operating under low line and light load conditions, one can prolong the minimum off time blanking period by using resistors Rdrain1 and Rdrain2 connected from the opposite SR MOSFET drain – refer to Figure 51. Figure 51. Possible Connection for Min Toff Prolongation in LLC Applications with Wide Operating Frequency Range Note that Rdrain1 and Rdrain2 should be designed in such a way that the maximum pulse current into the Min_Toff adjust pin is below 10 mA. Voltage on the min Toff and Ton pins is clamped by internal zener protection to 10 V. http://onsemi.com 22 NCP4303A/B Power Dissipation Calculation always operates under Zero Voltage Switching (ZVS) conditions when implemented in a synchronous rectification system. The following steps show how to approximately calculate the power dissipation and DIE temperature of the NCP4303A/B controller. Note that real results can vary due to the effects of the PCB layout on the thermal resistance. It is important to consider the power dissipation in the MOSFET driver of a SR system. If no external gate resistor is used and the internal gate resistance of the MOSFET is very low, nearly all energy losses related to gate charge are dissipated in the driver. Thus it is necessary to check the SR driver power losses in the target application to avoid over temperature and to optimize efficiency. In SR systems the body diode of the SR MOSFET starts conducting before turn on because the Vth_cs_on threshold level is below 0 V. On the other hand, the SR MOSFET turn off process always starts before the drain to source voltage rises up significantly. Therefore, the MOSFET switch Step 1 – MOSFET gate to source capacitance: During ZVS operation the gate to drain capacitance does not have a Miller effect like in hard switching systems because the drain to source voltage is close to zero and its change is negligible. C iss + C gs ) C gd C rss + C gd C oss + C ds ) C gd Figure 52. Typical MOSFET Capacitances Dependency on Vds and Vgs Voltages to source voltage − in this case the NCP4303A should be used. The total driving loss can be calculated using the selected gate driver clamp voltage and the input capacitance of the MOSFET: Therefore, the input capacitance of a MOSFET operating in ZVS mode is given by the parallel combination of the gate to source and gate to drain capacitances (i.e. Ciss capacitance for given gate to source voltage). The total gate charge, Qg_total, of most MOSFETs on the market is defined for hard switching conditions. In order to accurately calculate the driving losses in a SR system, it is necessary to determine the gate charge of the MOSFET for operation specifically in a ZVS system. Some manufacturers define this parameter as Qg_ZVS. Unfortunately, most datasheets do not provide this data. If the Ciss (or Qg_ZVS) parameter is not available then it will need to be measured. Please note that the input capacitance is not linear (as shown figure 52) and it needs to be characterized for a given gate voltage clamp level. P DRV_total + V CC @ V clamp @ C g_ZVS @ f SW (eq. 8) Where: Vcc is the NCP4303x supply voltage Vclamp is the driver clamp voltage Cg_ZVS is the gate to source capacitance of the MOSFET in ZVS mode fsw is the switching frequency of the target application The total driving power loss won’t only be dissipated in the IC, but also in external resistances like the external gate resistor (if used) and the MOSFET internal gate resistance (Figure 53). Because NCP4303A/B features a clamped driver, it’s high side portion can be modeled as a regular driver switch with equivalent resistance and a series voltage source. The low side driver switch resistance does not drop immediately at turn−off, thus it is necessary to use an equivalent value (Rdrv_low_eq) for calculations. This method simplifies power losses calculations and still provides acceptable accuracy. Internal driver power dissipation can then be calculated using Equation 9: Step 2 – Gate drive losses calculation: Gate drive losses are affected by the gate driver clamp voltage. Gate driver clamp voltage selection depends on the type of MOSFET used (threshold voltage versus channel resistance). The total power losses (driving loses and conduction losses) should be considered when selecting the gate driver clamp voltage. Most of today’s MOSFETs for SR systems feature low RDS(on) for 5 V Vgs voltage and thus it is beneficial to use NCP4303B. However, there is still a big group of MOSFETs on the market that require higher gate http://onsemi.com 23 NCP4303A/B Figure 53. Equivalent Schematic of Gate Drive Circuitry P DRV_IC + ǒ Ǔ R drv_low_eq 1 @ C g_ZVS @ V clamp 2 @ f SW @ ) C g_ZVS @ V clamp @ f SW @ ǒV CC * V clampǓ 2 R drv_low_eq ) R g_ext ) R g_int ) ǒ R drv_high_eq Ǔ (eq. 9) 1 @ C g_ZVS @ V clamp 2 @ f SW @ 2 R drv_high_eq ) R g_ext ) R g_int Step 4 – IC DIE Temperature Arise Calculation: Where: Rdrv_low_eq is the NCP4303x driver low side switch equivalent resistance (1.55 W) Rdrv_high_eq is the NCP4303x driver high side switch equivalent resistance (7 W) Rg_ext is the external gate resistor (if used) Rg_int is the internal gate resistance of the MOSFET The DIE temperature can be calculated now that the total internal power losses have been determined (driver losses plus internal IC consumption losses). The SO−8 package thermal resistance is specified in the maximum ratings table for a 35 mm thin copper layer with no extra copper plates on any pin (i.e. just 0.5 mm trace to each pin with standard soldering points are used). The DIE temperature is calculated as: Step 3 – IC Consumption Calculation: In this step, power dissipation related to the internal IC consumption is calculated. This power loss is given by the ICC current and the IC supply voltage. The ICC current depends on switching frequency and also on the selected min Ton and Toff periods because there is current flowing out from the min Ton and Toff pins. The most accurate method for calculating these losses is to measure the Icc current when Cload = 0 nF and the IC is switching at the target frequency with given Min_Ton and Min_Toff adjust resistors. Refer also to Figure 54 for typical IC consumption charts when the driver is not loaded. IC consumption losses can be calculated as: P ICC + V CC @ I CC T DIE + ǒP DRV_IC ) P ICCǓ @ R qJ*A ) T A (eq. 11) Where: PDRV_IC is the IC driver internal power dissipation PIcc is the IC control internal power dissipation RqJA is the thermal resistance from junction to ambient TA is the ambient temperature (eq. 10) http://onsemi.com 24 NCP4303A/B 400 160 POWER CONSUMTION (mW) NCP4303B, VCC = 30 V 140 120 NCP4303A, VCC = 30 V 100 80 NCP4303A, VCC = 12 V 60 40 NCP4303B, VCC = 12 V 20 0 50 100 150 200 250 300 350 400 OPERATING FREQUENCY (kHz) 450 350 300 NCP4303A, VCC = 30 V 250 200 NCP4303B, VCC = 30 V NCP4303A, VCC = 12 V 150 100 NCP4303B, VCC = 12 V 50 0 50 500 100 150 200 250 300 350 400 450 OPERATING FREQUENCY (kHz) Figure 54. IC Power Consumption as a Function of Frequency for Cload = 0 nF, Rton_min = Rtoff_min = 5 kW Figure 55. IC Power Consumption as a Function of Frequency for Cload = 1 nF, Rton_min = Rtoff_min = 5 kW 800 POWER CONSUMTION (mW) POWER CONSUMTION (mW) 180 NCP4303A, VCC = 30 V 700 NCP4303B, VCC = 30 V 600 500 400 300 200 NCP4303B, VCC = 12 V 100 0 50 NCP4303A, VCC = 12 V 100 150 200 250 300 350 400 450 500 OPERATING FREQUENCY (kHz) Figure 56. IC Power Consumption as a Function of Frequency for Cload = 10 nF, Rton_min = Rtoff_min = 5 kW http://onsemi.com 25 500 NCP4303A/B PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AJ −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J SOLDERING FOOTPRINT* S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. The products described herein (NCP4303) has patents pendings. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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