Datasheet

UNISONIC TECHNOLOGIES CO., LTD
CD4541
CMOS IC
PROGRAMMABLE TIMER

DESCRIPTION
The CD4541 programmable timer comprise a 16-stage
binary counter, an integrated oscillator for use with an external
capacitor and two resistors, output control logic, and a special
power-on reset circuit. The counter divides the oscillator
frequency by any of 4 digitally controlled division ratios.

FEATURES
* Operates at 2n frequency divider or as single transition timer
* Increments on positive edge clock transitions
* Wide supply voltage range: 3.0V ~ 15V
* Built-in low power RC oscillator
* Oscillator frequency range ~ DC to 100 kHz
* External clock applied to Pin 3 can be used instead of
* oscillator
* Available division ratios 28, 210, 213, or 216
* High noise immunity: 0.45 VDD (typ)
* Master reset totally independent of automatic reset operation
* Automatic reset initializes all counters when power turns on
* Q/Q select provides output logic level flexibility
* High output drive min. one TTL load
* Maximum input leakage 1μA at 15V over full temperature
* range

ORDERING INFORMATION
Ordering Number
Lead Free
CD4541-D14-T
-

Halogen Free
CD4541L-D14-T
CD4541L-S14-R
CD4541L-P14-T
Package
Packing
DIP-14
SOP-14
TSSOP-14
Tube
Tape Reel
Tube
MARKING
DIP-14
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Copyright © 2015 Unisonic Technologies Co., Ltd
SOP-14 / TSSOP-14
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CD4541


CMOS IC
PIN CONFIGURATION
14
VDD
CTC
2
13
B
RS
3
12
A
N.C.
4
11
N.C.
AR
5
10
MODE
MR
6
9
Q/Q SELECT
VSS
7
8
Q
STATE
0
Auto Reset Operating
Timer Operational
Output Initially Low after Reset
Single Cycle Mode
5
6
9
10

1
TRUTH TABLE
PIN

RTC
1
Auto Reset Disabled
Master Reset On
Output Initially High after Reset
Recycle Mode
DIVISION RATIO TABLE
A
B
0
0
1
1
0
1
0
1
Number of Counter Stages
n
13
10
8
16
Count
2n
8192
1024
256
65536
BLOCK DIAGRAM
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CD4541

CMOS IC
ABSOLUTE MAXIMUM RATING
PARAMETER
SYMBOL
VDD
VIN
RATINGS
UNIT
-0.5 ~ +18
V
-0.5 ~ VDD+0.5
V
DIP-14
700
Power Dissipation
PD
mW
SOP-14/ TSSOP-14
500
Junction Temperature
TJ
125
°C
Operating Temperature
TOPR
-20 ~ +85
°C
Storage Temperature
TSTG
-40 ~ +150
°C
Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
Supply Voltage
Input Voltage

RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Operating Temperature

SYMBOL
VDD
VIN
TOPR
RATINGS
3 ~ 15
0 ~ VDD
-40 ~ +85
UNIT
V
V
°C
DC ELECTRICAL CHARACTERISTICS (TA=25°C, unless otherwise specified.)
PARAMETER
SYMBOL
Quiescent Device Current
IDD
Low Level Output Voltage
VOL
High Level Output Voltage
VOH
Low Level Input Voltage
VIL
High Level Input Voltage
VIH
Low Level Output Current (Note)
IOL
High Level Output Current (Note)
IOH
Input Current
IIN
TEST CONDITIONS
VDD= 5V, VIN=VDD or VSS
VDD=10V, VIN=VDD or VSS
VDD=15V, VIN=VDD or VSS
VDD=5V
VDD=10V, I IO I<1μA
VDD=15V
VDD=5V
VDD=10V, I IO I<1μA
VDD=15V
VDD=5V, VO=0.5V or 4.5V
VDD=10V, VO=1.0V or 9.0V
VDD=15V, VO=1.5V or 13.5V
VDD=5V, VO=0.5V or 4.5V
VDD=10V, VO=1.0V or 9.0V
VDD=15V, VO=1.5V or 13.5V
VDD=5V, VO=0.4V
VDD=10V, VO=0.5V
VDD=15V, VO=1.5V
VDD=5V, VO=2.5V
VDD=10V, VO=9.5V
VDD=15V, VO=13.5V
VDD=15V, VIN=0V
VDD=15V, VIN=15V
MIN
4.95
9.95
14.95
3.5
7.0
11.0
1.96
2.66
10.4
4.27
2.25
8.8
TYP
0.005
0.010
0.015
0
0
0
5
10
15
2
4
6
3
6
9
3.6
9.0
34.0
130
8.0
30.0
-10-5
10-5
MAX
20
40
80
0.05
0.05
0.05
UNIT
μA
V
V
1.5
3.0
4.0
V
V
mA
mA
-0.3
0.3
μA
Note: IOH and IOL are tested one output at a time.
UNISONIC TECHNOLOGIES CO., LTD
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
CMOS IC
AC ELECTRICAL CHARACTERISTICS (Note 1, TA=25℃, CL=50pF (refer to test circuits))
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
VDD=5V
Output Rise Time
tTLH
VDD=10V
VDD=15V
VDD=5V
Output Fall Time
tTHL
VDD=10V
VDD=15V
VDD=5V
Turn-Off, Turn-On Propagation
t
,
t
VDD=10V
PLH PHL
Delay, Clock to Q (28 Output)
VDD=15V
VDD=5V
Turn-On, Turn-Off Propagation
tPHL, tPLH
VDD=10V
16
Delay, Clock to Q (2 Output)
VDD=15V
VDD=5V
400
Clock Pulse Width
tWH(CL)
VDD=10V
200
VDD=15V
150
VDD=5V
Clock Pulse Frequency
fCL
VDD=10V
VDD=15V
VDD=5V
400
MR Pulse Width
tWH(R)
VDD=10V
200
VDD=15V
150
Average Input Capacitance
CI
Any Input
Power Dissipation Capacitance
CPD
(Note 2)
Notes: 1. AC Parameters are guaranteed by DC correlated testing.
2. CPD determines the no load AC power consumption of any CMOS device.
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TYP
50
30
25
50
30
25
1.8
0.6
0.4
3.2
1.5
1.0
200
100
70
2.5
6.0
8.5
170
75
50
5.0
100
MAX
200
100
80
200
100
80
4.0
1.5
1.0
8.0
3.0
2.0
UNIT
ns
ns
μs
μs
ns
1.0
3.0
4.0
MHz
ns
7.5
pF
pF
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CMOS IC
OPERATING CHARACTERISTICS
With Auto Reset pin set to a “0” the counter circuit is initialized by turning on power. Or with power already on, the
counter circuit is reset when the Master Reset pin is set to a “1”. Both types of reset will result in synchronously
resetting all counter stages independent of counter state.
The RC oscillator frequency is determined by the external RC network, i.e.:
and RS ~ 2 RTC where RS≧10 kΩ
The time select inputs (A and B) provide a two-bit address to output any one of four counter stages (28, 210, 213,
and 216). The 2n counts as shown in the Division Ratio Table represent the Q output of the Nth stage of the counter.
When A is “1”, 216 is selected for both states of B.
However, when B is “0”, normal counting is interrupted and the 9th counter stage receives its clock directly from
the oscillator (i.e., effectively outputting 28).
The Q/Q select output control pin provides for a choice of output level. When the counter is in a reset condition
and Q/Q select pin is set to a “0” the Q output is a “0”. Correspondingly, when Q/Q select pin is set to a “1” the Q
output is a “1”.
When the mode control pin is set to a “1”, the selected count is continually transmitted to the output. But, with
mode pin “0” and after a reset condition the RS flip-flop resets (see Logic Diagram), counting commences and after
2n-1 counts the RS flip-flop sets which causes the output to change state. Hence, after another 2n-1 counts the output
will not change. Thus, a Master Reset pulse must be applied or a change in the mode pin level is required to reset
the single cycle operation.
Oscillator Circuit Using RC Configuration
3
TO CLOCK
CIRCUIT
INTERNAL
RESET
2
RS
CTC
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1
RTC
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
CMOS IC
TEST CIRCUIT AND WAVEFORMS
Switching Time Test Circuit and Waveforms
VDD
PULSE
GENERATOR
Rs
AR
Q/Q SELECT
Q
MODE
A
B
MR
CL
VSS
tWH (CL)
Rs
20 ns
90%
50%
10%
20 ns
50%
tPLH
Q
tPHL
90%
50%
10%
tTLH
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50%
tTHL
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CMOS IC
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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