VEML6070 www.vishay.com Vishay Semiconductors UV A Light Sensor with I2C Interface FEATURES • Package type: surface mount • Dimensions (L x W x H in mm): 2.35 x 1.8 x 1.0 • Integrated modules: ultraviolet sensor (UV), and signal conditioning IC • Converts solar UV light intensity to digital data • Excellent UV sensitivity and linearity via FiltronTM technology • Excellent performance of UV radiation measurement under long time solar UV exposure • Excellent temperature compensation DESCRIPTION • High dynamic detection resolution VEML6070 is an advanced ultraviolet (UV) light sensor with I2C protocol interface and designed by the CMOS process. It is easily operated via a simple I2C command. The active acknowledge (ACK) feature with threshold windows setting allows the UV sensor to send out a UVI alert message. Under a strong solar UVI condition, the smart ACK signal can be easily implemented by the software programming. VEML6070 incorporates a photodiode, amplifiers, and analog / digital circuits into a single chip. VEML6070’s adoption of FiltronTM UV technology provides the best spectral sensitivity to cover UV spectrum sensing. It has an excellent temperature compensation and a robust refresh rate setting that does not use an external RC low pass filter. VEML6070 has linear sensitivity to solar UV light and is easily adjusted by an external resistor. Software shutdown mode is provided, which reduces power consumption to be less than 1 μA. VEML6070’s operating voltage ranges from 2.7 V to 5.5 V. • Standard I2C protocol interface • Support acknowledge feature (ACK) • Immunity on fluorescent light flicker software shutdown mode control • Package: OPLGA • Temperature compensation: -40 °C to +85 °C • Floor life: 168 h, MSL 3, according to J-STD-020 • Output type: I2C bus • Operation voltage: 2.7 V to 5.5 V • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 APPLICATIONS • Solar UV indicator • Cosmetic / outdoor sport handheld product • Consumer products PRODUCT SUMMARY PART NUMBER VEML6070 OPERATING VOLTAGE RANGE (V) I2C BUS VOLTAGE RANGE (V) PEAK SENSITIVITY (nm) RANGE OF SPECTRAL BANDWIDTH λ0.5 (nm) OUTPUT CODE 2.7 to 5.5 1.7 to 5.5 355 ± 20 16 bit, I2C Note (1) Adjustable through I2C interface ORDERING INFORMATION ORDERING CODE PACKAGING VOLUME (1) REMARKS VEML6070 Tape and reel MOQ: 2500 pcs 2.35 mm x 1.8 mm x 1.0 mm Note MOQ: minimum order quantity (1) ABSOLUTE MAXIMUM RATINGS (Tamb = 25 °C, unless otherwise specified) PARAMETER SYMBOL MIN. MAX. Supply voltage VDD 0 6.0 V Operation temperature range Tamb -40 +85 °C Rev. 1.6, 31-Jul-15 TEST CONDITION UNIT Document Number: 84277 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VEML6070 www.vishay.com Vishay Semiconductors RECOMMENDED OPERATING CONDITIONS (Tamb = 25 °C, unless otherwise specified) PARAMETER TEST CONDITION SYMBOL MIN. MAX. UNIT VDD 2.7 5.5 V Operation temperature range Tamb -40 +85 °C I2C bus operating frequency f(I2CCLK) 10 400 kHz Supply voltage PIN DESCRIPTIONS PIN ASSIGNMENT SYMBOL TYPE FUNCTION 1 GND I Power supply ground, all voltage are reference to GND 2 ACK O (open drain) Acknowledge pin 3 SDA I / O (open drain) I2C digital serial data output to the host 4 SET 5 SCL I Light reading adjustment, connect a resistor to GND I2C digital serial clock input from the host 6 VDD I Supply voltage BLOCK DIAGRAM VEML6070 GND 1 Temperature sensor 6 VDD 5 SCL 4 RSET Low pass filter ACK 2 Timing controller SDA Output buffer I2C interface UV-PD 3 Oscillator BASIC CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified) PARAMETER TEST CONDITION Supply operation voltage Supply current I2C signal input RSET = 240 kΩ Logic high (1)(2) (1)(2) Logic low SYMBOL MIN. TYP. MAX. UNIT VDD 2.7 - 5.5 V μA IDD - 100 250 VIH 1.5 - VDD VIL - - 0.8 V Peak sensitivity wavelength λp - 355 - Range of spectral sensitivity λ0.1 320 - 410 nm - 5 - μW/cm2/step UVA sensitivity RSET = 240 kΩ, IT = 1T (3) nm Maximum UVA detection power RSET = 240 kΩ, IT = 1T (3) - - 328 mW/cm2 Dark offset RSET = 240 kΩ, IT = 1T (1) 0 1 5 steps - 2 - steps - 1 15 μA Output offset Shutdown current RSET = 240 kΩ, IT = 1T (1)(4) Light condition = dark (1) IDD Notes (1) Test condition: V DD = 3.3 V, temperature: 25°C (2) Light source: solar light source (3) Test using 365 nm UVA LED (4) Ambient light intensity = 500 lx Rev. 1.6, 31-Jul-15 Document Number: 84277 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VEML6070 www.vishay.com Vishay Semiconductors I2C TIMING CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified) PARAMETER SYMBOL Clock frequency STANDARD MODE MIN. MAX. f(SMBCLK) 10 t(BUF) 4.7 t(HDSTA) Repeated start condition setup time Stop condition setup time Data hold time t(HDDAT) Data setup time t(SUDAT) t(LOW) Bus free time between start and stop condition Hold time after (repeated) start condition; after this period, the first clock is generated I2C clock (SCK) low period I2C clock (SCK) high period FAST MODE UNIT MIN. MAX. 100 10 400 kHz - 1.3 - μs 4.0 - 0.6 - μs t(SUSTA) 4.7 - 0.6 - μs t(SUSTO) 4.0 - 0.6 - μs 3450 - 900 ns 250 - 100 - ns 4.7 - 1.3 - μs t(HIGH) 4.0 - 0.6 - μs t(TIMEOUT) 25 35 - - ms Clock / data fall time t(F) - 300 - 300 ns Clock / data rise time t(R) - 1000 - 300 ns Detect clock / data low timeout t(LOW) t(R) t(F) VIH I2C Bus CLOCK (SCL) VIL t(HDSTA) t(HIGH) t(SUSTA) t(SUSTO) t(BUF) I2C Bus DATA (SDA) t(HDDAT t(SUDAT ) ) VIH Start { S Start Condition { P Stop Condition { { VIL S P Stop t(LOSEXT) SCL ACK t(LOWMEXT) SDAACK t(LOWMEXT) t(LOWMEXT) I2C Bus CLOCK (SCL) I2C Bus DATA (SDA) Fig. 1 - I2C Timing Diagram Rev. 1.6, 31-Jul-15 Document Number: 84277 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VEML6070 www.vishay.com Vishay Semiconductors PARAMETER TIMING INFORMATION I2C Bus CLOCK (SCL) I2C Bus DATA (SDA) SA7 SA6 SA5 SA4 SA3 SA1 SA2 W DA7 Start by Master DA7 DA5 DA4 DA3 DA2 DA0 DA1 ACK by VEML6070 ACK by Stop by VEML6070 Master I2C Bus Slave Address Byte Command Byte Fig. 2 - Timing for Send Byte Command Format I2C Bus CLOCK (SCL) I2C Bus DATA (SDA) SA7 SA6 SA5 SA4 SA3 SA2 SA1 R Start by Master DA7 DA6 DA5 DA4 DA3 DA2 DA0 DA1 ACK by Stop by Master Master ACK by VEML6070 I2C Bus Slave Address Byte VEML6070 Data Byte Fig. 3 - I2C Timing for Receive Byte Command Format TYPICAL PERFORMANCE CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified) Axis Title 100 10000 View Angle OPLGA package 90 1 70 0.9 1000 50 40 100 30 0.8 0.7 Normalized Output 60 1st line 2nd line 2nd line Normalized Output (%) 1.1 80 0.6 VEML6070 0.5 Ideal Cosine 0.4 0.3 20 0.2 10 0.1 10 λ - Wavelength (nm) 2nd line Fig. 4 - Normalized Spectral Response Rev. 1.6, 31-Jul-15 90 70 80 50 60 40 20 30 0 -10 -30 0 -20 600 -40 550 -50 500 -60 450 -70 400 -80 350 -90 300 10 0 View Angle Fig. 5 - Normalized Output vs. View Angle Document Number: 84277 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VEML6070 www.vishay.com Vishay Semiconductors CM 3512 Refresh Time 40 50 60 70 80 90 100 110 Temperature 1200 30 1100 1150 20 0 50 100 150 200 250 10 950 1000 1050 75 850 900 85 750 800 95 550 600 650 700 105 450 500 Time (ms) IDD (uA) 115 350 400 125 500 475 450 425 400 375 350 325 300 275 250 225 200 175 150 125 100 75 50 25 0 300 Temperature vs. IDD Rset (Kohm) Fig. 6 - IDD vs.Temperature Fig. 7 - Refresh Time APPLICATION INFORMATION Pin Connection with the Host VEML6070 is a cost effective solution for ultraviolet light sensing with I2C interface. The standard serial digital interface easily accesses “UV light intensity” digital data. The additional capacitor near the VDD pin is used for power supply noise rejection. For the I2C bus design, the pull-up voltage refers to the I/O of the baseband due to the “open drain” design. The pull-up resistors for the I2C bus design are recommended to be 2.2 kΩ. The circuit diagram as an example is shown in figure 8. 1.7 V to 5.5 V R1 R2 R3 Host Micro Controller GND (1) 2.7 V to 5.5 V R4 10R 10 μF C1 and R4 are optional for very disturbed supply C1 C2 100 nF VDD (6) VEML6070 R5 RSET (4) SDA (3) I2C Bus Data SDA SCL (5) I2C Bus Clock SCL ACK (2) GPIO (INT) 270K Fig. 8 - Hardware Pin Connection Diagram Rev. 1.6, 31-Jul-15 Document Number: 84277 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VEML6070 www.vishay.com Vishay Semiconductors Digital Interface VEML6070 contains a 8-bit command register written via the I2C bus. All operations can be controlled by the command register. The simple command structure enables users to easily program the operation setting and latch the light data from VEML6070. In figure 9, VEML6070 I2C command format description for reading and writing operation between the host and VEML6070 are shown. The white sections indicate host activity and the gray sections indicate VEML6070’s acknowledgement of the host access activity. Receive byte → read data from UVS S Slave address Rd A Light data (1 byte ) A P A Command (1 byte ) A P Send byte → write command to UVS S Slave address Wr S = start condition P = stop condition A = acknowledge Shaded area = VEML6070 acknowledge Fig. 9 - VEML6070 Command Protocol Slave Address and Function Description The VEML6070 has one slave address used for write functions (command) and two slave addresses used for read functions (UV data LSB and MSB). The 7-bit address for write functions is 38h = 0111000x resulting in a 70h = 01110000 8-bit address. The 7-bit addresses for read functions are 38h = 0111000x for the UV Data LSB and 39h = 0111001x for the UV data MSB. This results in a 71h = 01110001 and 73h = 01110011 8-bit address, respectively. The 7-bit address 39h should not be used for a write function. Command Register Format VEML6070 provides a command to set device operations and sensitivity adjustment. This command is 8-bit long and includes 4 parameter groups for programming. The command format descriptions and register setting explanations are shown in tables 1 and 2. TABLE 1 - COMMAND REGISTER BITS DESCRIPTION COMMAND FORMAT Reserved ACK ACK_THD Reserved SD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 IT Bit 2 Bit 1 Bit 0 0 0 ACK THD IT1 IT0 1 SD DESCRIPTION Reserved ACK ACK_THD Reserved Acknowledge activity setting Acknowledge threshold window setting for byte mode usage IT Integration time setting SD Shutdown mode setting Rev. 1.6, 31-Jul-15 Document Number: 84277 6 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VEML6070 www.vishay.com Vishay Semiconductors TABLE 2 - REGISTER TABLE SETTING BITS SETTING DESCRIPTION Reserved BITS SETTING Set initial value to (0 : 0) (IT1 : IT0) 0 = disable ACK (0 : 0) = ½T (0 : 1) = 1T (1 : 0) = 2T (1 : 1) = 4T (1) Reserved 1 = enable 0 = 102 steps ACK_THD DESCRIPTION Set initial value to 1 0 = disable SD 1 = 145 steps 1 = enable Note (1) Please refer to table 4, “Example of Refresh Time and R SET Value Relation” Data Access VEML6070 has 16-bit resolution to give high resolution for light intensity sensing. Examples of the application setting are shown in table 3. TABLE 3 - DATA ACCESS DESCRIPTION VEML6070 16-BIT DATA BUFFER Data bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Sequence 1 Sequence 2 Notes • Slave addresses (8 bits) for data read: 0x71 and 0x73 • Data reading sequence for the host: -Set read command to 0x73, read MSB 8 bits of 16 bits light data (sequence 1) -Set read command to 0x71, read LSB 8 bits of 16 bits light data for completing data structure (sequence 2) Initialization VEML6070 needs to be initialized while the system’s power is on. The initialization includes two major steps: (1) clear ACK state of UVS and (2) fill the initial value, 06 (HEX), into the 0x70 addresses. After the initialization is completed, VEML6070 can be programmable for operation by write command setting from the host. VEML6070 initialization is recommended to be completed within 150 ms. Acknowledge Activity VEML6070 provides a function for sending an acknowledge signal (ACK) to the host when the value of sensed UV light is over the programmed threshold (ACK_THD) value. The purpose of the ACK signal is similar to the interrupt feature which informs the host once the sensed data level goes beyond the interrupt threshold setting. VEML6070 has two ACK threshold values, 102 steps and 145 steps. There are two methods of driving acknowledge condition and read / write command to VEML6070: (1) If the host implements the INT function, it performs a modified received byte operation to disengage VEML6070’s acknowledge signal and acknowledge alert response address (ARA), 0x18 (Hex). A command format for responses to an ARA is shown in figure 10. S ARA (0x18) Rd A UVS Slave Address A P Fig. 10 - Command Format for Responds to an ARA (2) If the host does not implement this feature, it should periodically access the ARA or read ARA before setting each read / write command. The behavior of an ACK signal is similar to the INT definition in I2C specification. For the hardware circuit design, this pin connects to an INT pin or GPIO pin of the MCU. The threshold ACK_THD definition is based on the sensitivity setting of VEML6070. Rev. 1.6, 31-Jul-15 Document Number: 84277 7 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VEML6070 www.vishay.com Vishay Semiconductors The ACK or UVI interrupt function allows the UVI sensing system to perform data pooling based on the interrupt event. The system sensor manager does not need to do continual data pooling and this significantly reduced the MCU loading. The ACK signal can also be used as a trigger event for popping up a warning UVI message. Refresh Time Determination VEML6070’s refresh time can be determined by the RSET value. Cooperating with the command register setting, the designer has a flexible way of defining the timing for light data collection. The default refresh time is 1T, (IT1 : IT0) = (0 : 1). If the RSET value is changed, the default timing changes and the other parts in the register table also change by comparing itself with the default timing (refer to figure 7). Table 4 is an example of two RSET resistors that show the timing table that the system designer can use a flexible way to determine the desired refresh time. TABLE 4 - EXAMPLE OF REFRESH TIME AND RSET VALUE RELATION REGISTER (IT1 : IT0) SETTING REFRESH TIME RSET = 300 kΩ RSET = 600 kΩ (0 : 0) = ½T 62.5 ms 125 ms (0 : 1) = 1T 125 ms 250 ms (1 : 0) = 2T 250 ms 500 ms (1 : 1) = 4T 500 ms 1000 ms The designer can decide the refresh timing range requirement first, then choose an appropriate RSET value for the timing range, and then write the correct value for the system application via I2C protocol. Rev. 1.6, 31-Jul-15 Document Number: 84277 8 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VEML6070 www.vishay.com Vishay Semiconductors PACKAGE INFORMATION in millimeters TOP VIEW SIDE VIEW BOTTOM VIEW 2.35 ± 0.15 0.075 min. 0.1 0.15 min. Pin 1 Marking 6 1.80 ± 0.15 0.6 1 3 0.4 ± 0.1 0.28 4 0.45 ± 0.1 0.3 ± 0.1 1.0 ± 0.1 0.56 0.20 VEML6070 pin-out assignment 1 GND 6 VDD 2 ACK 5 SCL 3 SDA 4 SET Unit: mm Fig. 11 - VEML6070 A3OP Package Dimensions LAYOUT NOTICE 2.25 mm 0.4 mm 0.6 mm 1.0 mm 0.45 mm Fig. 12 - VEML6070 OPLGA PCB Layout Footprint Rev. 1.6, 31-Jul-15 Document Number: 84277 9 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VEML6070 www.vishay.com Vishay Semiconductors APPLICATION CIRCUIT BLOCK REFERENCE 1.7 V to 5.5 V R1 R2 R3 Host Micro Controller GND (1) 2.7 V to 5.5 V R4 C1 10R 10 μF C2 VDD (6) 100 nF C1 and R4 are optional for very disturbed supply VEML6070 SDA (3) I2C Bus Data SDA SCL (5) I2C Bus Clock SCL ACK (2) GPIO (INT) R5 RSET (4) 270K Fig. 13 - VEML6070 Application Circuit Notes • VDD range: 2.7 V to 5.5 V • The pull-up voltage for I2C bus is referring to the I/O specification of baseband RECOMMENDED STORAGE AND REBAKING CONDITIONS PARAMETER MIN. MAX. UNIT Storage temperature CONDITIONS 5 50 °C Relative humidity - 60 % Open time Rebaking process should be done when aluminized envelope reopened - - Total time From the date code on the aluminized envelope (unopened) - 6 months Tape and reel: 60 °C - 22 h Tube: 60 °C - 22 h Rebaking RECOMMENDED INFRARED REFLOW Soldering conditions are based on J-STD-020 C definition. 1. After opening the tape and reel, IR reflow process should be done 2. IR reflow profile conditions IR REFLOW PROFILE CONDITION PARAMETER CONDITIONS Peak temperature Preheat temperature range and timing Timing within 5 °C to peak temperature Timing maintained above temperature / time Timing from 25 °C to peak temperature TEMPERATURE TIME 255 °C + 0 °C / - 5 °C (max.: 260 °C) 10 s 150 °C to 200 °C 60 s to 180 s - 10 s to 30 s 217 °C 60 s to 150 s - 8 min (max.) Ramp-up rate 3 °C/s (max.) - Ramp-down rate 6 °C/s (max.) - 3. Recommend Normal Solder Reflow is 235 °C to 255 °C Rev. 1.6, 31-Jul-15 Document Number: 84277 10 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VEML6070 Temperature (°C) www.vishay.com Vishay Semiconductors Max. Temperature (260 °C + 5 °C / - 5 °C)/10 s 255 Ramp-Up Rate 3 °C/s (max.) 217 200 150 Ramp-Down Rate 6 °C/s (max.) Soldering Zone 60 s to 150 s Ramp-Up Rate 3 °C/s (max.) Pre-Heating Time t2 - t1 = 60 s to 180 s t2 t1 Time (s) Fig. 14 - VEML6070 A3OP Solder Reflow Profile Chart RECOMMENDED IRON TIP SOLDERING CONDITION AND WARNING HANDLING 1. Solder the device with the following conditions: 1.1. Soldering temperature: 400 °C (max.) 1.2. Soldering time: 3 s (max.) 2. If the temperature of the method portion rises in addition to the residual stress between the leads, the possibility that an open or short circuit occurs due to the deformation or destruction of the resin increases. 3. The following methods: VPS and wave soldering, have not been suggested for the component assembly. 4. Cleaning method conditions: 4.1. Solvent: methyl alcohol, ethyl alcohol, isopropyl alcohol 4.2. Solvent temperature < 45 °C (max.) 4.3. Time: 3 min (min.) Rev. 1.6, 31-Jul-15 Document Number: 84277 11 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VEML6070 www.vishay.com Vishay Semiconductors TAPE PACKAGING INFORMATION in millimeters PIN 1 DIMENSION OF CARRIER TAPE 4.00 ± 0.10 4.00 ± 0.10 Ф 1.50 ± 0.10 12.00 +0.30 / -0.10 5.50 ± 0.10 2.00 ± 0.10 2.03 ± 0.10 UNIT: mm 1.25 ± 0.10 R 9 Max 1.75 ± 0.10 TOP VIEW 0.28 ± 0.02 SIDE VIEW R 9 Max 2.58 ± 0.10 Fig. 15 - VEML6070 A3OP Package Carrier Tape Fig. 16 - Taping Direction Fig. 17 - Reel Dimension Rev. 1.6, 31-Jul-15 Document Number: 84277 12 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000