ICS841654I FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS841654I is an optimized PCIe and sRIO clock ICS generator and member of the HiPerClocks™ family HiPerClockS™ of high-performance clock solutions from IDT. The device uses a 25MHz parallel crystal to generate 100MHz and 125MHz clock signals, replacing solutions requiring multiple oscillator and fanout buffer solutions. The device has excellent phase jitter (< 1ps rms) suitable to clock components requiring precise and low-jitter PCIe or sRIO or both clock signals. Designed for telecom, networking and industrial applications, the ICS841654I can also drive the high-speed sRIO and PCIe SerDes clock inputs of communication processors, DSPs, switches and bridges. • Four differential HCSL clock outputs: configurable for PCIe (100MHz) and sRIO (100MHz or 125MHz) clock signals One REF_OUT LVCMOS/LVTTL clock output • Selectable crystal oscillator interface, 25MHz, 18pF parallel resonant crystal or LVCMOS/LVTTL single-ended reference clock input • Supports the following output frequencies: 100MHz or 125MHz • VCO: 500MHz • PLL bypass and output enable • RMS phase jitter at 100MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.44ps (typical) • Full 3.3V power supply mode • -40°C to 85°C ambient operating temperature • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages BLOCK DIAGRAM PIN ASSIGNMENT XTAL_IN OSC FemtoClock PLL XTAL_OUT REF_IN Pulldown 1 QA0 1 0 nQA0 0 ÷NA QA1 VCO = 500MHz nQA1 REF_SEL Pulldown M = ÷20 QB0 IREF nQB0 ÷NB QB1 BYPASS Pulldown FSEL[0:1] Pulldown nQB1 MR/nOE Pulldown REF_OUT nREF_OE Pullup IDT ™ / ICS™ HCSL CLOCK GENERATOR 1 VDD REF_OUT GND QA0 nQA0 VDDOA GND QA1 nQA1 nREF_OE BYPASS REF_IN REF_SEL VDDA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 IREF FSEL0 FSEL1 QB0 nQB0 VDDOB GND QB1 nQB1 MR/nOE VDD XTAL_IN XTAL_OUT GND ICS841654I 28-Lead TSSOP 6.1mm x 9.7mm x 0.925mm package body G Package Top View ICS841654AGI REV. A APRIL 17, 2008 ICS841654I FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number Name 1, 18 VDD Power 2 REF_OUT Output 3, 7, 15, 22 4, 5, 8, 9 6 GND QA0, nQA0, QA1, nQA1 VDDOA Power Core supply pins. Single-ended reference frequency clock output. LVCMOS/LVTTL interface levels. Power supply ground. Ouput Differential Bank A output pairs. HCSL interface levels. Power 10 nREF_OE Input Pullup 11 BYPASS Input Pulldown 12 REF_IN Input Pulldown 13 REF_SEL Input Pulldown 14 VDDA XTAL_OUT, XTAL_IN Power 19 MR/nOE Input Output supply pin for Bank A outputs. Active low REF_OUT enable/disable. See Table 3E. LVCMOS/LVTTL interface levels. Selects PLL operation/PLL bypass operation. See Table 3C. LVCMOS/LVTTL interface levels. Single-ended PLL reference clock input. LVCMOS/LVTTL interface levels. Reference select. Selects the input reference source. See Table 3B. LVCMOS/LVTTL interface levels. Analog supply pin. Parallel resonant cr ystal interface. XTAL_OUT is the output, XTAL_IN is the input. (PLL reference.) Active HIGH master reset. Active LOW output enable. When logic HIGH, the internal dividers are reset and the differential outputs are in high impedance (HiZ). When logic LOW, the internal dividers and the differential outputs are enabled. See Table 3D. LVCMOS/LVTTL interface levels. 20, 21 24, 2 5 23 nQB1, QB1 nQB0, QB0 VDDOB FSEL1, FSEL0 16, 17 26, 27 Type Input Pulldown Description Output Differential Bank B output pairs. HCSL interface levels. Power Output supply pin for Bank B outputs. Input Pulldown Output frequency select pins. LVCMOS/LVTTL interface levels. HCSL current reference external resistor output. A fixed precision resistor (RREF = 475Ω) from this pin to ground provides a reference current used 28 IREF Output for differential current-mode QA[0:1]/nQA[0:1] and QB[0:1]/nQB[0:1] clock outputs. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input PullupResistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ IDT ™ / ICS™ HCSL CLOCK GENERATOR 2 ICS841654AGI REV. A APRIL 17, 2008 ICS841654I FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR TABLE 3A. FSELX FUNCTION TABLE (fref = 25MHZ) Inputs FSEL1 FSEL0 Outputs Frequency Settings M QA0:1/nQA0:1 QB0:1/nQB0:1 0 0 20 VCO/5 (100MHz) VCO/5 (100MHz) (default) 0 1 20 VCO/5 (100MHz) VCO/4 (125MHz) 1 0 20 VCO/5 (100MHz) QB0:1 = L, nQB0:1 = H 1 1 20 VCO/4 (125MHz) VCO/4 (125MHz) TABLE 3B. REF_SEL FUNCTION TABLE TABLE 3C. BYPASS FUNCTION TABLE Input Input NOTE 1 REF_SEL Input Reference BYPASS 0 XTAL (default) 0 PLL on (default) 1 REF_IN 1 PLL bypassed (QA, QB = fref/N) PLL Configuration NOTE 1: Asynchronous function. TABLE 3D. MR/nOE FUNCTION TABLE Input MR/nOE FunctionNOTE 1 0 Outputs enabled (default) 1 Device reset, outputs disabled (High Impedance) NOTE 1: Asynchronous function. TABLE 3E. nREF_OE FUNCTION TABLE Input nREF_OE Function NOTE 1 0 REF_OUT enabled 1 REF_OUT disabled (High Impedance) (default) NOTE 1: Asynchronous function. IDT ™ / ICS™ HCSL CLOCK GENERATOR 3 ICS841654AGI REV. A APRIL 17, 2008 ICS841654I FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDOX + 0.5V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause per manent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, θJA 64.4°C/W (0 lfpm) -65°C to 150°C Storage Temperature, TSTG TABLE 4A. POWER SUPPLY CHARACTERISTICS, VDD = VDDOA = VDDOB = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage VDD – 0.20 3.3 3.465 V VDDOA, VDDOB Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current Unterminated 85 mA IDDA Analog Supply Current Unterminated 20 mA IDDOA and IDDOB Output Supply Current Unterminated, RREF = 475Ω ± 1% 5 mA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C Symbol VIH Parameter Input High Voltage VIL Input Low Voltage IIH IIL Input High Current Input Low Current Test Conditions Minimum Typical 2 Maximum VDD + 0.3 Units V 0.8 V VDD = VIN = 3.465 V 150 µA VDD = VIN = 3.465V 5 µA -0.3 REF_IN, REF_SEL, BYPASS, MR/nOE, FSEL0, FSEL1 nREF_OE REF_IN, REF_SEL, BYPASS, MR/nOE, FSEL0, FSEL1 nREF_OE VDD = 3.465V, VIN = 0V -5 µA VDD = 3.465V, VIN = 0V -150 µA Ouput High Voltage; 2.6 REF_OUT VDD = 3.465V NOTE 1 Ouput Low Voltage; VOL REF_OUT VDD = 3.465V NOTE 1 ZOUT Output Impedance REF_OUT VDD = 3.465V 20 NOTE 1: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Information Section, Output Load Test Circuit diagram. V VOH IDT ™ / ICS™ HCSL CLOCK GENERATOR 4 0.5 V Ω ICS841654AGI REV. A APRIL 17, 2008 ICS841654I FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR TABLE 5. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental Frequency 25 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Maximum Units NOTE: Characterized using an 18pF parallel resonant crystal. TABLE 6A. LVCMOS AC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency tR / t F Output Rise/Fall Time o dc Output Duty Cycle Test Conditions Minimum 20% to 80% 0.60 1.80 ns 49 51 % Maximum Units REF_OUT Typical 25 MHz TABLE 6B. HCSL AC CHARACTERISTICS, VDD = VDDOA = VDDOB = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency tjit(Ø) RMS Phase Jitter (Random); NOTE 1 tjit(cc) tsk(o) tL Test Conditions Minimum Typical VCO/5 100 MHz VCO/4 100MHz, (1.875MHz - 20MHz) 125MHz, (1.875MHz - 20MHz) 125 MHz 0.44 ps 0.44 ps Cycle-to-Cycle Jitter; NOTE 3 Output Skew; QAx/nQAx, NOTE 2, 3 QBx/nQBx PLL Lock Time VHIGH Voltage High VLOW Voltage Low VOVS Max. Voltage, Overshoot VUDS Min. Voltage, Undershoot Vrb Ringback Voltage 125MHz 650 700 -150 ps 100 ps 100 ms 950 mV 150 mV 0.3 V -0.3 VCROSS V Absolute Crossing Voltage 200 Total Variation of VCROSS over all ΔVCROSS edges QAx/nQAx, measured between tR / tF Output Rise/Fall Time 100 QBx/nQBx 0.175V to 0.525V Rise/Fall Time Variation ΔtR /ΔtF QAx/nQAx, odc Output Duty Cycle 48 QBx/nQBx NOTE: All specifications are taken at 100MHz and 125MHz. NOTE 1: Please refer to the Phase Noise Plot. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. IDT ™ / ICS™ HCSL CLOCK GENERATOR 35 5 0.2 V 550 mV 160 mV 700 ps 125 ps 52 % ICS841654AGI REV. A APRIL 17, 2008 ICS841654I FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR ➤ TYPICAL PHASE NOISE AT 100MHZ Filter 100MHz Raw Phase Noise Data ➤ ➤ NOISE POWER dBc Hz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.44ps (typical) Phase Noise Result by adding a Filter to raw data OFFSET FREQUENCY (HZ) ➤ TYPICAL PHASE NOISE AT 125MHZ Filter 125MHz Raw Phase Noise Data ➤ ➤ NOISE POWER dBc Hz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.44ps (typical) Phase Noise Result by adding an Filter to raw data OFFSET FREQUENCY (HZ) IDT ™ / ICS™ HCSL CLOCK GENERATOR 6 ICS841654AGI REV. A APRIL 17, 2008 ICS841654I FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION 3.3V±5% 3.3V±5% 3.3V±5% 3.3V±5% SCOPE VDD, VDDOA, VDDOB 50Ω VDD, VDDOA, VDDA VDDOB 50Ω 33Ω Qx VDDA 49.9Ω 2pF HCSL HCSL 50Ω 33Ω 50Ω GND GND 49.9Ω 475Ω IREF 475Ω IREF nQx 2pF 0V 0V HCSL OUTPUT LOAD AC TEST CIRCUIT HCSL OUTPUT LOAD AC TEST CIRCUIT 1.65V±5% Phase Noise Plot Noise Power 1.65V±5% SCOPE VDD VDDA Qx LVCMOS Phase Noise Mask GND f1 Offset Frequency f2 RMS Jitter = Area Under the Masked Phase Noise Plot -1.65V±5% 3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT RMS PHASE JITTER nQA[0:1], nQB[0:1] nQx QA[0:1], QB[0:1] Qx ➤ tcycle n ➤ tcycle n+1 ➤ nQy ➤ tjit(cc) = |tcycle n – tcycle n+1| 1000 Cycles Qy tsk(o) HCSL OUTPUT SKEW CYCLE-TO-CYCLE JITTER IDT ™ / ICS™ HCSL CLOCK GENERATOR 7 ICS841654AGI REV. A APRIL 17, 2008 ICS841654I FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION, CONTINUED 80% 80% V DDO 2 REF_OUT REF_OUT 20% 20% tR t PW tF t odc = PERIOD t PW x 100% t PERIOD LVCMOS OUTPUT RISE/FALL TIME LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD Clock Period (Differential) nQAx, nQBx 0.525V Positive Duty Cycle (Differential) 0.525V Negative Duty Cycle (Differential) VSW I N G QAx, QBx 0.175V 0.175V tR 0.0V tF Q - nQ DIFFERENTIAL MEASUREMENT POINTS FOR RISE/FALL TIME DIFFERENTIAL MEASUREMENT POINTS FOR DUTY CYCLE/PERIOD TSTABLE nQ VRB +150mV VRB = +100mV 0.0V VRB = -100mV -150mV VCROSS_DELTA = 140mV Q Q - nQ VRB TSTABLE SE MEASUREMENT POINTS FOR DELTA CROSS POINT IDT ™ / ICS™ HCSL CLOCK GENERATOR DIFFERENTIAL MEASUREMENT POINTS FOR RINGBACK 8 ICS841654AGI REV. A APRIL 17, 2008 ICS841654I FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION, CONTINUED VMAX = 1.15V nQ VCROSS_MAX = 550mV VCROSS_MIN = 250mV Q VMIN = -0.30V SE MEASUREMENT POINTS FOR ABSOLUTE CROSS POINT/SWING APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS841654I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, VDDOA and VDDOB should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that V DDA requires that an additional10Ω resistor along with a 10µF bypass capacitor be connected to the VDDA pin. 3.3V VDD .01μF 10Ω VDDA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: CRYSTAL INPUTS For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. OUTPUTS: HCSL OUTPUTS All unused HCSL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. REF_IN INPUT For applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the REF_IN to ground. LVCMOS OUTPUT The unused LVCMOS output can be left floating. We recommend that there is no trace attached. LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. IDT ™ / ICS™ HCSL CLOCK GENERATOR 9 ICS841654AGI REV. A APRIL 17, 2008 ICS841654I FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR CRYSTAL INPUT INTERFACE The ICS841654I has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. XTAL_OUT C1 27p X1 18pF Parallel Crystal XTAL_IN C2 27p FIGURE 2. CRYSTAL INPUt INTERFACE LVCMOS TO XTAL INTERFACE series resistance (Rs) equals the transmission line impedance. In addition, matched ter mination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. The XTAL_IN input can accept a single-ended LVCMOS signal through an AC couple capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the VDD VCC VDD VCC R1 Ro .1uf Rs Zo = 50 XTAL_IN R2 Zo = Ro + Rs XTAL_OUT FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER IDT ™ / ICS™ HCSL CLOCK GENERATOR 10 TO XTAL INPUT INTERFACE ICS841654AGI REV. A APRIL 17, 2008 ICS841654I FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR SCHEMATIC LAYOUT Figure 4 shows an example of ICS841654I application schematic. In this example, the device is operated at VCC = 3.3V. The 18pF parallel resonant 25MHz crystal is used. The C1 = 27pF and C2 = 27pF are recommended for frequency accuracy. For different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. One example of HCSL and one example of LVCMOS terminations are shown in this schematic. The decoupling capacitors should be located as close as possible to the power pin. R1 33 Zo = 50 REF_OUT LVCMOS R2 33 Zo = 50 + TL2 VDD R4 475 R5 33 Zo = 50 - VDD TL3 U1 C5 0.1u R6 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 VDDOA VCCOA C7 .1uf nREF_OE BYPASS REF_SEL VDD REF_OUT GND QA0 nQA0 VDDOA GND QA1 nQA1 nREF_OE BYPASS REF_IN REF_SEL VDDA IREF FSEL0 FSEL1 QB0 nQB0 VDDOB GND QB1 nQB1 MR/nOE VDD XTAL_IN XTAL_OUT GND 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Using for PCI Express Add-In Card FSEL0 FSEL1 VDDOB VCCOB C8 .1uf MR/nOE VDD VDD=3.3V HCSL Termination VDDOA=3.3V VDDOB=3.3V VDD VDD C6 0.1u R8 VDD R7 50 Zo = 50 + VDDA 10 ICS841654I C1 0.1u TL4 C2 10u Zo = 50 - TL5 X1 C3 27pF Logic Control Input Examples Set Logic Input to '1' VDD RU1 1K Set Logic Input to '0' VDD R12 50 25MHz 18pF C4 27pF R13 50 Using for PCI Express Point-to-Point Connection RU2 Not Install To Logic Input pins RD1 Not Install To Logic Input pins RD2 1K FIGURE 4. ICS841654I SCHEMATIC LAYOUT IDT ™ / ICS™ HCSL CLOCK GENERATOR 11 ICS841654AGI REV. A APRIL 17, 2008 ICS841654I FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS841654I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS841654I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 85mA = 294.5mW Power (outputs)MAX = 50.06mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 50.06mW = 200.24mW Total Power_MAX (3.465V, with all outputs switching) = 294.5mW + 200.24mW = 494.74mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in Section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 64.5°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.495W * 64.5°C/W = 116.9°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 7. THERMAL RESISTANCE θJA FOR 28-LEAD TSSOP, FORCED CONVECTION θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards IDT ™ / ICS™ HCSL CLOCK GENERATOR 0 1 2.5 64.5°C/W 60.4°C/W 58.5°C/W 12 ICS841654AGI REV. A APRIL 17, 2008 ICS841654I FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR 3. Calculations and Equations. The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 4. VDD IOUT = 17mA ➤ VOUT RREF = 475Ω ± 1% RL 50Ω IC FIGURE 4. HCSL DRIVER CIRCUIT AND TERMINATION HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation, use the following equations which assume a 50Ω load to ground. The highest power dissipation occurs when VDD is HIGH. Power = (VDD_HIGH – VOUT ) * IOUT, since VOUT = IOUT * RL = (VDD_HIGH – IOUT * RL) * IOUT = (3.465V – 17mA * 50Ω) * 17mA Total Power Dissipation per output pair = 50.06mW IDT ™ / ICS™ HCSL CLOCK GENERATOR 13 ICS841654AGI REV. A APRIL 17, 2008 ICS841654I FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR RECOMMENDED TERMINATION Figure 5A is the recommended termination for applications which require the receiver and driver to be on a separate PCB. All traces should be 50Ω impedance. FIGURE 5A. RECOMMENDED TERMINATION Figure 5B is the recommended termination for applications which require a point to point connection and contain the driver and receiver on the same PCB. All traces should all be 50Ω impedance. FIGURE 5B. RECOMMENDED TERMINATION IDT ™ / ICS™ HCSL CLOCK GENERATOR 14 ICS841654AGI REV. A APRIL 17, 2008 ICS841654I FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR RELIABILITY INFORMATION TABLE 8. θJAVS. AIR FLOW TABLE FOR 28 LEAD TSSOP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 64.5°C/W 60.4°C/W 58.5°C/W TRANSISTOR COUNT The transistor count for ICS841654I is: 2954 PACKAGE OUTLINE PACKAGE OUTLINE - G SUFFIX FOR AND 28 LEAD TSSOP PACKAGE DIMENSIONS TABLE 9. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N Maximum 28 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 9.60 E E1 9.80 8.10 BASIC 6.00 e 6.20 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 IDT ™ / ICS™ HCSL CLOCK GENERATOR 15 ICS841654AGI REV. A APRIL 17, 2008 ICS841654I FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR TABLE 10. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS841654AGI ICS841654AGI 28 Lead TSSOP tube -40°C to 85°C ICS841654AGIT ICS841654AGI 28 Lead TSSOP 1000 tape & reel -40°C to 85°C ICS841654AGILF ICS841654AGILF 28 Lead "Lead-Free" TSSOP tube -40°C to 85°C ICS841654AGILFT ICS841654AGILF 28 Lead "Lead-Free" TSSOP 1000 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT ™ / ICS™ HCSL CLOCK GENERATOR 16 ICS841654AGI REV. A APRIL 17, 2008 ICS841654I FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support Corporate Headquarters 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT [email protected] +480-763-2056 Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA) © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA