! " # # # " $ IBM Haifa Verification Conference 2006 Page 1 % & # '# # # ( ) ( * Page 2 + , ) - . /0 ( # 30 80 ( )" ) ( ) ( # 4 # ) ( ) ) 90 ( 1 2 ( ( ) ( 5 4" 7 ( 1 5% 2 5- # 5 # ) 6 0 0 1 7( ( ' # ' # # ) 6 # 4 " Page 3 ) 5 ' ) 0 6 1 ) : ) * ; ) ) < & %# # ) # 5" . $ : 5 * ' 5 5" 5 6 ' # ) ) ) & & " ; %5 # " ' /==> ) ; # : 5 ' # # ) 4 # ) Page 4 5; 5 ) 0 7 ' # % ) ) ) ( 2 2 )/==> + |a-b| + |a-b| + |a-b| 0 0 + |a-b| 0 '0 1 1- reset valid |a-b| 00 |a-b| |a-b| C S A C S A C S A 01 C S A 1'0 00 01 |a-b| '0 reset valid Page 5 1- + 2 ; 2% ' # : ' # ) ? ( 1 # 2 ? ; ) ) : ; ( ( )( ( # ( ( ' # 7( ' # ( Page 6 * * 7 + )( RTL RTL Schematics Schematics Compile Compile Extract Extract Modify the Schematic FEV FEV Verification Verification Passed Failed Debug Debug Page 7 ( " 4 &0 7 - # ; ' 4@ &0 # ) 7 " # ) & " # 5@ & '# ; " # " # Page 8 - " ; ) + ) % # % - : < – - % : ) # ) - 5 $ : – – – " . " – % – " + ) 5 $ - . + $ ) : ) ) # ) Page 9 )( ) ' ; ) " # # )( ( & 5 ; # * ( *A Page 10 " SALT (SM) BDD Complete system Clever (SM) BDD + SAT Complete system Verification theory Automatic Initialization methods Compositional proofs Verification methodology Debugging algorithms and tools Productivity … task manager Database Seqver 1.0 Prototype 1992 Pentium 1997 1995 Pentium-Pro Pentium-II 1st prototype (SM) BDD Based on CLS 2002 P4, Centrino 1st Retiming Ver. Ver. BDD + MC Page 11 “Butterfly” usage: Retiming RTL2RTL Today Seqver SAT + BDD Complete system ? 1 Page 12 + a0 b0 : |a-b| + a1 b1 |a-b| + a2 b2 00 |a-b| 01 + a3 b3 |a-b| '0 1- reset valid : a0 b0 |a-b| a1 b1 |a-b| 00 01 a2 b2 |a-b| a3 b3 |a-b| C S A C S A C S A C S A 1'0 + 00 01 1- '0 reset valid Page 13 + a0 b0 |a-b| + : and Large a1 b1 |a-b| + a2 b2 00 |a-b| complex data a paths b 01 + 3 |a-b| 3 '0 1- reset valid : a0 b0 |a-b| a1 b1 |a-b| 00 01 a2 b2 |a-b| a3 b3 |a-b| C S A C S A C S A C S A 1'0 + 00 01 1- '0 reset valid Page 14 + a0 b0 : |a-b| + a1 b1 |a-b| + a2 b2 00 |a-b| Different reset encoding valid : 01 + a3 b3 a0 b0 |a-b| a1 b1 |a-b| |a-b| '0 1- 00 01 a2 b2 |a-b| a3 b3 |a-b| C S A C S A C S A C S A 1'0 + 00 01 1- '0 reset valid Page 15 + a0 b0 : |a-b| + a1 b1 |a-b| + Extensive a (undocumented) b re-timing a2 b2 00 |a-b| 01 + 3 |a-b| 3 '0 1- reset valid : a0 b0 |a-b| a1 b1 |a-b| 00 01 a2 b2 |a-b| a3 b3 |a-b| C S A C S A C S A C S A 1'0 + 00 01 1- '0 reset valid Page 16 + a0 b0 : |a-b| + a1 b1 |a-b| + a2 b2 00 |a-b| a Tricky clocking b scheme 01 + 3 |a-b| 3 '0 1- reset valid : a0 b0 |a-b| a1 b1 |a-b| 00 01 a2 b2 |a-b| a3 b3 |a-b| C S A C S A C S A C S A 1'0 + 00 01 1- '0 reset valid Page 17 % < @ ) ( 7 & # * ) ( " + ) ( ( * # '# " - $ " 4/BB90 " ( ( / D / out ; D / D Page 18 & out ) ' # " % 4 /530 : /4 % ' 4 /530 ) " ' # / )-$ : / 0C 3 -$ 6 4 3 0 ) ) 4 /530 3 -/ -3 )# 4-/ -305) ' % " % " 5 )-$ # )-$ ' Page 19 ) < % ' G ) * ( # 4D0 ' < ( =E /E # ) " ) ) ) Page 20 ) ' * ) ' " F '# " ) Page 21 % # < Page 22 % - s1 s2 s3 Page 23 %# ) ) ' 7; " * RTL % -/ C-3 " # ) ( ( ' # ) ( ) C1 C1 D s1 D s2 0 " Schematics C2 C2 0 Page 24 %# ) ' ) % @H -/ -3 ' # " " # ) ( ) ( ' # ) ( RTL s1 D s2 C1 C1 Schematics 1 C2 C2 Page 25 D 1 s1 RTL Data D - s2 " D out s3 D s1 Schematics Data D s4 D s2 D out s3 D s4 D Page 26 s1 RTL Data D - s2 " D out s3 D s4 D INVERSE(s2,s4) s1 Schematics Data D s2 D out s3 D s4 D Page 27 s1 RTL Data D - s2 " D out s3 D s4 D INVERSE(s2,s4) Page 28 s1 RTL Data D - " s2 D out s3 D s4 D INVERSE(s2,s4) INVERSE(s1,s3) Page 29 s1 RTL Data D - " s2 D out s3 D s4 D INVERSE(s1,s3) Page 30 s1 RTL Data D s2 ' D out s3 D s1 Schematics Data D s4 D s2 D out s3 D s4 D No need for intermediate properties !! Page 31 ' ) - ; " @ F %# G " ; 5 # ; " # )" % 7 F# GA & ) ( 2 & " + ) # ) F( * G 2 I # " 2 )" ' ); # )A Page 32 32 '# ) ) " $ # # %" " ; ) - . " $ - ) # # # ! # ) # ' # ) A A A Page 33 & ) ( * $ . " " * : " ' $4 * " # 0 % 2 " # " '# # ) &4 5 5 Page 34 5I0 , J% Page 35