ST Sitronix ST7565S 65 x 132 Dot Matrix LCD Controller/Driver FEATURES Direct display of RAM data through the Display Data RAM. RAM capacity : 65 x 132 = 8580 bits Display duty selectable by select pin 1/65 duty : 65 common x 132 segment 1/49 duty : 49 common x 132 segment 1/33 duty : 33 common x 132 segment 1/55 duty : 55 common x 132 segment 1/53 duty : 53 common x 132 segment High-speed 8-bit MPU interface The chip can be connected directly to the both the 80x86 series MPUs and the 68000 series MPUs. Serial interfaces are supported. Abundant command functions: Display data Read/Write, Normal/Reverse display mode, display ON/OFF, page address set, display start line set, column address set, status read, display all points ON/OFF, LCD bias set, electronic volume, read/modify/write, segment driver direction selects, power saver, static indicator, common output status select, V5 voltage regulation internal resistor ratio set. Static drive circuit equipped internally for indicators. (1 system, with variable flashing speed.) Low-power liquid crystal display power supply circuit equipped internally. Booster circuit (with Boost ratios of 2X/3X/4X/5X/6X, where the step-up voltage reference power supply can be input externally). High-accuracy voltage adjustment circuit (Thermal gradient –0.05%/°C ) V5 voltage regulator resistors equipped internally, V1 to V4 voltage divider resistors equipped internally, electronic volume function equipped internally, voltage follower. CR oscillator circuit equipped internally (external clock can also be input) Extremely low power consumption. For example, operating current with built-in power supply is 60uA (VDD–VSS = VDD–VSS2 =3.0V, Booster x4, V5–VDD = –11.0V). Conditions: When displays pattern OFF and the normal mode is selected. Power supply operate on the low 1.8V Logic power supply VDD – VSS = 1.8V ~ 3.3V (+10% Range) Boost reference voltage: VDD – VSS2 = 2.4V to 3.3V Booster maximum voltage limited VDD – VOUT= 16.0V (+10% Range) Liquid crystal drive power supply: VDD – V5 = 4.0V to 13.0 V Wide range of operating temperatures: –40 to 85°C CMOS process Available Package: Bare chip and TCP These chips not designed for resistance to light or resistance to radiation. GENERAL DESCRIPTION The ST7565S is a single-chip dot matrix LCD driver that can be connected directly to a microprocessor bus. 8-bit parallel or serial display data sent from the microprocessor is stored in the internal display data RAM and the chip generates a LCD drive signal independent of the microprocessor. Because the chips in the ST7565S contain 65x132 bits of display data RAM and there is a 1-to-1 correspondence between the LCD panel pixels and the internal RAM bits, these chips enable displays with a high degree of freedom. The ST7565S chips contain 65 common output circuits and 132 segment output circuits, so that a single chip can drive a 65x132 dot display (capable of displaying 8 columnsx4 rows of a 16x16 dot kanji font). PART NO. ST7565S Ver 0.6c Moreover, the capacity of the display can be extended through the use of master/slave structures between chips. The chips are able to minimize power consumption because no external operating clock is necessary for the display data RAM read/write operation. Furthermore, because each chip is equipped internally with a low-power LCD driver power supply, resistors for LCD driver power voltage adjustment and a display clock CR oscillator circuit, the ST7565S can be used to create the lowest power display system with the fewest components for high-performance portable devices. VRS temperature gradient -0.05%/°C 1/72 VRS range -2.1V ±0.03V 2009/09/07 ST7565S ST7565S Pad Arrangement(COG) Chip Size 9,336µm x 1,000µm Bump Pitch 58µm (Min.) Bump Height 18µm(Typ) Chip Thickness 635µm PAD No Bump Size 001 ~ 012 40µm x 90µm 013 ~ 102 56µm x 60µm 103 ~ 114 40µm x 90µm 115 90µm x 25.5µm 116 ~ 128 90µm x 40µm 129 ~ 276 40µm x 90µm 277 ~ 289 90µm x 40µm 290 90µm x 25.5µm Use select pin to define display duty as following table SEL 3 , 2 , 1 DUTY Ver 0.6c BIAS 0,0,0 1/65 1/9 or 1/7 0,0,1 1/49 1/8 or 1/6 0,1,0 1/33 1/6 or 1/5 0,1,1 1/55 1/8 or 1/6 1,0,0 1/53 1/8 or 1/6 1, X , X ----- ----- 2/72 2009/09/07 ST7565S Pad Center Coordinates (1/65 Duty) Units: μm PAD No. PIN Name X Y PAD No. PIN Name X Y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 COM[53] COM[54] COM[55] COM[56] COM[57] COM[58] COM[59] COM[60] COM[61] COM[62] COM[63] COMS1 FRS FR CL /DOF VSS /CS1 CS2 VDD /RES A0 VSS /WR(R/W) /RD(E) VDD D0 D1 D2 D3 D4 D5 D6 D7 VDD VDD VDD VSS VSS VSS2 VSS2 VOUT VOUT CAP5CAP5CAP1+ CAP1+ 4241 4183 4125 4067 4009 3951 3893 3835 3777 3719 3661 3603 3443 3369 3295 3221 3147 3073 2999 2925 2851 2777 2703 2629 2555 2481 2407 2333 2259 2185 2111 2037 1963 1889 1815 1741 1667 1593 1519 1445 1371 1297 1223 1149 1075 1001 927 374 374 374 374 374 374 374 374 374 374 374 374 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 CAP3CAP3CAP1+ CAP1+ CAP1CAP1CAP2CAP2CAP2+ CAP2+ CAP4CAP4VSS VSS VRS VRS VDD VDD V1 V1 V2 V2 V3 V3 V4 V4 V5 V5 VR VR VDD VDD TEST0 TEST1 TEST2 TEST3 TEST4 TEST5 VDD M/S CLS VSS C86 P/S VDD /HPM VSS 853 779 705 631 557 483 409 335 261 187 113 39 -35 -109 -183 -257 -331 -405 -479 -553 -627 -701 -775 -849 -923 -997 -1071 -1145 -1219 -1293 -1367 -1441 -1515 -1589 -1663 -1737 -1811 -1885 -1959 -2033 -2107 -2181 -2255 -2329 -2403 -2477 -2551 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 Ver 0.6c 3/72 2009/09/07 ST7565S PAD No. 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 Ver 0.6c PIN Name X Y IRS VDD SEL1 VSS SEL2 VDD SEL3 VSS COM[31] COM[30] COM[29] COM[28] COM[27] COM[26] COM[25] COM[24] COM[23] COM[22] COM[21] COM[20] (NC) COM[19] COM[18] COM[17] COM[16] COM[15] COM[14] COM[13] COM[12] COM[11] COM[10] COM[9] COM[8] COM[7] COM[6] COM[5] COM[4] COM[3] COM[2] COM[1] COM[0] COMS2 SEG[0] SEG[1] SEG[2] SEG[3] SEG[4] SEG[5] SEG[6] SEG[7] SEG[8] SEG[9] -2625 -2699 -2773 -2847 -2921 -2995 -3069 -3143 -3606 -3664 -3722 -3780 -3838 -3896 -3954 -4012 -4070 -4128 -4186 -4244 -4542 -4542 -4542 -4542 -4542 -4542 -4542 -4542 -4542 -4542 -4542 -4542 -4542 -4542 -4267 -4209 -4151 -4093 -4035 -3977 -3919 -3861 -3803 -3745 -3687 -3629 -3571 -3513 -3455 -3397 -3339 -3281 389 389 389 389 389 389 389 389 374 374 374 374 374 374 374 374 374 374 374 374 404 351 293 235 177 119 61 3 -55 -113 -171 -229 -287 -345 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 PAD No. 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 4/72 PIN Name X Y SEG[10] SEG[11] SEG[12] SEG[13] SEG[14] SEG[15] SEG[16] SEG[17] SEG[18] SEG[19] SEG[20] SEG[21] SEG[22] SEG[23] SEG[24] SEG[25] SEG[26] SEG[27] SEG[28] SEG[29] SEG[30] SEG[31] SEG[32] SEG[33] SEG[34] SEG[35] SEG[36] SEG[37] SEG[38] SEG[39] SEG[40] SEG[41] SEG[42] SEG[43] SEG[44] SEG[45] SEG[46] SEG[47] SEG[48] SEG[49] SEG[50] SEG[51] SEG[52] SEG[53] SEG[54] SEG[55] SEG[56] SEG[57] SEG[58] SEG[59] SEG[60] SEG[61] -3223 -3165 -3107 -3049 -2991 -2933 -2875 -2817 -2759 -2701 -2643 -2585 -2527 -2469 -2411 -2353 -2295 -2237 -2179 -2121 -2063 -2005 -1947 -1889 -1831 -1773 -1715 -1657 -1599 -1541 -1483 -1425 -1367 -1309 -1251 -1193 -1135 -1077 -1019 -961 -903 -845 -787 -729 -671 -613 -555 -497 -439 -381 -323 -265 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 2009/09/07 ST7565S PAD No. 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 Ver 0.6c PIN Name X Y SEG[62] SEG[63] SEG[64] SEG[65] SEG[66] SEG[67] SEG[68] SEG[69] SEG[70] SEG[71] SEG[72] SEG[73] SEG[74] SEG[75] SEG[76] SEG[77] SEG[78] SEG[79] SEG[80] SEG[81] SEG[82] SEG[83] SEG[84] SEG[85] SEG[86] SEG[87] SEG[88] SEG[89] SEG[90] SEG[91] SEG[92] SEG[93] SEG[94] SEG[95] SEG[96] SEG[97] SEG[98] SEG[99] SEG[100] SEG[101] SEG[102] SEG[103] SEG[104] SEG[105] SEG[106] SEG[107] SEG[108] -207 -149 -91 -33 25 83 141 199 257 315 373 431 489 547 605 663 721 779 837 895 953 1011 1069 1127 1185 1243 1301 1359 1417 1475 1533 1591 1649 1707 1765 1823 1881 1939 1997 2055 2113 2171 2229 2287 2345 2403 2461 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 PAD No. 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 5/72 PIN Name X Y SEG[109] SEG[110] SEG[111] SEG[112] SEG[113] SEG[114] SEG[115] SEG[116] SEG[117] SEG[118] SEG[119] SEG[120] SEG[121] SEG[122] SEG[123] SEG[124] SEG[125] SEG[126] SEG[127] SEG[128] SEG[129] SEG[130] SEG[131] COM[32] COM[33] COM[34] COM[35] COM[36] COM[37] COM[38] COM[39] COM[40] COM[41] COM[42] COM[43] COM[44] COM[45] COM[46] COM[47] COM[48] COM[49] COM[50] COM[51] COM[52] (NC) 2519 2577 2635 2693 2751 2809 2867 2925 2983 3041 3099 3157 3215 3273 3331 3389 3447 3505 3563 3621 3679 3737 3795 3853 3911 3969 4027 4085 4143 4201 4259 4542 4542 4542 4542 4542 4542 4542 4542 4542 4542 4542 4542 4542 4542 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -345 -287 -229 -171 -113 -55 3 61 119 177 235 293 351 404 2009/09/07 ST7565S Pad Center Coordinates (1/49 Duty) PAD No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Ver 0.6c PIN Name X Y COM[37] COM[38] COM[39] COM[40] COM[41] COM[42] COM[43] COM[44] COM[45] COM[46] COM[47] COMS1 FRS FR CL /DOF VSS /CS1 CS2 VDD /RES A0 VSS /WR(R/W) /RD(E) VDD D0 D1 D2 D3 D4 D5 D6 D7 VDD VDD VDD VSS VSS VSS2 VSS2 VOUT VOUT CAP5CAP5CAP1+ CAP1+ 4241 4183 4125 4067 4009 3951 3893 3835 3777 3719 3661 3603 3443 3369 3295 3221 3147 3073 2999 2925 2851 2777 2703 2629 2555 2481 2407 2333 2259 2185 2111 2037 1963 1889 1815 1741 1667 1593 1519 1445 1371 1297 1223 1149 1075 1001 927 374 374 374 374 374 374 374 374 374 374 374 374 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 PAD No. 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 6/72 Units: μm PIN Name X Y CAP3CAP3CAP1+ CAP1+ CAP1CAP1CAP2CAP2CAP2+ CAP2+ CAP4CAP4VSS VSS VRS VRS VDD VDD V1 V1 V2 V2 V3 V3 V4 V4 V5 V5 VR VR VDD VDD TEST0 TEST1 TEST2 TEST3 TEST4 TEST5 VDD M/S CLS VSS C86 P/S VDD /HPM VSS 853 779 705 631 557 483 409 335 261 187 113 39 -35 -109 -183 -257 -331 -405 -479 -553 -627 -701 -775 -849 -923 -997 -1071 -1145 -1219 -1293 -1367 -1441 -1515 -1589 -1663 -1737 -1811 -1885 -1959 -2033 -2107 -2181 -2255 -2329 -2403 -2477 -2551 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 2009/09/07 ST7565S PAD No. 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 Ver 0.6c PIN Name X Y IRS VDD SEL1 VSS SEL2 VDD SEL3 VSS Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve COM[23] COM[22] COM[21] COM[20] (NC) COM[19] COM[18] COM[17] COM[16] COM[15] COM[14] COM[13] COM[12] COM[11] COM[10] COM[9] COM[8] COM[7] COM[6] COM[5] COM[4] COM[3] COM[2] COM[1] COM[0] COMS2 SEG[0] SEG[1] SEG[2] SEG[3] SEG[4] SEG[5] SEG[6] SEG[7] SEG[8] SEG[9] -2625 -2699 -2773 -2847 -2921 -2995 -3069 -3143 -3606 -3664 -3722 -3780 -3838 -3896 -3954 -4012 -4070 -4128 -4186 -4244 -4542 -4542 -4542 -4542 -4542 -4542 -4542 -4542 -4542 -4542 -4542 -4542 -4542 -4542 -4267 -4209 -4151 -4093 -4035 -3977 -3919 -3861 -3803 -3745 -3687 -3629 -3571 -3513 -3455 -3397 -3339 -3281 389 389 389 389 389 389 389 389 374 374 374 374 374 374 374 374 374 374 374 374 404 351 293 235 177 119 61 3 -55 -113 -171 -229 -287 -345 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 PAD No. 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 7/72 PIN Name X Y SEG[10] SEG[11] SEG[12] SEG[13] SEG[14] SEG[15] SEG[16] SEG[17] SEG[18] SEG[19] SEG[20] SEG[21] SEG[22] SEG[23] SEG[24] SEG[25] SEG[26] SEG[27] SEG[28] SEG[29] SEG[30] SEG[31] SEG[32] SEG[33] SEG[34] SEG[35] SEG[36] SEG[37] SEG[38] SEG[39] SEG[40] SEG[41] SEG[42] SEG[43] SEG[44] SEG[45] SEG[46] SEG[47] SEG[48] SEG[49] SEG[50] SEG[51] SEG[52] SEG[53] SEG[54] SEG[55] SEG[56] SEG[57] SEG[58] SEG[59] SEG[60] SEG[61] -3223 -3165 -3107 -3049 -2991 -2933 -2875 -2817 -2759 -2701 -2643 -2585 -2527 -2469 -2411 -2353 -2295 -2237 -2179 -2121 -2063 -2005 -1947 -1889 -1831 -1773 -1715 -1657 -1599 -1541 -1483 -1425 -1367 -1309 -1251 -1193 -1135 -1077 -1019 -961 -903 -845 -787 -729 -671 -613 -555 -497 -439 -381 -323 -265 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 2009/09/07 ST7565S PAD No. 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 Ver 0.6c PIN Name X Y SEG[62] SEG[63] SEG[64] SEG[65] SEG[66] SEG[67] SEG[68] SEG[69] SEG[70] SEG[71] SEG[72] SEG[73] SEG[74] SEG[75] SEG[76] SEG[77] SEG[78] SEG[79] SEG[80] SEG[81] SEG[82] SEG[83] SEG[84] SEG[85] SEG[86] SEG[87] SEG[88] SEG[89] SEG[90] SEG[91] SEG[92] SEG[93] SEG[94] SEG[95] SEG[96] SEG[97] SEG[98] SEG[99] SEG[100] SEG[101] SEG[102] SEG[103] SEG[104] SEG[105] SEG[106] SEG[107] SEG[108] -207 -149 -91 -33 25 83 141 199 257 315 373 431 489 547 605 663 721 779 837 895 953 1011 1069 1127 1185 1243 1301 1359 1417 1475 1533 1591 1649 1707 1765 1823 1881 1939 1997 2055 2113 2171 2229 2287 2345 2403 2461 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 PAD No. 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 8/72 PIN Name X Y SEG[109] SEG[110] SEG[111] SEG[112] SEG[113] SEG[114] SEG[115] SEG[116] SEG[117] SEG[118] SEG[119] SEG[120] SEG[121] SEG[122] SEG[123] SEG[124] SEG[125] SEG[126] SEG[127] SEG[128] SEG[129] SEG[130] SEG[131] Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve COM[24] COM[25] COM[26] COM[27] COM[28] COM[29] COM[30] COM[31] COM[32] COM[33] COM[34] COM[35] COM[36] (NC) 2519 2577 2635 2693 2751 2809 2867 2925 2983 3041 3099 3157 3215 3273 3331 3389 3447 3505 3563 3621 3679 3737 3795 3853 3911 3969 4027 4085 4143 4201 4259 4542 4542 4542 4542 4542 4542 4542 4542 4542 4542 4542 4542 4542 4542 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -345 -287 -229 -171 -113 -55 3 61 119 177 235 293 351 404 2009/09/07 ST7565S Pad Center Coordinates (1/33 Duty) PAD No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Ver 0.6c PIN Name X Y COM[21] COM[22] COM[23] COM[24] COM[25] COM[26] COM[27] COM[28] COM[29] COM[30] COM[31] COMS1 FRS FR CL /DOF VSS /CS1 CS2 VDD /RES A0 VSS /WR(R/W) /RD(E) VDD D0 D1 D2 D3 D4 D5 D6 D7 VDD VDD VDD VSS VSS VSS2 VSS2 VOUT VOUT CAP5CAP5CAP1+ CAP1+ 4241 4183 4125 4067 4009 3951 3893 3835 3777 3719 3661 3603 3443 3369 3295 3221 3147 3073 2999 2925 2851 2777 2703 2629 2555 2481 2407 2333 2259 2185 2111 2037 1963 1889 1815 1741 1667 1593 1519 1445 1371 1297 1223 1149 1075 1001 927 374 374 374 374 374 374 374 374 374 374 374 374 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 PAD No. 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 9/72 Units: μm PIN Name X Y CAP3CAP3CAP1+ CAP1+ CAP1CAP1CAP2CAP2CAP2+ CAP2+ CAP4CAP4VSS VSS VRS VRS VDD VDD V1 V1 V2 V2 V3 V3 V4 V4 V5 V5 VR VR VDD VDD TEST0 TEST1 TEST2 TEST3 TEST4 TEST5 VDD M/S CLS VSS C86 P/S VDD /HPM VSS 853 779 705 631 557 483 409 335 261 187 113 39 -35 -109 -183 -257 -331 -405 -479 -553 -627 -701 -775 -849 -923 -997 -1071 -1145 -1219 -1293 -1367 -1441 -1515 -1589 -1663 -1737 -1811 -1885 -1959 -2033 -2107 -2181 -2255 -2329 -2403 -2477 -2551 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 2009/09/07 ST7565S PAD No. 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 Ver 0.6c PIN Name X Y IRS VDD SEL1 VSS SEL2 VDD SEL3 VSS Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve (NC) Reserve Reserve Reserve Reserve COM[15] COM[14] COM[13] COM[12] COM[11] COM[10] COM[9] COM[8] COM[7] COM[6] COM[5] COM[4] COM[3] COM[2] COM[1] COM[0] COMS2 SEG[0] SEG[1] SEG[2] SEG[3] SEG[4] SEG[5] SEG[6] SEG[7] SEG[8] SEG[9] -2625 -2699 -2773 -2847 -2921 -2995 -3069 -3143 -3606 -3664 -3722 -3780 -3838 -3896 -3954 -4012 -4070 -4128 -4186 -4244 -4542 -4542 -4542 -4542 -4542 -4542 -4542 -4542 -4542 -4542 -4542 -4542 -4542 -4542 -4267 -4209 -4151 -4093 -4035 -3977 -3919 -3861 -3803 -3745 -3687 -3629 -3571 -3513 -3455 -3397 -3339 -3281 389 389 389 389 389 389 389 389 374 374 374 374 374 374 374 374 374 374 374 374 404 351 293 235 177 119 61 3 -55 -113 -171 -229 -287 -345 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 PAD No. 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 10/72 PIN Name X Y SEG[10] SEG[11] SEG[12] SEG[13] SEG[14] SEG[15] SEG[16] SEG[17] SEG[18] SEG[19] SEG[20] SEG[21] SEG[22] SEG[23] SEG[24] SEG[25] SEG[26] SEG[27] SEG[28] SEG[29] SEG[30] SEG[31] SEG[32] SEG[33] SEG[34] SEG[35] SEG[36] SEG[37] SEG[38] SEG[39] SEG[40] SEG[41] SEG[42] SEG[43] SEG[44] SEG[45] SEG[46] SEG[47] SEG[48] SEG[49] SEG[50] SEG[51] SEG[52] SEG[53] SEG[54] SEG[55] SEG[56] SEG[57] SEG[58] SEG[59] SEG[60] SEG[61] -3223 -3165 -3107 -3049 -2991 -2933 -2875 -2817 -2759 -2701 -2643 -2585 -2527 -2469 -2411 -2353 -2295 -2237 -2179 -2121 -2063 -2005 -1947 -1889 -1831 -1773 -1715 -1657 -1599 -1541 -1483 -1425 -1367 -1309 -1251 -1193 -1135 -1077 -1019 -961 -903 -845 -787 -729 -671 -613 -555 -497 -439 -381 -323 -265 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 2009/09/07 ST7565S PAD No. 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 Ver 0.6c PIN Name X Y SEG[62] SEG[63] SEG[64] SEG[65] SEG[66] SEG[67] SEG[68] SEG[69] SEG[70] SEG[71] SEG[72] SEG[73] SEG[74] SEG[75] SEG[76] SEG[77] SEG[78] SEG[79] SEG[80] SEG[81] SEG[82] SEG[83] SEG[84] SEG[85] SEG[86] SEG[87] SEG[88] SEG[89] SEG[90] SEG[91] SEG[92] SEG[93] SEG[94] SEG[95] SEG[96] SEG[97] SEG[98] SEG[99] SEG[100] SEG[101] SEG[102] SEG[103] SEG[104] SEG[105] SEG[106] SEG[107] SEG[108] -207 -149 -91 -33 25 83 141 199 257 315 373 431 489 547 605 663 721 779 837 895 953 1011 1069 1127 1185 1243 1301 1359 1417 1475 1533 1591 1649 1707 1765 1823 1881 1939 1997 2055 2113 2171 2229 2287 2345 2403 2461 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 PAD No. 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 11/72 PIN Name X Y SEG[109] SEG[110] SEG[111] SEG[112] SEG[113] SEG[114] SEG[115] SEG[116] SEG[117] SEG[118] SEG[119] SEG[120] SEG[121] SEG[122] SEG[123] SEG[124] SEG[125] SEG[126] SEG[127] SEG[128] SEG[129] SEG[130] SEG[131] Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve COM[16] COM[17] COM[18] COM[19] COM[20] (NC) 2519 2577 2635 2693 2751 2809 2867 2925 2983 3041 3099 3157 3215 3273 3331 3389 3447 3505 3563 3621 3679 3737 3795 3853 3911 3969 4027 4085 4143 4201 4259 4542 4542 4542 4542 4542 4542 4542 4542 4542 4542 4542 4542 4542 4542 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -345 -287 -229 -171 -113 -55 3 61 119 177 235 293 351 404 2009/09/07 ST7565S Pad Center Coordinates (1/55 Duty) PAD No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Ver 0.6c PIN Name X Y COM[43] COM[44] COM[45] COM[46] COM[47] COM[48] COM[49] COM[50] COM[51] COM[52] COM[53] COMS1 FRS FR CL /DOF VSS /CS1 CS2 VDD /RES A0 VSS /WR(R/W) /RD(E) VDD D0 D1 D2 D3 D4 D5 D6 D7 VDD VDD VDD VSS VSS VSS2 VSS2 VOUT VOUT CAP5CAP5CAP1+ CAP1+ 4241 4183 4125 4067 4009 3951 3893 3835 3777 3719 3661 3603 3443 3369 3295 3221 3147 3073 2999 2925 2851 2777 2703 2629 2555 2481 2407 2333 2259 2185 2111 2037 1963 1889 1815 1741 1667 1593 1519 1445 1371 1297 1223 1149 1075 1001 927 374 374 374 374 374 374 374 374 374 374 374 374 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 PAD No. 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 12/72 Units: μm PIN Name X Y CAP3CAP3CAP1+ CAP1+ CAP1CAP1CAP2CAP2CAP2+ CAP2+ CAP4CAP4VSS VSS VRS VRS VDD VDD V1 V1 V2 V2 V3 V3 V4 V4 V5 V5 VR VR VDD VDD TEST0 TEST1 TEST2 TEST3 TEST4 TEST5 VDD M/S CLS VSS C86 P/S VDD /HPM VSS 853 779 705 631 557 483 409 335 261 187 113 39 -35 -109 -183 -257 -331 -405 -479 -553 -627 -701 -775 -849 -923 -997 -1071 -1145 -1219 -1293 -1367 -1441 -1515 -1589 -1663 -1737 -1811 -1885 -1959 -2033 -2107 -2181 -2255 -2329 -2403 -2477 -2551 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 2009/09/07 ST7565S PAD No. 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 Ver 0.6c PIN Name X Y IRS VDD SEL1 VSS SEL2 VDD SEL3 VSS Reserve Reserve Reserve Reserve Reserve COM[26] COM[25] COM[24] COM[23] COM[22] COM[21] COM[20] (NC) COM[19] COM[18] COM[17] COM[16] COM[15] COM[14] COM[13] COM[12] COM[11] COM[10] COM[9] COM[8] COM[7] COM[6] COM[5] COM[4] COM[3] COM[2] COM[1] COM[0] COMS2 SEG[0] SEG[1] SEG[2] SEG[3] SEG[4] SEG[5] SEG[6] SEG[7] SEG[8] SEG[9] -2625 -2699 -2773 -2847 -2921 -2995 -3069 -3143 -3606 -3664 -3722 -3780 -3838 -3896 -3954 -4012 -4070 -4128 -4186 -4244 -4542 -4542 -4542 -4542 -4542 -4542 -4542 -4542 -4542 -4542 -4542 -4542 -4542 -4542 -4267 -4209 -4151 -4093 -4035 -3977 -3919 -3861 -3803 -3745 -3687 -3629 -3571 -3513 -3455 -3397 -3339 -3281 389 389 389 389 389 389 389 389 374 374 374 374 374 374 374 374 374 374 374 374 404 351 293 235 177 119 61 3 -55 -113 -171 -229 -287 -345 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 PAD No. 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 13/72 PIN Name X Y SEG[10] SEG[11] SEG[12] SEG[13] SEG[14] SEG[15] SEG[16] SEG[17] SEG[18] SEG[19] SEG[20] SEG[21] SEG[22] SEG[23] SEG[24] SEG[25] SEG[26] SEG[27] SEG[28] SEG[29] SEG[30] SEG[31] SEG[32] SEG[33] SEG[34] SEG[35] SEG[36] SEG[37] SEG[38] SEG[39] SEG[40] SEG[41] SEG[42] SEG[43] SEG[44] SEG[45] SEG[46] SEG[47] SEG[48] SEG[49] SEG[50] SEG[51] SEG[52] SEG[53] SEG[54] SEG[55] SEG[56] SEG[57] SEG[58] SEG[59] SEG[60] SEG[61] -3223 -3165 -3107 -3049 -2991 -2933 -2875 -2817 -2759 -2701 -2643 -2585 -2527 -2469 -2411 -2353 -2295 -2237 -2179 -2121 -2063 -2005 -1947 -1889 -1831 -1773 -1715 -1657 -1599 -1541 -1483 -1425 -1367 -1309 -1251 -1193 -1135 -1077 -1019 -961 -903 -845 -787 -729 -671 -613 -555 -497 -439 -381 -323 -265 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 2009/09/07 ST7565S PAD No. 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 Ver 0.6c PIN Name X Y SEG[62] SEG[63] SEG[64] SEG[65] SEG[66] SEG[67] SEG[68] SEG[69] SEG[70] SEG[71] SEG[72] SEG[73] SEG[74] SEG[75] SEG[76] SEG[77] SEG[78] SEG[79] SEG[80] SEG[81] SEG[82] SEG[83] SEG[84] SEG[85] SEG[86] SEG[87] SEG[88] SEG[89] SEG[90] SEG[91] SEG[92] SEG[93] SEG[94] SEG[95] SEG[96] SEG[97] SEG[98] SEG[99] SEG[100] SEG[101] SEG[102] SEG[103] SEG[104] SEG[105] SEG[106] SEG[107] SEG[108] -207 -149 -91 -33 25 83 141 199 257 315 373 431 489 547 605 663 721 779 837 895 953 1011 1069 1127 1185 1243 1301 1359 1417 1475 1533 1591 1649 1707 1765 1823 1881 1939 1997 2055 2113 2171 2229 2287 2345 2403 2461 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 PAD No. 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 14/72 PIN Name X Y SEG[109] SEG[110] SEG[111] SEG[112] SEG[113] SEG[114] SEG[115] SEG[116] SEG[117] SEG[118] SEG[119] SEG[120] SEG[121] SEG[122] SEG[123] SEG[124] SEG[125] SEG[126] SEG[127] SEG[128] SEG[129] SEG[130] SEG[131] Reserve Reserve Reserve Reserve Reserve COM[27] COM[28] COM[29] COM[30] COM[31] COM[32] COM[33] COM[34] COM[35] COM[36] COM[37] COM[38] COM[39] COM[40] COM[41] COM[42] (NC) 2519 2577 2635 2693 2751 2809 2867 2925 2983 3041 3099 3157 3215 3273 3331 3389 3447 3505 3563 3621 3679 3737 3795 3853 3911 3969 4027 4085 4143 4201 4259 4542 4542 4542 4542 4542 4542 4542 4542 4542 4542 4542 4542 4542 4542 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -345 -287 -229 -171 -113 -55 3 61 119 177 235 293 351 404 2009/09/07 ST7565S Pad Center Coordinates (1/53 Duty) PAD No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Ver 0.6c PIN Name X Y COM[41] COM[42] COM[43] COM[44] COM[45] COM[46] COM[47] COM[48] COM[49] COM[50] COM[51] COMS1 FRS FR CL /DOF VSS /CS1 CS2 VDD /RES A0 VSS /WR(R/W) /RD(E) VDD D0 D1 D2 D3 D4 D5 D6 D7 VDD VDD VDD VSS VSS VSS2 VSS2 VOUT VOUT CAP5CAP5CAP1+ CAP1+ 4241 4183 4125 4067 4009 3951 3893 3835 3777 3719 3661 3603 3443 3369 3295 3221 3147 3073 2999 2925 2851 2777 2703 2629 2555 2481 2407 2333 2259 2185 2111 2037 1963 1889 1815 1741 1667 1593 1519 1445 1371 1297 1223 1149 1075 1001 927 374 374 374 374 374 374 374 374 374 374 374 374 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 PAD No. 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 15/72 Units: μm PIN Name X Y CAP3CAP3CAP1+ CAP1+ CAP1CAP1CAP2CAP2CAP2+ CAP2+ CAP4CAP4VSS VSS VRS VRS VDD VDD V1 V1 V2 V2 V3 V3 V4 V4 V5 V5 VR VR VDD VDD TEST0 TEST1 TEST2 TEST3 TEST4 TEST5 VDD M/S CLS VSS C86 P/S VDD /HPM VSS 853 779 705 631 557 483 409 335 261 187 113 39 -35 -109 -183 -257 -331 -405 -479 -553 -627 -701 -775 -849 -923 -997 -1071 -1145 -1219 -1293 -1367 -1441 -1515 -1589 -1663 -1737 -1811 -1885 -1959 -2033 -2107 -2181 -2255 -2329 -2403 -2477 -2551 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 389 2009/09/07 ST7565S PAD No. 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 Ver 0.6c PIN Name X Y IRS VDD SEL1 VSS SEL2 VDD SEL3 VSS Reserve Reserve Reserve Reserve Reserve Reserve COM[25] COM[24] COM[23] COM[22] COM[21] COM[20] (NC) COM[19] COM[18] COM[17] COM[16] COM[15] COM[14] COM[13] COM[12] COM[11] COM[10] COM[9] COM[8] COM[7] COM[6] COM[5] COM[4] COM[3] COM[2] COM[1] COM[0] COMS2 SEG[0] SEG[1] SEG[2] SEG[3] SEG[4] SEG[5] SEG[6] SEG[7] SEG[8] SEG[9] -2625 -2699 -2773 -2847 -2921 -2995 -3069 -3143 -3606 -3664 -3722 -3780 -3838 -3896 -3954 -4012 -4070 -4128 -4186 -4244 -4542 -4542 -4542 -4542 -4542 -4542 -4542 -4542 -4542 -4542 -4542 -4542 -4542 -4542 -4267 -4209 -4151 -4093 -4035 -3977 -3919 -3861 -3803 -3745 -3687 -3629 -3571 -3513 -3455 -3397 -3339 -3281 389 389 389 389 389 389 389 389 374 374 374 374 374 374 374 374 374 374 374 374 404 351 293 235 177 119 61 3 -55 -113 -171 -229 -287 -345 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 PAD No. 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 16/72 PIN Name X Y SEG[10] SEG[11] SEG[12] SEG[13] SEG[14] SEG[15] SEG[16] SEG[17] SEG[18] SEG[19] SEG[20] SEG[21] SEG[22] SEG[23] SEG[24] SEG[25] SEG[26] SEG[27] SEG[28] SEG[29] SEG[30] SEG[31] SEG[32] SEG[33] SEG[34] SEG[35] SEG[36] SEG[37] SEG[38] SEG[39] SEG[40] SEG[41] SEG[42] SEG[43] SEG[44] SEG[45] SEG[46] SEG[47] SEG[48] SEG[49] SEG[50] SEG[51] SEG[52] SEG[53] SEG[54] SEG[55] SEG[56] SEG[57] SEG[58] SEG[59] SEG[60] SEG[61] -3223 -3165 -3107 -3049 -2991 -2933 -2875 -2817 -2759 -2701 -2643 -2585 -2527 -2469 -2411 -2353 -2295 -2237 -2179 -2121 -2063 -2005 -1947 -1889 -1831 -1773 -1715 -1657 -1599 -1541 -1483 -1425 -1367 -1309 -1251 -1193 -1135 -1077 -1019 -961 -903 -845 -787 -729 -671 -613 -555 -497 -439 -381 -323 -265 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 2009/09/07 ST7565S PAD No. 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 Ver 0.6c PIN Name X Y SEG[62] SEG[63] SEG[64] SEG[65] SEG[66] SEG[67] SEG[68] SEG[69] SEG[70] SEG[71] SEG[72] SEG[73] SEG[74] SEG[75] SEG[76] SEG[77] SEG[78] SEG[79] SEG[80] SEG[81] SEG[82] SEG[83] SEG[84] SEG[85] SEG[86] SEG[87] SEG[88] SEG[89] SEG[90] SEG[91] SEG[92] SEG[93] SEG[94] SEG[95] SEG[96] SEG[97] SEG[98] SEG[99] SEG[100] SEG[101] SEG[102] SEG[103] SEG[104] SEG[105] SEG[106] SEG[107] SEG[108] -207 -149 -91 -33 25 83 141 199 257 315 373 431 489 547 605 663 721 779 837 895 953 1011 1069 1127 1185 1243 1301 1359 1417 1475 1533 1591 1649 1707 1765 1823 1881 1939 1997 2055 2113 2171 2229 2287 2345 2403 2461 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 PAD No. 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 17/72 PIN Name X Y SEG[109] SEG[110] SEG[111] SEG[112] SEG[113] SEG[114] SEG[115] SEG[116] SEG[117] SEG[118] SEG[119] SEG[120] SEG[121] SEG[122] SEG[123] SEG[124] SEG[125] SEG[126] SEG[127] SEG[128] SEG[129] SEG[130] SEG[131] Reserve Reserve Reserve Reserve Reserve Reserve COM[26] COM[27] COM[28] COM[29] COM[30] COM[31] COM[32] COM[33] COM[34] COM[35] COM[36] COM[37] COM[38] COM[39] COM[40] (NC) 2519 2577 2635 2693 2751 2809 2867 2925 2983 3041 3099 3157 3215 3273 3331 3389 3447 3505 3563 3621 3679 3737 3795 3853 3911 3969 4027 4085 4143 4201 4259 4542 4542 4542 4542 4542 4542 4542 4542 4542 4542 4542 4542 4542 4542 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -374 -345 -287 -229 -171 -113 -55 3 61 119 177 235 293 351 404 2009/09/07 ST7565S BLOCK DIAGRAM COMS 132 SEGMENT DRIVERS COMS COM63 COM0 SEG131 SEG0 VDD V1 V2 V3 V4 V5 64 COMMON DRIVERS COM output control circuit Voltage follower circuit Display data latch circuit VRS IRS Voltage Regulator circuit Power Supply Circuit Status VSS FRS M/S CL DOF FR Column address circuit Voltage booster circuit Oscillator circuit VSS2 DISPLAY DATA RAM 65 X 132 = 8580 Bits VOUT CAP1+ CAP1CAP2+ CAP2CAP3+ CAP4CAP5- Line address circuit VR I/O buffer Page address circuit V5 Display timing generator circuit HPM Command decoder CLS Bus holder MPU INTERFACE ( Parallel and Serial ) D7(SI) D6(SCL) D5 D4 D3 D2 D1 18/72 D0 P/S C86 /RES CS2 CS1 A0 RW(/WR) E(/RD) SEL3 SEL2 SEL1 Ver 0.6c 2009/09/07 ST7565S PIN DESCRIPTIONS Power Supply Pins Pin Name I/O Function No. of Pins VDD Power Shared with the MPU power supply terminal Vcc. Supply 13 VSS Power This is a 0V terminal connected to the system GND. Supply 10 VSS2 Power This is the reference power supply for the step-up voltage circuit for the liquid crystal Supply drive. 2 VRS Power This is the internal-output VREG power supply for the LCD power supply voltage Supply regulator. 2 This is a multi-level power supply for the liquid crystal drive. The voltage Supply applied is determined by the liquid crystal cell, and is changed through the use of a resistive voltage divided or through changing the impedance using an op. amp. Voltage levels are determined based on VDD, and must maintain the relative magnitudes shown below. VDD (= V0) ≧V1 ≧V2 ≧V3 ≧V4 ≧V5 V1, V2, V3, V4, V5 Power When the power supply turns ON, the internal power supply circuits produce the V1 to V4 Supply voltages shown below. The voltage settings are selected using the LCD bias set command. V1 V2 V3 V4 1/65 DUTY 1/9*V5,1/7*V5 2/9*V5,2/7*V5 7/9*V5,5/7*V5 8/9*V5,6/7*V5 1/49 DUTY 1/8*V5,1/6*V5 2/8*V5,2/6*V5 6/8*V5,4/6*V5 7/8*V5,5/6*V5 1/33 DUTY 1/6*V5,1/5*V5 2/6*V5,2/5*V5 4/6*V5,3/5*V5 5/6*V5,4/5*V5 1/55 DUTY 1/8*V5,1/6*V5 2/8*V5,2/6*V5 6/8*V5,4/6*V5 7/8*V5,5/6*V5 10 1/53 DUTY 1/8*V5,1/6*V5 2/8*V5,2/6*V5 6/8*V5,4/6*V5 7/8*V5,5/6*V5 LCD Power Supply Pins Pin Name I/O Function No. of Pins CAP1+ O DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1terminal. 4 CAP1– O DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1+ terminal. 2 CAP2+ O DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2terminal. 2 CAP2– O DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2+ terminal. 2 CAP3– O DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1+ terminal. 2 CAP4– O DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2+ terminal. 2 CAP5– O DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1+ terminal. 2 VOUT O DC/DC voltage converter. Connect a capacitor between this terminal and VSS. 2 I Output voltage regulator terminal. Provides the voltage between VDD and V5 through a resistive voltage divider. IRS = “L” : the V5 voltage regulator internal resistors are not used . IRS = “H” : the V5 voltage regulator internal resistors are used . 2 VR Ver 0.6c 19/72 2009/09/07 ST7565S System Bus Connection Pins Pin Name I/O Function I/O This is an 8-bit bi-directional data bus that connects to an 8-bit or 16-bit standard MPU data bus. When the serial interface is selected (P/S = “L”) : D7 : serial data input (SI) ; D6 : the serial clock input (SCL). D0 to D5 are set to high impedance. When the chip select is not active, D0 to D7 are set to high impedance. 8 A0 I This is connect to the least significant bit of the normal MPU address bus, and it determines whether the data bits are data or a command. A0 = “H”: Indicates that D0 to D7 are display data. A0 = “L”: Indicates that D0 to D7 are control data. 1 /RES I When /RES is set to “L,” the settings are initialized. The reset operation is performed by the /RES signal level. 1 /CS1 CS2 I This is the chip select signal. When /CS1 = “L” and CS2 = “H,” then the chip select becomes active, and data/command I/O is enabled. 2 I • When connected to an 8080 MPU, this is active LOW. (E) This pin is connected to the /RD signal of the 8080 MPU, and the ST7565S series data bus is in an output status when this signal is “L”. • When connected to a 6800 Series MPU, this is active HIGH. This is the 6800 Series MPU enable clock input terminal. 1 /WR (R/W) I • When connected to an 8080 MPU, this is active LOW. (R/W) This terminal connects to the 8080 MPU /WR signal. The signals on the data bus are latched at the rising edge of the /WR signal. • When connected to a 6800 Series MPU: This is the read/write control signal input terminal. When R/W = “H”: Read. When R/W = “L”: Write. 1 C86 I This is the MPU interface switch terminal. C86 = “H”: 6800 Series MPU interface. C86 = “L”: 8080 MPU interface. 1 D5 to D0 D6 (SCL) D7 (SI) /RD (E) No. of Pins This is the parallel data input/serial data input switch terminal. P/S = “H”: Parallel data input. P/S = “L”: Serial data input. The following applies depending on the P/S status: P/S I P/S Data/Command Data Read/Write Serial Clock “H” A0 D0 to D7 /RD, /WR X “L” A0 SI (D7) Write only SCL (D6) 1 When P/S = “L”, D0 to D5 fixed “H”. /RD (E) and /WR (R/W) are fixed to either “H” or “L”. With serial data input, It is impossible read data from RAM. Ver 0.6c 20/72 2009/09/07 ST7565S Pin Name I/O Function No. of Pins CLS I Terminal to select whether or enable or disable the display clock internal oscillator circuit. CLS = “H” : used Internal oscillator circuit . CLS = “L” : used external clock input .(internal oscillator is disable) When CLS = “L”, input the display clock through the CL terminal. 1 M/S I This terminal selects the master/slave operation for the ST7565S Series chips. Master operation outputs the timing signals that are required for the LCD display, while slave operation uses the input timing signals to synchronize the liquid crystal display system. M/S = “H” Master operation M/S = “L” Slave operation Power Oscillator M/S CLS Supply CL FR FRS DOF Circuit Circuit “H” “H” “L” Enabled Disabled Enabled Enabled Output Input Output Output Output Output Output Output “L” “H” “L” Disabled Disabled Disabled Disabled Input Input Input Input Output Output Input Input 1 This is the display clock input terminal. The following is true depending on the M/S and CLS status. M/S CLS CL CL I/O “H” “H” “L” Output Input “L” “H” “L” Input Input 1 FR O This is the liquid crystal alternating current signal terminal. 1 /DOF O This is the LCD blanking control terminal. 1 FRS O This is the output terminal for the static drive. This terminal is only enabled when the static indicator display is ON and is used in conjunction with the FR terminal. 1 I This terminal selects the resistors for the V5 voltage level adjustment. IRS = “H”: Use the internal resistors IRS = “L”: Do not use the internal resistors. The V5 voltage level is regulated by an external resistive voltage divider attached to the VR terminal 1 I This is the power control terminal for the power supply circuit for liquid crystal drive. /HPM = “H”: Normal mode /HPM = “L”: High power mode 1 IRS /HPM These pins are DUTY selection. SEL 3 , 2 , 1 DUTY SEL3 SEL2 SEL1 TEST0 ~ 5 Ver 0.6c I I BIAS 0,0,0 1/65 1/9 or 1/7 0,0,1 1/49 1/8 or 1/6 0,1,0 1/33 1/6 or 1/5 0,1,1 1/55 1/8 or 1/6 1,0,0 1/53 1/8 or 1/6 1, X , X ----- ----- These are terminals for IC testing. They are set to open. 3 6 21/72 2009/09/07 ST7565S LCD Driver Pins Pin Name SEG0 to SEG131 I/O Function No. of Pins These are the LCD segment drive outputs. Through a combination of the contents of the display RAM and with the FR signal, a single level is selected from VDD, V2, V3, and V5. Output Voltage RAM DATA FR Normal Display Reverse Display O H H VDD V2 H L V5 V3 L H V2 VDD L L V3 V5 Power save 132 VDD Through a combination of the contents of the scan data and with the FR signal, a single level is selected from VDD, V1, V4, and V5. Scan Data FR Output Voltage COM0 to COMn O H H V5 H L VDD L H V1 L L Power save COMS O 67 V4 VDD These are the COM output terminals for the indicator. Both terminals output the same signal. Leave these open if they are not used. 2 I/O PIN ITO Resister Limitation PIN Name FR, /DOF, C86, P/S, M/S, /HPM,SEL1…SEL3, CLS, IRS TEST0…6 VDD, VSS, VSS2, VOUT, VR, VRS V1, V2, V3, V4, V5, CAP1+, CAP1–, CAP2+, CAP2–, CAP3–, CAP4–, CAP5– /CS1, CS2, CL, E, R/W, A0, D0…D7, /RES Ver 0.6c 22/72 ITO Resister No Limitation Floating <100Ω <300Ω <1KΩ <10KΩ 2009/09/07 ST7565S DESCRIPTION OF FUNCTIONS The MPU Interface Selecting the Interface Type With the ST7565S chips, data transfers are done through an 8-bit parallel data bus (D7 to D0) or through a serial data input (SI). Through selecting the P/ S terminal polarity to the “H” or “L” it is possible to select either parallel data input or serial data input as shown in Table 1. P/S /CS1 CS2 A0 Table 1 /RD /WR C86 D7 D6 D5~D0 H: Parallel Input /CS1 CS2 A0 /RD /WR C86 D7 D6 D5~D0 A0 — — — SI SCL (HZ) L: Serial Input /CS1 CS2 “—” indicates fixed to either “H” or to “L” The Parallel Interface When the parallel interface has been selected (P/S =“H”), then it is possible to connect directly to either an 8080-system C86 (P/S=H) /CS1 CS2 MPU or a 6800 Series MPU (shown in Table 2) by selecting the C86 terminal to either “H” or to “L”. Table 2 A0 E(/RD) R/W(/WR) D7~D0 H: 6800 Series /CS1 CS2 A0 E R/W D7~D0 L: 8080 Series /CS1 CS2 A0 /RD /WR D7~D0 Moreover, data bus signals are recognized by a combination of A0, /RD (E), /WR (R/W) signals, as shown in Table 3. Ver 0.6c Table 3 8080 Series Shared 6800 Series A0 R/W /RD /WR 1 1 0 1 Reads the display data 1 0 1 0 Writes the display data 0 1 0 1 Status read 0 0 1 0 Write control data (command) 23/72 Function 2009/09/07 ST7565S The Serial Interface When the serial interface has been selected (P/S = “L”) then when the chip is in active state (/CS1 = “L” and CS2 = “H”) the serial data input (SI) and the serial clock input (SCL) can be received. The serial data is read from the serial data input pin in the rising edge of the serial clocks D7, D6 through D0, in this order. This data is converted to 8 bits parallel data in the rising edge of the eighth serial clock for the processing. The A0 input is used to determine whether or the serial data input is display data or command data; when A0 = “H”, the data is display data, and when A0 = “L” then the data is command data. The A0 input is read and used for detection every 8th rising edge of the serial clock after the chip becomes active. Figure 1 is a serial interface signal chart. CS1 CS2 SI D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 SCL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A0 Figure 1 * When the chip is not active, the shift registers and the counter are reset to their initial states. * Reading is not possible while in serial interface mode. * Caution is required on the SCL signal when it comes to line-end reflections and external noise. We recommend that operation be rechecked on the actual equipment. The Chip Select The ST7565S have two chip select terminals: /CS1 and CS2. The MPU interface or the serial interface is enabled only when /CS1 = “L” and CS2 = “H”. When the chip select is inactive, D0 to D7 enter a high impedance state, and the A0, /RD, and /WR inputs are inactive. When the serial interface is selected, the shift register and the counter are reset. The Accessing the Display Data RAM and the Internal Registers Data transfer at a higher speed is ensured since the MPU is required to satisfy the cycle time (tCYC) requirement alone in accessing the ST7565S. Wait time may not be considered. And, in the ST7565S, each time data is sent from the MPU, a type of pipeline process between LSIs is performed through the bus holder attached to the internal data bus. Internal data bus. For example, when the MPU writes data to the display data RAM, once the data is stored in the bus holder, then it is written to the display data RAM before the next data write cycle. Moreover, when the MPU reads the display data RAM, Ver 0.6c the first data read cycle (dummy) stores the read data in the bus holder, and then the data is read from the bus holder to the system bus at the next data read cycle. There is a certain restriction in the read sequence of the display data RAM. Please be advised that data of the specified address is not generated by the read instruction issued immediately after the address setup. This data is generated in data read of the second time. Thus, a dummy read is required whenever the address setup or write cycle operation is conducted. This relationship is shown in Figure 2. 24/72 2009/09/07 ST7565S The Busy Flag When the busy flag is “1” it indicates that the ST7565S is running internal processes, and at this time no command aside from a status read will be received. The busy flag is outputted to D7 pin with the read instruction. If the cycle time (tCYC) is maintained, it is not necessary to check for this flag before each command. This makes vast improvements in MPU processing capabilities possible. MPU Writing WR Internal Timing DATA N N+1 N+2 N BUS Holder N+1 N+3 N+2 N+3 Write Signal Reading MPU WR RD DATA N N n n+1 Increment N+1 N+2 Internal Timing Address Preset Read Signal Column Address Preset N Bus Holder N Address Set #n n Dummy Read n+1 Data Read #n n+2 Data Read #n+1 Figure 2 Ver 0.6c 25/72 2009/09/07 ST7565S Display Data RAM The display data RAM stores the dot data for the LCD. It has a 65 (8 page x 8 bit +1) x 132 bit structure. As is shown in Figure 3, the D7 to D0 display data from the MPU corresponds to the LCD display common direction; there are few constraints at the time of display data transfer when multiple ST7565S are used, thus and display structures can be created easily and with a high degree of freedom. Moreover, reading from and writing to the display RAM from the MPU side is performed through the I/O buffer, which is an independent operation from signal reading for the liquid crystal driver. Consequently, even if the display data RAM is accessed asynchronously during liquid crystal display, it will not cause adverse effects on the display (such as flickering). D0 0 1 1 1 0 COM0 D1 1 0 0 0 0 COM1 D2 0 0 0 0 0 COM2 D3 0 1 1 1 0 COM3 D4 1 0 0 0 0 COM4 - - Display data RAM Liquid crystal display Figure 3 The Page Address Circuit Page address of the display data RAM is specified through the Page Address Set Command. The page address must be specified again when changing pages to perform access. Page address 8 (D3, D2, D1, D0 = 1, 0, 0, 0) is a special RAM for icons, and only display data D0 is used (see Figure 4). The Column Addresses The display data RAM column address is specified by the Column Address Set command. The specified column address is incremented (+1) with each display data read/write command. This allows the MPU display data to be accessed continuously. Moreover, the increment of column addresses stops with 83H. The column address is independent of the page address. It is necessary to set both the page address and the column address again when moving from column 83H of page 0 to column 00H of page 1, for example. Furthermore, as is shown in Table 4, the ADC command (segment driver direction select command) can be used to reverse the relationship between the display data RAM column address and the segment output. Therefore, the constraints of the LCD module layout with this IC can be minimized. Table 4 SEG Output ADC (D0) “0” (D0) “1” SEG0 SEG 131 0 (H) 83 (H) Column Address Column Address 83 (H) 0 (H) The Line Address Circuit The line address circuit, as shown in Table 4, specifies the line address relating to the COM output when the contents of the display data RAM are displayed. Using the display start line address set command, what is normally the top line of the display can be specified (this is the COM0 output when the common output mode is normal, and the COM63 output for Ver 0.6c ST7565S , the detail is shown page.11 The display area is a 65 line area for the ST7565S. If the line addresses are changed dynamically using the display start line address set command, screen scrolling, page swapping, etc. can be performed. 26/72 2009/09/07 ST7565S Column address 0 1 ADC 83 D0 D0 LCD Out 82 00 S131 81 01 S130 80 02 S129 7F 03 S128 7E 04 S127 7D COM Output COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COMS Page 8 05 0 06 0 S126 0 S125 1 Page 7 7B 1 7C 1 07 1 08 0 Page 6 S124 0 S123 1 08 1 07 0 Page 5 7B 1 S8 0 06 1 7C 0 Page 4 S7 0 05 0 7D 1 S6 0 Page 3 04 1 7E 1 S5 0 03 0 Page 2 7F 0 S4 1 02 0 80 0 Page 1 S3 1 01 0 81 0 S2 0 When the common output is normal 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH Page 0 00 0 82 0 83 0 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 S0 0 Line Address Data S1 Page Address D3 D2 D1 D0 Regardless of the display start line address, 1/65duty => 64th line, 1/49duty =>48th line. 1/33duty =>32th line, 1/55duty =>54th line, 1/53duty =>52th line. Figure 4 Ver 0.6c 27/72 2009/09/07 ST7565S The Display Data Latch Circuit The display data latch circuit is a latch that temporarily stores the display data that is output to the liquid crystal driver circuit from the display data RAM. Because the display normal/reverse status, display ON/OFF status, and display all points ON/OFF commands control only the data within the latch, they do not change the data within the display data RAM itself. The Oscillator Circuit This is a CR-type oscillator that produces the display clock. The oscillator circuit is only enabled when M/S= “H” and CLS= “H”. When CLS = “L” the oscillation stops, and the external clock is input through the CL terminal. Display Timing Generator Circuit The display timing generator circuit generates the timing signal to the line address circuit and the display data latch circuit using the display clock. The display data is latched into the display data latch circuit synchronized with the display clock, and is output to the data driver output terminal. Reading to the display data liquid crystal driver circuits is completely independent of accesses to the display data RAM by the MPU. Consequently, even if the display data RAM is accessed asynchronously during liquid crystal display, there is absolutely no adverse effect (such as flickering) on the display. Moreover, the display timing generator circuit generates the common timing and the liquid crystal alternating current signal (FR) from the display clock. It generates a drive wave form using a 2 frame alternating current drive method, as is shown in Figure 5, for the liquid crystal drive circuit. Two-frame alternating current drive waveform 64 65 1 2 3 4 5 6 60 61 62 63 64 65 1 2 3 4 5 6 CL FR VDD V1 COM0 V4 V5 VDD V1 COM1 V4 V5 RAM Data VDD V2 SEGn V3 V5 Figure 5 Ver 0.6c 28/72 2009/09/07 ST7565S The Common Output Status Select Circuit In ST7565S, the COM output scan direction can be selected by the common “Common output mode select” (see Table 6). Status Duty Therefore, the constraints of the LCD module layout with this IC can be minimized. Table 6 COM Scan Direction 1/65 DUTY 1/49 DUTY 1/33 DUTY 1/55 DUTY 1/53 DUTY Normal COM0 → COM63 COM0 → COM47 COM0 → COM31 COM0 → COM53 COM0 → COM51 Reverse COM63 → COM0 COM47 → COM0 COM31 → COM0 COM53 → COM0 COM51 → COM0 COM mode 1/65 1/49 1/33 1/55 1/53 Ver 0.6c Common Output Pads COM[0:15] COM[16:23] COM[24:26] COM[27:36] COM[37:39] COM[40:47] COM[48:63] COMS 0 COM[0:63] COMS 1 COM[63:0] COMS 0 COM[0:23] Reserved COM[24:47] COMS 1 COM[47:24] Reserved COM[23:0] COMS 0 COM[0:15] Reserved COM[16:31] COMS 1 COM[31:16] Reserved COM[15:0] COMS 0 1 COM[0:26] COM[53:27] Reserved COM[27:53] COMS Reserved COM[26:0] COMS 0 COM[0:25] Reserved COM[26:51] COMS 1 COM[51:26] Reserved COM[25:0] COMS 29/72 2009/09/07 ST7565S The LCD Driver Circuits The LCD driver circuits generate four voltage levels to drive the LCD. The combination of display data, the COM scan signal and the FR signal produces the drive voltage of LCD. COM0 Figure 6 shows examples of the SEG and COM output wave form. FR VDD VSS COM0 V0 V1 V2 V3 V4 VSS COM1 V0 V1 V2 V3 V4 VSS COM2 V0 V1 V2 V3 V4 VSS SEG0 V0 V1 V2 V3 V4 VSS SEG1 V0 V1 V2 V3 V4 VSS COM0 to SEG0 V0 V1 V2 V3 V4 VSS -V4 -V3 -V2 -V1 -V0 COM0 to SEG1 V0 V1 V2 V3 V4 VSS -V4 -V3 -V2 -V1 -V0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 SEG 0 1 2 3 4 Figure 6 Ver 0.6c 30/72 2009/09/07 ST7565S The Power Supply Circuits The power supply circuits are low-power consumption power supply circuits that generate the voltage levels required for the LCD drivers. They are Booster circuits, voltage regulator circuits, and voltage follower circuits. They are only enabled in master operation. The power supply circuits can turn the Booster circuits, the voltage regulator circuits, and the voltage follower circuits ON or OFF independently through the use of the Power Control Set command. Consequently, it is possible to make an external power supply and the internal power supply function somewhat in parallel. Table 7 shows the Power Control Set Command 3-bit data control function, and Table 8 shows reference combinations. Table 7 bit D2 D1 D0 Status “1” “0” Function Booster circuit control bit (V/B circuit) ON Voltage regulator circuit control bit (V/R circuit) ON Voltage follower circuit control bit (V/F circuit) ON The Control Details of Each Bit of the Power Control Set Command OFF OFF OFF Table 8: Reference Power Circuits Combinations Use Settings D2 D1 D0 Voltage Booster Voltage Regulator Voltage Follower External power input Booster Capacitor Only the internal power supply is used 1 1 1 ON ON ON VSS2 Used Only the voltage regulator and follower circuits are used 0 1 1 OFF ON ON VOUT, VSS2 Open Only the voltage follower circuit is used 0 0 1 OFF OFF ON V5, VSS2 Open Only the external power supply is used 0 0 0 OFF OFF OFF V1 to V5 Open * The “Booster Capacitor” refers CAP1+, CAP1–, CAP2+, CAP2–, and CAP3–. * The other combinations (not shown above) are also possible, but they are not recommended because they have no practical use. The Step-up Voltage Circuits Using the booster circuits equipped within ST7565S, it is possible to generate a boosted voltage which is 2X, 3X, 4X, 5X or 6X step-up of the VDD – VSS2 voltage levels. The circuit connection is described below and illustrated in Figure 7. 6X step-up: Connect capacitor C1 between CAP1+ and CAP1–, between CAP2+ and CAP2–, between CAP1+ and CAP3–, between CAP2+ and CAP4–, between CAP1+ and CAP5–, and between VSS2 and VOUT. It produces a voltage level in the negative direction at the VOUT terminal, and which is 6 times the voltage level between VDD and VSS2. 5X step-up: Connect capacitor C1 between CAP1+ and CAP1–, between CAP2+ and CAP2–, between CAP1+ and CAP3–, between CAP2+ and CAP4–, and between VSS2 and VOUT. It produces a voltage level in the negative direction at the VOUT terminal, and which is 5 times the voltage level between VDD and VSS2. Ver 0.6c 4X step-up: Connect capacitor C1 between CAP1+ and CAP1–, between CAP2+ and CAP2–, between CAP1+ and CAP3–, and between VSS2 and VOUT. It produces a voltage level in the negative direction at the VOUT terminal, and which is 4 times the voltage level between VDD and VSS2. 3X step-up: Connect capacitor C1 between CAP1+ and CAP1–, between CAP2+ and CAP2–, between VSS2 and VOUT, and short CAP3– with VOUT. It produces voltages level in the negative direction at the VOUT terminal, and which is 3 times the voltage level between VDD and VSS2. 2X step-up: Connect capacitor C1 between CAP1+ and CAP1–, and between VSS2 and VOUT, and short CAP2– with CAP3– and VOUT (leave CAP2+ open). It produces a voltage in the negative direction at the VOUT terminal, and which is twice the voltage level between VDD and VSS2. 31/72 2009/09/07 ST7565S + C1 VDD / VSS2 + VDD / VSS2 C1 VOUT VOUT CAP3- CAP3- + C1 VDD / VSS2 VOUT CAP3- C1 + CAP1+ C1 + CAP1+ C1 CAP1- CAP1- CAP2- CAP1+ CAP1- CAP2C1 OPEN CAP2+ + C1 CAP2C1 + CAP2+ + CAP2+ OPEN CAP4- OPEN CAP4- OPEN CAP4- OPEN CAP5- OPEN CAP5- OPEN CAP5- 2x voltage booster circuit 3x voltage booster circuit 4x voltage booster circuit VDD=0V VSS2 Do NOT over voltage limitation VOUT<=2x(VSS2-VDD) 2x boost voltage relationship VDD=0V VSS2 Do NOT over voltage limitation VOUT<=3x(VSS2-VDD) 3x boost voltage relationship VDD=0V VSS2 Do NOT over voltage limitation VOUT<=4x(VSS2-VDD) 4x boost voltage relationship + C1 VDD / VSS2 + VDD / VSS2 C1 VOUT VOUT CAP3C1 + CAP3C1 + CAP1+ C1 CAP1- CAP1- CAP2C1 + CAP1+ C1 CAP2C1 + CAP2+ C1 CAP2+ C1 CAP4OPEN CAP5- CAP4C1 + CAP5- 5x voltage booster circuit 6x voltage booster circuit VDD=0V VSS2 Do NOT over voltage limitation VOUT<=5x(VSS2-VDD) 5x boost voltage relationship VDD=0V VSS2 Do NOT over voltage limitation VOUT<=6x(VSS2-VDD) 6x boost voltage relationship Figure 7 * The VSS2 voltage range must be set so that the VOUT terminal voltage does not exceed the absolute maximum rated value. * For compatibility with ST7565P, VOUT can connect to VSS2 or VDD.. Ver 0.6c 32/72 2009/09/07 ST7565S The Voltage Regulator Circuit The step-up voltage generated at VOUT outputs the LCD driver voltage V5 through the voltage regulator circuit. Because the ST7565S chips have an internal high-accuracy voltage regulator with a 64-level electronic volume control and internal resistors for the V5 voltage regulator, systems can be constructed without having to include high-accuracy voltage regulator circuit components. Note: * The internal VREG thermal gradient is approximate -0.05%/°C. * VDD is 0V unless otherwise specified. (A) When the V5 Voltage Regulator Internal Resistors Are Used Through the use of the V5 voltage regulator internal resistors and the electronic volume function the liquid crystal power supply voltage V5 can be controlled by commands alone (without adding any external resistors), making it possible to adjust the liquid crystal display brightness. The V5 voltage can be calculated using equation A-1 over the range where: | V5 | < | VOUT |. V ( Rb Ra ) Rb α =(1 + 1V ) ( Ra 162 ) α [∵ V = ( 1 - 162 ) V ] V5 = 1 + EV REG EV REG VDD VEV(constant voltage supply+electronic volume) Internal Ra V5 Internal Rb Figure 8 Ver 0.6c 33/72 2009/09/07 ST7565S If the power source is less than –2.1V, those relations cannot VREG is an internal voltage supply, and its voltage is fixed as shown in Table 9 (at Ta = 25°C). be maintained. Table 9 Part no. Equipment Type Thermal Gradient VREG ST7565S Internal Power Supply –0.05 %/°C –2.1V α is set to 1 of the 64 values which is selected by the 6-bit Table 10 shows the value for α when different electronic electronic volume register. It controls the VEV output level. volume parameters are set. Table 10 α D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 1 0 1 1 1 0 1 : : 1 1 1 1 1 1 1 1 1 63 62 61 : : 2 1 0 Rb/Ra is the resistor ratio of the internal V5 voltage regulator, The “1 + Rb/Ra” ratios are shown in Table 11 (reference and it can be set to 8 different levels through the command value), and they depend on the 3-bit data in the V5 voltage “V5 voltage regulator internal resistor ratio set”. regulator internal resistor ratio register. Table 11 Register ST7565S D2 D1 D0 0 0 0 0 1 1 1 1 Ver 0.6c 0 0 1 1 0 0 1 1 1 + Rb/Ra 0 1 0 1 0 1 0 1 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 34/72 2009/09/07 ST7565S V5 output voltage is controlled by two registers: V5 voltage regulator internal resistor ratio and the electronic volume. V5 UNIT:V Figures 9 shows V5 output levels with different internal resistance ratio and different electric volume. Ta = 25 °C and booster off ,regulator,follower on VSS=-3V -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 00H 111 110 101 100 011 010 001 000 V5 voltage regulator internal resistor ratio set D2,D1,D0 Electronic volume registered D5 ~ D0 1FH 3FH Figure 9 : Voltage Regulator Output (V5) Note: The internal Voltage Regulator output has the thermal gradient of -0.05%/°C. Using Figure 9 and the following parameters. Example: Set V5 = –7V (Ta = 25°C and temperature gradient = –0.05%/°C): Table 12 Register Contents D5 D4 D3 D2 D1 D0 V5 regulator resistor ratio – – – 0 1 0 Electronic Volume 1 0 0 1 0 1 At this time, the variable range and the notch width of the V5 The voltage level of V5 depends on the electronic volume. voltage is shown in Table 13. Table 13 V5 Min Typ Max Units Variable Range –8.4 (EV=63) –7.0 (EV=1,0,0,1,0,1) Notch width Ver 0.6c 51 35/72 –5.1 (EV=0) V mV 2009/09/07 ST7565S (B) When an External Resistance is Used (The V5 Voltage Regulator Internal Resistors Are Not Used) (1) The liquid crystal power supply voltage V5 can also be set without using the V5 voltage regulator internal resistors (IRS terminal = “L”) by adding resistors Ra’ and Rb’ between VDD and VR, and between VR and V5, respectively. When this is done, the use of the electronic volume function makes it possible to adjust the brightness of the liquid crystal display by controlling the liquid crystal power supply voltage V5 through commands. In the range where | V5 | < | VOUT |, the V5 voltage can be calculated using equation B-1 based on the external resistances Ra’ and Rb’. V ( Rb' Ra' ) Rb' α =(1 + 1V Ra' ) ( 162 ) α [∵ V = ( 1 - 162 ) V ] V5 = 1 + EV REG EV REG VDD External resistor Ra' VEV(fixed voltage power supply+electronic volume) V5 External resistor Rb' Figure 11 Setup example: When selecting Ta = 25°C and V5 = –7 V for ST7565S the temperature gradient = –0.05%/°C. When the central value of the electron volume register is (D5, D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0, 0), then α = 31 and VREG = –2.1V so, according to equation B-1, α 1( Rb' 162 ) Ra' ) ( 31 Rb' -7V = ( 1 + 1162 ) Ra' ) ( V5 = 1 + Consequently, by equations B-2 and B-3, Rb' = 3.12 Ra' VREG Ra' = 340kΩ (-2.1) Rb' = 1060kΩ Moreover, when the value of the current running through Ra’ and Rb’ is set to 5 uA, At this time, the V5 voltage variable range and notch width, based on the electron volume function, is as given in Table 14. Table 14 V5 Variable Range Min Typ Max Units –8.6 (EV=63) –7.0 (EV=1,0,0,0,0,0) –5.3 (EV=0) V Notch width Ver 0.6c 52 36/72 mV 2009/09/07 ST7565S (C) When External Resistors are Used (The V5 Voltage Regulator Internal Resistors Are Not Used) (2) When the external resistor described above are used, adding a variable resistor as well makes it possible to perform fine adjustments on Ra’ and Rb’, to set the liquid crystal drive voltage V5. In this case, the use of the electronic volume function makes it possible to control the liquid crystal power supply voltage V5 by commands to adjust the liquid crystal display brightness. In the range where | V5 | < | VOUT | the V5 voltage can be calculated by equation C-1 below based on the R1 and R2 (variable resistor) and R3 settings, where R2 can be subjected to fine adjustments (∆R2). V ( R3+R2-ΔR2 R1+ΔR2 ) R3+R2-ΔR2 α 1=(1 + R1+ΔR2 ) ( 162 ) α [∵ V = ( 1 - 162 ) V ] V5 = 1 + EV EV VREG REG VDD Ra' External resistor R2 Rb' VEV(fixed voltage power supply+electronic volume) External resistor R1 ΔR2 V5 VR External resistor R3 Figure 12 Setup example: When selecting Ta = 25°C and V5 = –5 t o –9 V (using R2) for an ST7565S the temperature gradient = –0.05%/°C. When the central value for the electronic volume register is set at (D5, D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0, 0), then α = 31 and VREG = –2.1V. According to equation C-1, when ΔR2 = 0Ω, in order to make V5 = –9 V, ( -9V= 1 + R3+R2 R1 31 ) ( 1 - 162 ) When the current flowing VDD and V5 is set to 5 uA, With this, according to equation C-2, C-3 and C-4, R1 = 264kΩ R2 = 211kΩ R3 = 925kΩ (-2.1) When ΔR2 = R2, in order to make V = –5 V, ( -5V= 1 + R3 R1+R2 31 ) ( 1 - 162 ) (-2.1) The V5 voltage variable range and notch width based on the electron volume function is as shown in Table 15. Table 15 V5 Variable Range Min Typ Max Units –9 (EV=63) –7.3 (EV=1,0,0,0,0,0) –5.5 (EV=0) V Notch width Ver 0.6c 56 37/72 mV 2009/09/07 ST7565S * When the V5 voltage regulator internal resistors or the electronic volume function is used, it is necessary to at least set the voltage regulator circuit and the voltage follower circuit to an operating mode using the power control set commands. Moreover, it is necessary to provide a voltage from VOUT when the Booster circuit is OFF. * The VR terminal is enabled only when the V5 voltage regulator internal resistors are not used (i.e. the IRS terminal = “L”). When the V5 voltage regulator internal resistors are used (i.e. when the IRS terminal = “H”), then the VR terminal is left open. * Because the input impedance of the VR terminal is high, it is necessary to take into consideration short leads, shield cables, etc. to handle noise. The LCD Voltage Generator Circuit The V5 voltage is produced by a resistive voltage divider within the IC, and can be produced at the V1, V2, V3, and V4 voltage levels required for liquid crystal driving. Moreover, when the voltage follower changes the impedance, it provides V1, V2, V3 and V4 to the liquid crystal drive circuit. High Power Mode that the display be checked on actual equipment to determine whether or not to use this mode. Moreover, if the improvement to the display is inadequate even after high power mode has been set, then it is necessary to add a liquid crystal drive power supply externally. The power supply circuit equipped in the ST7565S chips has very low power consumption (normal mode: HPM = “H”). However, for LCDs or panels with large loads, this low-power power supply may cause display quality to degrade. When this occurs, setting the HPM terminal to “L” (high power mode) can improve the quality of the display. We recommend The Internal Power Supply Shutdown Command Sequence The sequence shown in Figure 13 is recommended for shutting down the internal power supply, first placing the Sequence Step1 Step2 End power supply in power saver mode and then turning the power supply OFF. Details (Command, status) Display OFF Display all points ON Command address D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 1 1 1 0 Power saver 1 commands 0 1 0 0 1 0 Internal power supply OFF 1 (compound) Figure 13 The temperature gradient of the Internal Power Supply (-0.05%/°C) Ta=-40°C , V5=8.735V 8.735V Ta=25°C , V5=8.460V 8.460V Ta=85°C , V5=8.206V 8.206V V5 0V -40°C -20°C 0°C 25°C 50°C 85°C Ta Figure 14 Ver 0.6c 38/72 2009/09/07 ST7565S Reference Circuit Examples 1. When used all of the step-up circuit, voltage regulating circuit and V/F circuit (1) When the voltage regulator internal resistor is used. (2) When the voltage regulator internal resistor is not used. (Example where VSS2 = VSS, with 4x step-up) (Example where VSS2 = VSS, with 4x step-up) VDD VDD IRS M/S IRS VSS2 VSS M/S VSS2 C1 VSS C1 VOUT VOUT CAP3- CAP4- C1 CAP3- CAP4- CAP1+ CAP5- C1 CAP1+ CAP5- C1 C1 CAP1- CAP1- CAP2+ CAP2+ C1 C1 CAP2- CAP2- VR V5 R2 VDD VDD VR R1 VDD C2 VDD C2 V1 C2 C2 V2 C2 C2 V3 C2 C2 V4 C2 ST7565S R3 ST7565S V5 C2 V5 V1 V2 V3 V4 V5 2. When the voltage regulator circuit and V/F circuit alone are used (1) When the V5 voltage regulator internal resistor is not (2) When the V5 voltage regulator internal resistor is used. used. VDD IRS VDD M/S IRS VSS2 VSS2 VSS VSS VOUT External power supply CAP4- CAP1+ CAP5- External power supply CAP4- CAP1+ CAP5- CAP1- CAP2+ CAP2+ CAP2- CAP2- VR ST7565S ST7565S VR V5 R1 VDD VDD C2 C2 C2 C2 C2 Ver 0.6c CAP3- CAP1- V5 R2 VOUT CAP3- R3 VDD M/S VDD C2 V1 C2 V2 C2 V3 C2 V4 C2 V5 39/72 V1 V2 V3 V4 V5 2009/09/07 ST7565S (3) When the V/F circuit alone is used (4) When the built-in power is not used VDD VDD VSS IRS M/S IRS VSS2 M/S VSS2 VSS VOUT CAP4- CAP3- CAP4- CAP1+ CAP5- CAP1+ CAP5- CAP1- CAP1- CAP2+ CAP2+ CAP2- CAP2- VR V5 VR VDD ST7565S V5 ST7565S External power supply VOUT CAP3- VDD C2 C2 C2 C2 C2 VDD VDD V1 V1 V2 V2 V3 External power supply V3 V4 V4 V5 V5 Note: Item Set value Units C1 C2 1.0 ~ 4.7 0.1 ~ 4.7 uF uF * C1 and C2 are determined by the size of the LCD being driven Note: 1. Because the VR terminal input impedance is high, use short leads and shielded lines. 2. C1 and C2 are determined by the size of the LCD being driven. Select a value that will stabilize the liquid crystal drive voltage. Example of the Process by which to Determine the Settings: Turn the voltage regulator circuit and voltage follower circuit ON and supply a voltage to VOUT from the outside. Determine C2 by displaying an LCD pattern with a heavy load (such as horizontal stripes) and selecting a C2 that stabilizes the liquid crystal drive voltages (V1 to V5). Note that all C2 capacitors must have the same capacitance value. Next turn all the power supplies ON and determine C1. Ver 0.6c 40/72 2009/09/07 ST7565S The Reset Circuit When the /RES input comes to the “L” level, these LSIs return to the default state. Their default states are as follows: 1. Display OFF 2. Normal display 3. ADC select: Normal (ADC command D0 = “L”) 4. Power control register: (D2, D1, D0) = (0, 0, 0) 5. Serial interface internal register data clear 6. LCD power supply bias rate: 1/65 DUTY = 1/9 bias 1/49,1/55,1/53 DUTY = 1/8 bias 1/33 DUTY = 1/6 bias 7. All-indicator lamps-on OFF (All-indicator lamps ON/OFF command D0 = “L”) 8. Power saving clear 9. V5 voltage regulator internal resistors Ra and Rb separation 10. Output conditions of SEG and COM terminals SEG=VDD , COM=VDD 11. Read modify write OFF 12. Static indicator OFF Static indicator register : (D1, D2) = (0, 0) 13. Display start line set to first line 14. Column address set to Address 0 15. Page address set to Page 0 16. Common output status normal 17. V5 voltage regulator internal resistor ratio set mode clear Ver 0.6c 18. Electronic volume register set mode clear Electronic volume register : (D5, D4, D3, D2, D1, D0) = (1, 0. 0, 0, 0,0) 19. Test mode clear On the other hand, when the reset command is used, the above default settings from 11 to 19 are only executed. When the power is turned on, the IC internal state becomes unstable, and it is necessary to initialize it using the /RES terminal. After the initialization, each input terminal should be controlled normally. Moreover, when the control signal from the MPU is in the high impedance, an over current may flow to the IC. After applying a current, it is necessary to take proper measures to prevent the input terminal from getting into the high impedance state. If the internal liquid crystal power supply circuit is not used on ST7565S,it is necessary that /RES is “H” when the external liquid crystal power supply is turned on. This IC has the function to discharge V5 when /RES is “L,” and the external power supply short-circuits to VDD when /RES is “L”. This means that an internal resistor is connected between VDD and V5. While /RES is “L,” the oscillator works but the display timing generator stops, and the CL, FR, FRS and /DOF terminals are fixed to “H.” The terminals D0 to D7 are not affected. The VDD level is output from the SEG and COM output terminals after a successful hardware reset. 41/72 2009/09/07 ST7565S COMMANDS The ST7565S identify the data bus signals by a combination of A0, /RD (E), /WR(R/W) signals. Command interpretation and execution does not depend on the external clock, but rather is performed through internal timing only, and thus the processing is fast enough that normally a busy check is not required. In the 8080 MPU interface, commands are launched by inputting a low pulse to the RD terminal for reading, and inputting a low pulse to the /WR terminal for writing. In the 6800 Series MPU interface, the interface is placed in a read mode when an “H” signal is input to the R/W terminal and placed in a write mode when a “L” signal is input to the R/W terminal and then the command is launched by inputting a high pulse to the E terminal. Consequently, the 6800 Series MPU interface is different than the 80x86 Series MPU interface in that in the explanation of commands and the display commands the status read and display data read /RD (E) becomes “1(H)”. In the explanations below the commands are explained using the 8080 Series MPU interface as the example. When the serial interface is selected, the data is input in sequence starting with D7. <Explanation of Commands> Display ON/OFF This command turns the display ON and OFF. E R/W A0 0 /RD 1 /WR 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 1 D0 Setting 1 Display ON 0 Display OFF When the display OFF command is executed when in the display all points ON mode, power saver mode is entered. See the section on the power saver for details. Display Start Line Set This command is used to specify the display start line address of the display data RAM shown in Figure 4. For further details see the explanation of this function in “The Line Address Circuit”. E R/W A0 0 /RD 1 /WR 0 D7 D6 D5 D4 D3 D2 D1 D0 Line address 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 0 1 0 1 2 ↓ 62 63 ↓ Page Address Set This command specifies the page address corresponding to the low address when the MPU accesses the display data RAM (see Figure 4). Specifying the page address and column address enables to access a desired bit of the display data RAM. Changing the page address does not accompany a change in the status display. E R/W A0 0 /RD 1 /WR 0 D7 D6 D5 D4 D3 D2 D1 D0 Page address 1 0 1 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 0 1 2 ↓ 7 8 0 1 Ver 0.6c ↓ 42/72 2009/09/07 ST7565S Column Address Set This command specifies the column address of the display data RAM shown in Figure 4. The column address is split into two sections (the higher 4 bits and the lower 4 bits) when it is set (fundamentally, set continuously). Each time the display data RAM is accessed, the column address automatically increments (+1), making it possible for the MPU to continuously read from/write to the display data. The column address increment is topped at 83H. This does not change the page address continuously. See the function explanation in “The Column Address Circuit,” for details. E R/W Column A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0 A7 A6 A5 A4 A3 A2 A1 A0 address 0 1 0 High bits → 0 0 0 1 A7 A6 A5 A4 0 0 0 0 0 0 0 0 0 Low bits → 0 A3 A2 A1 A0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 2 ↓ ↓ 1 0 0 0 0 0 1 0 130 1 0 0 0 0 0 1 1 131 Status Read E R/W A0 /RD /WR 0 0 1 BUSY ADC ON/OFF RESET D7 D6 BUSY ADC D5 D4 ON/OFF RESET D3 D2 D1 D0 0 0 0 0 BUSY = 1: it indicates that either processing is occurring internally or a reset condition is in process. BUSY = 0: A new command can be accepted . if the cycle time can be satisfied, there is no need to check for BUSY conditions. This shows the relationship between the column address and the segment driver. 0: Reverse (column address 131-n ↔ SEG n) 1: Normal (column address n ↔ SEG n) (The ADC command switches the polarity.) ON/OFF: indicates the display ON/OFF state. 0: Display ON 1: Display OFF (This display ON/OFF command switches the polarity.) This indicates that the chip is in the process of initialization either because of a /RES signal or because of a reset command. 0: Operating state 1: Reset in progress Display Data Write This command writes 8-bit data to the specified display data RAM address. Since the column address is automatically incremented by “1” after the write, the MPU can write the display data. E R/W A0 /RD /WR 1 0 1 Ver 0.6c D7 D6 D5 D4 D3 D2 D1 D0 Write data 43/72 2009/09/07 ST7565S Display Data Read This command reads 8-bit data from the specified display data RAM address. Since the column address is automatically incremented by “1” after the read, the CPU can continuously read multiple-word data. One dummy read is required immediately after the column address has been set. See the function explanation in “Display Data RAM” for the explanation of accessing the internal registers. When the serial interface is used, reading of the display data becomes unavailable. E R/W A0 /RD /WR 1 0 D7 D6 D5 D4 D3 D2 D1 D0 1 Read data ADC Select (Segment Driver Direction Select) This command can reverse the correspondence between the display RAM data column address and the segment driver output. Thus, sequence of the segment driver output pins may be reversed by the command. See the column address circuit (page 1–20) for the detail. Increment of the column address (by “1”) accompanying the reading or writing the display data is done according to the column address indicated in Figure 4. E R/W A0 0 /RD 1 /WR 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 0 1 Setting Normal Reverse Display Normal/Reverse This command can reverse the lit and unlit display without overwriting the contents of the display data RAM. When this is done the display data RAM contents are maintained. E R/W A0 0 /RD 1 /WR 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 1 D0 0 1 Setting RAM Data “H” LCD ON voltage (normal) RAM Data “L” LCD ON voltage (reverse) Display All Points ON/OFF This command makes it possible to force all display points ON regardless of the content of the display data RAM. The contents of the display data RAM are maintained when this is done. This command takes priority over the display normal/reverse command. E R/W A0 0 /RD 1 /WR 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 0 D0 0 1 Setting Normal display mode Display all points ON When the display is in an OFF mode, executing the display all points ON command will place the display in power save mode. For details, see the Power Save section. Ver 0.6c 44/72 2009/09/07 ST7565S LCD Bias Set This command selects the voltage bias ratio required for the liquid crystal display. A0 E R/W /RD /WR 1 0 0 Select Status D7 D6 D5 D4 D3 D2 D1 D0 1/65duty 1/49duty 1/33duty 1/55duty 1/53duty 1 0 1 0 0 0 1 0 1/9 bias 1/8 bias 1/6 bias 1/8 bias 1/8 bias 1 1/7 bias 1/6 bias 1/5 bias 1/6 bias 1/6 bias Read/Modify/Write This command is used paired with the “END” command. Once this command has been input, the display data read command does not change the column address, but only the display data write command increments (+1) the column address. This mode is maintained until the END command is input. When the END command is input, the column address returns to the address it was at when the read/modify/write command was entered. This function makes it possible to reduce the load on the MPU when there are repeating data changes in a specified display region, such as when there is a blanking cursor. E R/W A0 /RD /WR 1 0 0 D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 0 0 0 0 0 * Even in read/modify/write mode, other commands aside from display data read/write commands can also be used. Page address set Column address set Read-modify-write cycle Dummy read Data read Data write NO Changes Finished ? YES END Figure 24 Command Sequence For read modify write Return Column address N N+1 N+2 N+3 Read-modify-write mode set N+m N End Figure 25 Ver 0.6c 45/72 2009/09/07 ST7565S End This command releases the read/modify/write mode, and returns the column address to the address it was at when the mode was entered. E R/W A0 /RD /WR 1 0 0 D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 0 1 1 1 0 Reset This command initializes the display start line, the column address, the page address, the common output mode, the V5 voltage regulator internal resistor ratio, the electronic volume, and the static indicator are reset, and the read/modify/write mode and test mode are released. There is no impact on the display data RAM. See the function explanation in “Reset” for details. The reset operation is performed after the reset command is entered. E R/W A0 /RD /WR 0 1 D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 1 0 0 0 1 0 The initialization when the power supply is applied must be done through applying a reset signal to the /RES terminal. The reset command must not be used instead. Common Output Mode Select This command can select the scan direction of the COM output terminal. For details, see the function explanation in “Common Output Mode Select Circuit.” E R/W Selected Mode A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 0 0 0 1 * * * 1/65duty 1/49duty 1/33duty 1/55duty 1/53duty Normal COM0→COM63 COM0→COM47 COM0→COM31 COM0→COM53 COM0→COM51 Reverse COM63→COM0 COM47→COM0 COM31→COM0 COM53→COM0 COM51→COM0 * Disabled bit Ver 0.6c 46/72 2009/09/07 ST7565S Power Controller Set This command sets the power supply circuit functions. See the function explanation in “The Power Supply Circuit,” for details E R/W A0 /RD /WR 0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Selected Mode 0 0 1 0 1 0 Booster circuit: OFF 1 Booster circuit: ON 0 Voltage regulator circuit: OFF 1 Voltage regulator circuit: ON 0 Voltage follower circuit: OFF 1 Voltage follower circuit: ON V5 Voltage Regulator Internal Resistor Ratio Set This command sets the V5 voltage regulator internal resistor ratio. For details, see the function explanation is “The Voltage Regulator circuit " and Table 11 . E R/W A0 /RD /WR 0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 ↓ 1 1 1 1 1 1 Rb/Ra Ratio Small ↓ Large The Electronic Volume (Double Byte Command) This command makes it possible to adjust the brightness of the liquid crystal display by controlling the LCD drive voltage V5 through the output from the voltage regulator circuits of the internal liquid crystal power supply. This command is a two byte command used as a pair with the electronic volume mode set command and the electronic volume register set command, and both commands must be issued one after the other. The Electronic Volume Mode Set When this command is input, the electronic volume register set command becomes enabled. Once the electronic volume mode has been set, no other command except for the electronic volume register command can be used. Once the electronic volume register set command has been used to set data into the register, then the electronic volume mode is released. E R/W A0 /RD /WR 0 Ver 0.6c 1 0 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 0 0 0 1 47/72 2009/09/07 ST7565S Electronic Volume Register Set By using this command to set six bits of data to the electronic volume register, the liquid crystal drive voltage V5 assumes one of the 64 voltage levels. When this command is input, the electronic volume mode is released after the electronic volume register has been set. E R/W A0 /RD /WR 0 1 0 D7 D6 D5 * * 0 * * 0 * * 0 * * * * 1 1 D4 0 0 0 D3 D2 0 0 0 0 0 0 ↓ 1 1 1 1 1 1 D1 0 1 1 D0 1 0 1 1 1 0 1 | V5 | Small ↓ Large * Inactive bit (set “0”) When the electronic volume function is not used, set this to (1, 0, 0, 0, 0, 0) The Electronic Volume Register Set Sequence electronic volume mode set electronic volume register set Electronic volume mode clear NO Set complete ? YES Figure 26 Static Indicator (Double Byte Command) This command controls the static drive system indicator display. The static indicator display is controlled by this command only, and is independent of other display control commands. This is used when one of the static indicator liquid crystal drive electrodes is connected to the FR terminal, and the other is connected to the FRS terminal. A different pattern is recommended for the static indicator electrodes than for the dynamic drive electrodes. If the pattern is too close, it can result in deterioration of the liquid crystal and of the electrodes. The static indicator ON command is a double byte command paired with the static indicator register set command, and thus one must execute one after the other. (The static indicator OFF command is a single byte command.) Static Indicator ON/OFF When the static indicator ON command is entered, the static indicator register set command is enabled. Once the static indicator ON command has been entered, no other command aside from the static indicator register set command can be used. This mode is cleared when data is set in the register by the static indicator register set command. E R/W A0 /RD /WR 0 Ver 0.6c 1 0 D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 1 1 0 0 1 Static Indicator OFF ON 48/72 2009/09/07 ST7565S Static Indicator Register Set This command sets two bits of data into the static indicator register, and is used to set the static indicator into a blinking mode. E R/W A0 /RD /WR 0 1 0 D7 D6 D5 D4 D3 D2 D1 * * * * * * 0 0 1 1 D0 0 1 0 1 Indicator Display State OFF ON (blinking at approximately one second intervals) ON (blinking at approximately 0.5 second intervals) ON (constantly on) * Disabled bit (set “0”) Static Indicator Register Set Sequence Static indicator mode set Static indicator register set Static indicator mode clear NO Set complete ? YES Figure 27 Power Save (Compound Command) When the display all points ON is performed while the display is in the OFF mode, the power saver mode is entered, thus greatly reducing power consumption. The power saver mode has two different modes: the sleep mode and the standby mode. When the static indicator is OFF, it is the sleep mode that is entered. When the static indicator is ON, it is the standby mode that is entered. In the sleep mode and in the standby mode, the display data is saved as is the operating mode that was in effect before the power saver mode was initiated, and the MPU is still able to access the display data RAM. Refer to figure 28 for power save off sequence. Static indicator ON Static indicator OFF Display OFF Display OFF Display all point ON Display all point ON Standby mode Sleep mode Power save OFF ( Display all point OFF ) Power save OFF Display all point OFF Static indicator ON (2 bytes) Standby mode cancel Sleep mode cancel Figure 28 Ver 0.6c 49/72 2009/09/07 ST7565S Sleep Mode This stops all operations in the LCD display system, and as long as there are no accesses from the MPU, the consumption current is reduced to a value near the static current. The internal modes during sleep mode are as follows: 1. The oscillator circuit and the LCD power supply circuit are halted. 2. All liquid crystal drive circuits are halted, and the segment in common drive outputs output a VDD level. Standby Mode The duty LCD display system operations are halted and only the static drive system for the indicator continues to operate, providing the minimum required consumption current for the static drive. The internal modes are in the following states during standby mode. 1 The LCD power supply circuits are halted. The oscillator circuit continues to operate. 2 The duty drive system liquid crystal drive circuits are halted and the segment and common driver outputs output a VDD level. The static drive system does not operate. When a reset command is performed while in standby mode, the system enters sleep mode. * When an external power supply is used, it is recommended that the functions of the external power supply circuit be stopped when the power saver mode is started. For example, when the various levels of liquid crystal drive voltage are provided by external resistive voltage dividers, it is recommended that a circuit be added in order to cut the electrical current flowing through the resistive voltage divider circuit when the power saver mode is in effect. The ST7565S series chips have a liquid crystal display blanking control terminal /DOF. This terminal enters an “L” state when the power saver mode is launched. Using the output of /DOF, it is possible to stop the function of an external power supply circuit. * When the master is turned on, the oscillator circuit is operable immediately after the powering on. The Booster Ratio (Double Byte Command) This command makes it possible to select step-up ratio. It is used when the power control set have turn on the internal booster circuit. This command is a two byte command used as a pair with the booster ratio select mode set command and the booster ratio register set command, and both commands must be issued one after the other. Booster Ratio Select Mode Set When this command is input, the Booster ratio register set command becomes enabled. Once the booster ratio select mode has been set, no other command except for the booster ratio register command can be used. Once the booster ratio register set command has been used to set data into the register, then the booster ratio select mode is released. E R/W A0 /RD /WR 0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 1 0 0 0 Booset Ratio Register Set By using this command to set two bits of data to the booster ratio register,it can be select what kind of the booster ratio can be used. When this command is input, the booster ratio select mode is released after the booster ratio register has been set. E R/W Booster D7 D6 D5 D4 D3 D2 D1 D0 ratio A0 /RD /WR select * * * * * * 0 0 2x,3x,4x 0 1 0 * * * * * * 0 1 5x 6x * * * * * * 1 1 * Inactive bit (set “0”) When the booster ratio select function is not used, set this to (0, 0) 2x,3x,4x step-up mode Ver 0.6c 50/72 2009/09/07 ST7565S The booster ratio Register Set Sequence booster ratio select mode set booster ratio register set Booster ratio select mode clear NO Set complete ? YES Figure 29 NOP Non-OPeration Command E R/W A0 /RD /WR 0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 0 0 0 1 1 Test This is a command for IC chip testing. Please do not use it. If the test command is used by accident, it can be cleared by applying a “L” signal to the /RES input by the reset command or by using an NOP. E R/W A0 /RD /WR 0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 1 1 * * * Inactive bit Note: The ST7565S maintain their operating modes until something happens to change them. Consequently, excessive external noise, etc., can change the internal modes of the ST7565S . Thus in the packaging and system design it is necessary to suppress the noise or take measure to prevent the noise from influencing the chip. Moreover, it is recommended that the operating modes be refreshed periodically to prevent the effects of unanticipated noise. Ver 0.6c 51/72 2009/09/07 ST7565S Table 16: Table of ST7565S Commands Command Code Command A0 /RD /WR Function D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 1 1 1 0 1 LCD display ON/OFF 0: OFF, 1: ON Sets the display RAM display start Display start address line address Sets the display RAM page 1 1 Page address address 0 1 Most significant Sets the most significant 4 bits of column address the display RAM column address. 0 0 Least significant Sets the least significant 4 bits of column address the display RAM column address. (1) Display ON/OFF 0 1 0 (2) Display start line set 0 1 0 0 1 (3) Page address set 0 1 0 1 0 (4) Column address set 0 upper bit Column address set 0 lower bit 1 0 0 0 1 0 0 0 (5) Status read 0 0 1 (6) Display data write 1 1 0 Write data (7) Display data read 1 0 1 Read data (8) ADC select Writes to the display RAM Reads from the display RAM Sets the display RAM address SEG output correspondence 0: normal, 1: reverse Sets the LCD display normal/ reverse 0: normal, 1: reverse Display all points 0: normal display 1: all points ON Sets the LCD drive voltage bias ratio 0: 1/9 bias, 1: 1/7 bias (ST7565S) Column address increment At write: +1 At read: 0 0 0 1 1 0 1 0 0 1 1 0 1 1 0 1 0 0 1 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 1 0 0 0 0 0 1 0 1 1 1 0 1 1 1 0 Clear read/modify/write 0 1 0 1 1 1 0 0 0 1 0 Internal reset 0 1 0 1 1 0 0 0 1 * * * 0 1 0 0 0 1 0 1 Operating mode Select COM output scan direction 0: normal direction 1: reverse direction Select internal power supply operating mode 1 0 0 0 1 0 0 Resistor ratio Select internal ratio(Rb/Ra) mode 1 0 1 0 0 0 0 0 0 0 1 0 Electronic volume value 1 0 1 0 1 1 1 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 step-up value (10) Display all points 0 ON/OFF 1 0 (11) LCD bias set 0 1 0 (12) Read/modify/write 0 1 (13) End 0 (14) Reset (16) Power control set Reads the status data 0 0 output 0 0 1 Common mode select 0 0 0 (15) 0 1 0 normal/ 0 0 1 Display reverse Status 1 0 (9) (Note) *: disabled data (17) V5 voltage regulator internal resistor ratio 0 set (18) Electronic volume mode set 0 Electronic volume register set (19) Static indicator ON/OFF 0 Static indicator register set resistor Set the V5 output voltage electronic volume register 0 0 0: OFF, 1: ON 1 0 Mode Set the flashing mode select booster ratio 00: 2x,3x,4x 01: 5x 11: 6x Display OFF and display all points ON compound command 0 1 0 1 0 (22) NOP 0 1 0 1 1 1 0 0 0 1 1 Command for non-operation (23) Test 0 1 0 1 1 1 1 * * * * Command for IC test. Do not use this command (20) Booster ratio set (21) Power saver Ver 0.6c 52/72 2009/09/07 ST7565S COMMAND DESCRIPTION Instruction Setup: Reference (1) Initialization Note: With this IC, when the power is applied, LCD driving non-selective potentials V2 and V3 (SEG pin) and V1 and V4 (COM pin) are output through the LCD driving output pins SEG and COM. When electric charge is remaining in the smoothing capacitor connecting between the LCD driving voltage output pins (V1 ~ V5) and the VDD pin, the picture on the display may become totally dark instantaneously when the power is turned on. To avoid occurrence of such a failure, we recommend the following flow when turning on the power. 1. When the built-in power is being used immediately after turning on the power: Turn ON the power and keeping the /RES pin = “L” When the power is stabilized Release the reset state. (/RES pin = “H”) Waiting reset circuit stabilized (<1ms) Initialized state (Default) *1 Function setup by command input (User setup) (11) LCD bias setting *2 (8) ADC selection *3 (15) Common output state selection *4 Function setup by command input (User setup) (17) Setting the built-in resistance radio for regulation of the V5 voltage *5 (18) Electronic volume control *6 Arrange to execute all the procedures from releasing the reset state through setting the power control within 5ms. (In case of other models) execute the procedures from turning on the power to setting the power control in 5ms. Function setup by command input (User setup) (16) Power control setting *7 This concludes the initialization * The target time of 5ms will result to vary depending on the panel characteristics and the capacitance of the smoothing capacitor. Therefore, we suggest you to conduct an operation check using the actual equipment. Notes: Refer to respective sections or paragraphs listed below. *1: Description of functions; Resetting circuit *2: Command description; LCD bias setting *3: Command description; ADC selection *4: Command description; Common output state selection *5: Description of functions; Power circuit & Command description; Setting the built-in resistance radio for regulation of the V5 voltage *6: Description of functions; Power circuit & Command description; Electronic volume control *7: Description of functions; Power circuit & Command description; Power control setting Ver 0.6c 53/72 2009/09/07 ST7565S 2. When the built-in power is not being used immediately after turning on the power: Turn ON the VDD-VSS power keeping the /RES pin = “L”. When the power is stabilized Release the reset state. (/RES pin = “H”) Waiting reset circuit stabilized (<1ms) Initialized state (Default) *1 Power saver START (multiple commands) *8 Arrange to start the power s aver within 5ms after releasing the reset state. (In case of other models) execute the procedures from turning on the power to setting the power control in 5ms. Function setup by command input (User setup) (11) LCD bias setting *2 (8) ADC selection *3 (15) Common output state selection *4 Function setup by command input (User setup) (17) Setting the built-in resistance radio for regulation of the V5 voltage *5 (18) Electronic volume control *6 Power saver OFF *8 Function setup by command input (User setup) (16) Power control setting *7 Arrange to start power control setting within 5ms after turning OFF the power saver. This concludes the initialization * The target time of 5ms will result to vary depending on the panel characteristics and the capacitance of the smoothing capacitor. Therefore, we suggest you to conduct an operation check using the actual equipment. Notes: Refer to respective sections or paragraphs listed below. *1: Description of functions; Resetting circuit *2: Command description; LCD bias setting *3: Command description; ADC selection *4: Command description; Common output state selection *5: Description of functions; Power circuit & Command description; Setting the built-in resistance radio for regulation of the V5 voltage *6: Description of functions; Power circuit & Command description; Electronic volume control *7: Description of functions; Power circuit & Command description; Power control setting *8: The power saver ON state can either be in sleep state or stand-by state. Command description; Power saver START (multiple commands) Ver 0.6c 54/72 2009/09/07 ST7565S (2) Data Display End of initialization Function setup by command input (User setup) (2) Display start line set *9 (3) Page address set *10 (4) Column address set *11 Function setup by command input (User setup) (6) Display data write *12 Function setup by command input (User setup) (1) Display ON/OFF *13 End of data display Notes: Reference items *9: Command Description; Display start line set *10: Command Description; Page address set *11: Command Description; Column address set *12: Command Description; Display data write *13: Command Description; Display ON/OFF Avoid displaying all the data at the data display start (when the display is ON) in white. (3) Power OFF *14 Optional status Function setup by command input (User setup) (20) Power save *15 Reset active (/RES pin = “L”) VDD – VSS power OFF Set the time ( t L ) from reset active to turning off the VDD VSS power (VDD - VSS = 1.8V) longer than the time (tH) when the potential of V5 ~ V1 becomes below the threshold voltage (approximately 1V) of the LCD panel. For tH, refer to the <Reference Data> of this event. When tH is too long, insert a resistor between V5 and VDD to reduce it. Notes: Reference items *14: The logic circuit of this IC’s power supply VDD - VSS controls the driver of the LCD power supply VDD - V5. So, if the power supply VDD - VSS is cut off when the LCD power supply VDD - V5 has still any residual voltage, the driver (COM. SEG) may output any uncontrolled voltage. When turning off the power, observe the following basic procedures: • After turning off the internal power supply, make sure that the potential V5 ~ V1 has become below the threshold voltage of the LCD panel, and then turn off this IC’s power supply (VDD - VSS). 6. Description of Function, 6.7 Power Circuit *15: After inputting the power save command, be sure to reset the function using the /RES terminal until the power supply VDD - VSS is turned off. 7. Command Description (20) Power Save *16: After inputting the power save command, do not reset the function using the /RES terminal until the power supply VDD - VSS is turned off. 7. Command Description (20) Power Save Ver 0.6c 55/72 2009/09/07 ST7565S Refresh It is recommended to turn on the refresh sequence regularly at a specified interval. Refresh sequence Reset command or NOP command Set all commands to the ready state Refreshing of DRAM Precautions on Turning off the power <Turning the power (VDD - VSS) off> 1) Power Save (The LCD powers (VDD - V5) are off.) → Reset input → Power (VDD - VSS) OFF • Observe tL > tH. • When tL < tH, an irregular display may occur. Set tL on the MPU according to the software. tH is determined according to the external capacity C2 (smoothing capacity of V5 ~ V1) and the driver’s discharging capacity. Power Off Reset Power save tL VDD 1.8V RES VDD SEG Since the power (VDD-VSS) is cut off,the output comes not to be fixed. VDD COM V1 V2 V3 V4 V5 Ver 0.6c About 1V:below Vth of the LCD Panel tH 56/72 2009/09/07 ST7565S <Turning the power (VDD - VSS) off : When command control is not possible.> 2) Reset (The LCD powers (VDD - VSS) are off.) → Power (VDD - VSS) OFF • Observe tL > tH. • When tL < tH, an irregular display may occur. For tL, make the power (VDD - VSS) falling characteristics longer or consider any other method. tH is determined according to the external capacity C2 (smoothing capacity of V5 to V1) and the driver’s discharging capacity. Power Off Reset tL VDD 1.8V RES VDD SEG Since the power (VDD-VSS) is cut off,the output comes not be fixed. VDD COM About 1V:below Vth of the LCD Panel V1 V2 V3 V4 V5 tH <Reference Data> V5 voltage falling (discharge) time (tH) after the process of operation → power save → reset. V5 voltage falling (discharge) time (tH) after the process of operation → reset. 100 V5 voltage falling time (mSec) VDD-VSS(V) 1.8 2.4 50 3.0 4.0 5.0 0 0.5 1.0 C2 : V1 to V5 capacity (uF) Figure 31 Ver 0.6c 57/72 2009/09/07 ST7565S ABSOLUTE MAXIMUM RATINGS Unless otherwise noted, VSS = 0V Table 17 Parameter Symbol Conditions Unit Power Supply Voltage VDD –0.3 ~ +5.0 V Power supply voltage (VDD standard) VSS2 –4.0 ~ -1.8 V Power supply voltage (VDD standard) V5, VOUT –18.0 ~ +0.3 V Power supply voltage (VDD standard) V1, V2, V3, V4 V5 to +0.3 V Input voltage VIN –0.3 to VDD + 0.3 V Output voltage VO –0.3 to VDD + 0.3 V TOPR –40 to +85 °C TSTR –55 to +100 –55 to +125 °C Operating temperature Storage temperature TCP Bare chip VCC VDD GND VSS VDD VSS2,V1 to V4 V5.,VOUT System (MPU) side ST7565S chip side Figure 30 Notes and Cautions 1. The VSS2, V1 to V5 and VOUT are relative to the VDD = 0V reference. 2. Insure that the voltage levels of V1, V2, V3, and V4 are always such that VDD ≧ V1 ≧ V2 ≧ V3 ≧ V4 ≧ V5. 3. Permanent damage to the LSI may result if the LSI is used outside of the absolute maximum ratings. Moreover, it is recommended that in normal operation the chip be used at the electrical characteristic conditions, and use of the LSI outside of these conditions may not only result in malfunctions of the LSI, but may have a negative impact on the LSI reliability as well. Ver 0.6c 58/72 2009/09/07 ST7565S DC CHARACTERISTICS Unless otherwise specified, VSS = 0 V, VDD = 3.0 V ± 10%, Ta = –40 to 85°C Table 18 Item Symbol Operating Voltage (1) Vss Operating Voltage (2) VSS2 Operating Voltage (3) VSS2 Condition (Relative to VDD) (Relative to VDD) Units Applicable Pin -1.8 V Vss*1 — –1.8 V VSS2 –13.0 — –4.0 0.4 x V5 — VDD V5 — 0.6 x V5 Min. Rating Typ. Max. -3.3 — –3.3 V5 *2 V V1, V2 V3, V4 High-level Input Voltage VIHC 0.8 x VDD — VDD V *3 Low-level Input Voltage VILC VSS — 0.2 x VDD V *3 0.8 x VDD — VDD V *4 IOL = 0.5 mA VSS — 0.2 x VDD V *4 High-level Output Voltage VOHC IOH = –0.5 mA Low-level Output Voltage VOLC Input leakage current ILI VIN = VDD or VSS –1.0 — 1.0 μA *5 Output leakage current ILO VIN = VDD or VSS –3.0 — 3.0 μA *6 Liquid Crystal Driver ON Resistance RON Ta = 25°C V5 = –13.0 V (Relative To VDD) V5 = –8.0 V — 2.0 3.5 KΩ — 3.2 5.4 SEGn COMn *7 Static Consumption Current ISSQ — 0.01 2 μA VSS, VSS2 Output Leakage Current I5Q — 0.01 10 μA V5 Input Terminal Capacitance CIN — 5.0 8.0 pF 17 20 24 kHz *8 17 20 24 kHz CL 25 30 35 kHz *8 25 30 35 kHz CL Oscillator Frequency Ver 0.6c Internal Oscillator External Input Internal Oscillator External Input fOSC fCL fOSC fCL V5 = –13.0 V(Relative To VDD) Ta = 25°C , f = 1 MHz 1/65 duty 1/33 duty Ta = 25°C 1/49 duty 1/53 duty 1/55 duty Ta = 25°C 59/72 2009/09/07 ST7565S Table 19 Item Symbol Internal Power Input voltage VSS2 Condition (Relative To VDD) Supply Step-up output VOUT (Relative To VDD) voltage Circuit Voltage regulator Circuit Operating VOUT (Relative To VDD) Voltage Voltage Follower Circuit Operating V5 (Relative To VDD) Voltage Base Voltage VRS Rating Typ. Min. Ta = 25°C , (Relative To V DD) –0.05%/°C Max. Units Applicable Pin –3.3 — –1.8 V VSS2 –16.0 — — V VOUT –16.0 — –6.0 V VOUT –13.0 — –4.0 V V5 * 9 –2.07 –2.10 –2.13 V *10 Dynamic Consumption Current : During Display, with the Internal Power Supply OFF Current consumed by total ICs when an external power supply is used . Table 20 Rating Test pattern Symbol Condition Units Notes Min. Typ. Max. Display Pattern OFF IDD VDD = 3.0 V, V5 – VDD = –11.0 V — 16 27 μA *11 Display Pattern Checker IDD VDD = 3.0 V, V5 – VDD = –11.0 V — 19 32 μA *11 Dynamic Consumption Current : During Display, with the Internal Power Supply ON Table 21 Test pattern Symbol Display Pattern OFF IDD Display Pattern Checker IDD Min. Rating Typ. Max. Normal Mode — 60 100 High-Power Mode — 98 163 Normal Mode — 70 117 High-Power Mode — 105 175 Condition VDD = 3.0 V, Quad step-up voltage. V5 – VDD = –11.0 V VDD = 3.0 V, Quad step-up voltage. V5 – VDD = –11.0 V Units Notes μA *12 μA *12 Consumption Current at Time of Power Saver Mode : VSS = -3.0 V ± 10% Table 22 Rating Typ. 0.1 Max. 4 Ta = 25°C — 5 10 Symbol Condition Sleep mode IDD IDD Standby Mode Ver 0.6c Ta = 25°C Min. — Item 60/72 Units Notes μA 2009/09/07 ST7565S • The Relationship Between Oscillator Frequency fOSC, Display Clock Frequency fCL and the Liquid Crystal Frame Rate Frequency fFR Table 23 Item fCL fFR Used internal oscillator circuit fOSC / 4 fOSC / (4*65) Used external display clock External input (fCL) fCL / 260 Used internal oscillator circuit fOSC / 4 fOSC / (4*49) Used external display clock External input (fCL) fCL / 196 Used internal oscillator circuit fOSC / 8 fOSC / (8*33) Used external display clock External input (fCL) fCL / 264 Used internal oscillator circuit fOSC / 4 fOSC / (4*55) Used external display clock External input (fCL) fCL / 220 Used internal oscillator circuit fOSC / 4 fOSC / (4*53) Used external display clock External input (fCL) fCL / 212 1/65 DUTY 1/49 DUTY 1/33 DUTY 1/55 DUTY 1/53 DUTY (fFR is the liquid crystal alternating current period, and not the FR signal period.) References for items market with * *1 While a broad range of operating voltages is guaranteed, performance cannot be guaranteed if there are sudden fluctuations to the voltage while the MPU is being accessed. *2 The operating voltage range for the VDD system and the V5 system is. This applies when the external power supply is being used. *3 The A0, D0 to D5, D6 (SCL), D7 (SI), /RD (E), /WR (R/W), /CS1, CS2, CLS, CL, FR, M/S, C86, P/S, /DOF, /RES, IRS, and /HPM terminals. *4 The D0 to D7, FR, FRS, /DOF, and CL terminals. *5 The A0, /RD (E), /WR (R/W), /CS1, CS2, CLS, M/S, C86, P/S, /RES, IRS, and /HPM terminals. *6 Applies when the D0 to D5, D6 (SCL), D7 (SI), CL, FR, and /DOF terminals are in a high impedance state. *7 These are the resistance values for when a 0.1 V voltage is applied between the output terminal SEGn or COMn and the various power supply terminals (V 1 , V 2 , V 3 , and V 4 ). These are specified for the operating voltage (3) range. RON = 0.1 V /ΔI (Where ΔI is the current that flows when 0.1 V is applied while the power supply is ON.) *8 See Table 23 for the relationship between the oscillator frequency and the frame rate frequency. *9 The V5 voltage regulator circuit regulates within the operating voltage range of the voltage follower. *10 This is the internal voltage reference supply for the V5 voltage regulator circuit. In the ST7565S , the temperature range approximately –0.05%/°C. *11, 12 It indicates the current consumed on ICs alone when the internal oscillator circuit and display are turned on. The ST7565S is 1/9 biased. Does not include the current due to the LCD panel capacity and wiring capacity. Applicable only when there is no access from the MPU. *12 It is the value on a ST7565S having the VREG temperature gradient is –0.05%/°C when the V 5 voltage regulator internal resistor is used. Ver 0.6c 61/72 2009/09/07 ST7565S TIMING CHARACTERISTICS System Bus Read/Write Characteristics 1 (For the 8080 Series MPU) A0 tAW8 tAH8 CS1 (CS2="1") tCYC8 tCCLR,tCCLW WR,RD tCCHR,tCCHW tDS8 tDH8 D0 to D7 (Write) tACC8 tOH8 D0 to D7 (Read) Figure 37 Table 24 Item Signal Symbol Condition (VDD = 3.3V , Ta =25°C) Rating Units Min. Max. tAH8 0 — tAW8 0 — tCYC8 240 — tCCLW 80 — tCCHW 80 — tCCLR 140 — Enable H pulse width (READ) tCCHR 80 WRITE Data setup time tDS8 40 — tDH8 10 — Address hold time Address setup time A0 System cycle time Enable L pulse width (WRITE) WR Enable H pulse width (WRITE) Enable L pulse width (READ) WRITE Address hold time RD D0 to D7 READ access time tACC8 CL = 100 pF — 70 READ Output disable time tOH8 CL = 100 pF 5 50 Ver 0.6c 62/72 Ns 2009/09/07 ST7565S Table 25 Item Signal Symbol Condition (VDD = 2.7 V , Ta = 25°C ) Rating Units Min. Max. tAH8 0 — tAW8 0 — tCYC8 400 — tCCLW 220 — tCCHW 180 — tCCLR 220 — Enable H pulse width (READ) tCCHR 180 — WRITE Data setup time tDS8 40 — tDH8 15 — Address hold time Address setup time A0 System cycle time Enable L pulse width (WRITE) WR Enable H pulse width (WRITE) Enable L pulse width (READ) WRITE Address hold time RD D0 to D7 READ access time tACC8 CL = 100 pF — 140 READ Output disable time tOH8 CL = 100 pF 10 100 ns Table 26 Item Signal Symbol Condition (VDD = 1.8V , Ta = 25°C ) Rating Units Min. Max. tAH8 0 — tAW8 0 — tCYC8 640 — tCCLW 360 — tCCHW 280 — tCCLR 360 — Enable H pulse width (READ) tCCHR 280 WRITE Data setup time tDS8 80 — tDH8 30 — Address hold time Address setup time A0 System cycle time Enable L pulse width (WRITE) WR Enable H pulse width (WRITE) Enable L pulse width (READ) WRITE Address hold time RD D0 to D7 READ access time tACC8 CL = 100 pF — 240 READ Output disable time tOH8 CL = 100 pF 10 200 ns *1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr +tf) ≦ (tCYC8 – tCCLW – tCCHW ) for (tr + tf) ≦ (tCYC8 – tCCLR – tCCHR) are specified. *2 All timing is specified using 20% and 80% of VDD as the reference. *3 tCCLW and tCCLR are specified as the overlap between /CS1 being “L” (CS2 = “H”) and /WR and /RD being at the “L” level. Ver 0.6c 63/72 2009/09/07 ST7565S A0 R/W tAW6 tAH6 CS1 (CS2="1") tCYC6 tCCLR,tCCLW E tCCHR,tCCHW tDH6 tDS6 D0 to D7 (Write) tACC6 tOH6 D0 to D7 (Read) System Bus Read/Write Characteristics 2 (For the 6800 Series MPU) Figure 38 Table 27 Item Signal Symbol Condition (VDD = 3.3 V , Ta = 25°C ) Rating Units Min. Max. tAH6 0 — tAW6 0 — tCYC6 240 — tEWLW 80 — tEWHW 80 — tEWLR 80 — Enable H pulse width (READ) tEWHR 140 WRITE Data setup time tDS6 40 — tDH6 10 — Address hold time Address setup time A0 System cycle time Enable L pulse width (WRITE) WR Enable H pulse width (WRITE) Enable L pulse width (READ) WRITE Address hold time RD D0 to D7 READ access time tACC6 CL = 100 pF — 70 READ Output disable time tOH6 CL = 100 pF 5 50 Ver 0.6c 64/72 ns 2009/09/07 ST7565S Table 28 Item Signal Symbol Condition (VDD = 2.7V , Ta =25°C ) Rating Units Min. Max. tAH6 0 — tAW6 0 — tCYC6 400 — tEWLW 220 — tEWHW 180 — tEWLR 220 — Enable H pulse width (READ) tEWHR 180 — WRITE Data setup time tDS6 40 — tDH6 15 — Address hold time Address setup time A0 System cycle time Enable L pulse width (WRITE) WR Enable H pulse width (WRITE) Enable L pulse width (READ) WRITE Address hold time RD D0 to D7 READ access time tACC6 CL = 100 pF — 140 READ Output disable time tOH6 CL = 100 pF 10 100 ns Table 29 Item Signal Symbol Condition (VDD =1.8V , Ta =25°C ) Rating Units Min. Max. tAH6 0 — tAW6 0 — tCYC6 640 — tEWLW 360 — tEWHW 280 — tEWLR 360 — Enable H pulse width (READ) tEWHR 280 — WRITE Data setup time tDS6 80 — tDH6 30 — Address hold time Address setup time A0 System cycle time Enable L pulse width (WRITE) WR Enable H pulse width (WRITE) Enable L pulse width (READ) WRITE Address hold time RD D0 to D7 READ access time tACC6 CL = 100 pF — 240 READ Output disable time tOH6 CL = 100 pF 10 200 ns *1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr +tf) ≦ (tCYC6 – tEWLW – tEWHW ) for (tr + tf) ≦ (tCYC6 – tEWLR – tEWHR) are specified. *2 All timing is specified using 20% and 80% of VDD as the reference. *3 tEWLW and tEWLR are specified as the overlap between CS1 being “L” (CS2 = “H”) and E. Ver 0.6c 65/72 2009/09/07 ST7565S The Serial Interface tCCSS tCSH CS1 (CS2="1") tSAS tSAH A0 tSCYC tSLW SCL tSHW tf tr tSDS tSDH SI Figure 39 Table 30 Item Signal Serial Clock Period SCL “H” pulse width SCL SCL “L” pulse width Address setup time Address hold time Data setup time A0 SI Data hold time CS-SCL time CS CS-SCL time Symbol Condition Tscyc Tshw TSLW TSAS Tsah Tsds TSDH Tcss Tcsh (VDD = 3.3V, Ta =25°C ) Rating Units Min. Max. 50 — 25 — 25 — 20 — 10 — 20 — 10 — 20 — 40 — ns Table 31 Item Signal Serial Clock Period SCL “H” pulse width SCL SCL “L” pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time CS-SCL time Ver 0.6c A0 SI CS Symbol Tscyc TSHW TSLW TSAS TSAH TSDS TSDH TCSS TCSH 66/72 Condition (VDD =2.7V , Ta =25°C ) Rating Units Min. Max. 100 — 50 — 50 — 30 — 20 — 30 — 20 — 30 — 60 — ns 2009/09/07 ST7565S Table 32 Item Signal Serial Clock Period SCL “H” pulse width SCL SCL “L” pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time CS-SCL time A0 SI CS Symbol TSCYC TSHW TSLW TSAS TSAH TSDS TSDH TCSS TCSH Condition (VDD = 1.8V , Ta = 25°C ) Rating Units Min. Max. 200 — 80 — 80 — 60 — 30 — 60 — 30 — 40 — 100 — ns *1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less. *2 All timing is specified using 20% and 80% of VDD as the standard. Ver 0.6c 67/72 2009/09/07 ST7565S Reset Timing tRW RES tR Internal status During reset Reset complete Figure 41 Table 36 Item Reset time Reset “L” pulse width Signal /RES Symbol Condition tR tRW (VDD = 3.3V , Ta = –40 to 85°C ) Rating Units Min. Typ. Max. — — 0.5 us 0.5 — — us Table 37 Item Reset time Reset “L” pulse width Signal /RES Symbol Condition tR tRW (VDD = 2.7V , Ta = –40 to 85°C ) Rating Units Min. Typ. Max. — — 1 us 1 — — us Table 38 Item Reset time Reset “L” pulse width Signal /RES Symbol Condition tR tRW (VDD = 1.8V , Ta = –40 to 85°C ) Rating Units Min. Typ. Max. — — 1.5 us 1.5 — — us *1 All timing is specified with 20% and 80% of VDD as the standard. Ver 0.6c 68/72 2009/09/07 ST7565S THE MPU INTERFACE (REFERENCE EXAMPLES) The ST7565S Series can be connected to either 80X86 Series MPUs or to 68000 Series MPUs. Moreover, using the serial interface it is possible to operate the ST7565S series chips with fewer signal lines. The display area can be enlarged by using multiple ST7565S Series chips. When this is done, the chip select signal can be used to select the individual ICs to access. (1) 8080 Series MPUs VDD VCC A1 to A7 IORQ CS1 CS2 Decoder DO to D7 RD WR RES GND VDD C86 A0 ST7565S MPU A0 DO to D7 RD WR RES P/S VSS RESET VSS Figure 42-1 (2) 6800 Series MPUs VDD VCC A1 to A15 VMA CS1 CS2 Decoder DO to D7 E R/W RES GND VDD C86 A0 ST7565S MPU A0 DO to D7 E R/W RES P/S VSS RESET VSS Figure 42-2 (3) Using the Serial Interface VDD or VSS VCC A0 Port 1 Port 2 RES GND VDD C86 ST7565S CS1 CS2 Decoder MPU A1 to A7 A0 SI SCL RES P/S VSS RESET VSS Figure 42-3 Ver 0.6c 69/72 2009/09/07 ST7565S CONNECTIONS EXAMPLE) BETWEEN LCD DRI V E RS (REFERENCE The liquid crystal display area can be enlarged with ease through the use of multiple ST7565S Series chips. Use a same equipment type. (1) ST7565S (master) ↔ ST7565S (slave) VDD CLS CLS FR FR ST7565S Master M/S CL CL DOF DOF Output ST7565S Slave M/S Input VSS VDD CLS CLS FR FR ST7565S Master M/S CL CL DOF DOF Output Input ST7565S Slave M/S VSS Figure 43-1 Ver 0.6c 70/72 2009/09/07 ST7565S (2) Single-chip Structure 132 X 65 Dots ST7565S Master Figure 43-2 (3) Double-chip Structure 264 x 65 Dots COM SEG SEG ST7565S Master COM ST7565S Slave Figure 43-3 Ver 0.6c 71/72 2009/09/07 ST7565S Revisions Version Description 0.1 Preliminary. 0.2 update Pad Center Coordinates page 2,3,4,5 0.2a update ABSOLUTE MAXIMUM RATINGS and DC CHARACTERISTICS 0.2b update DC CHARACTERISTICS , Pad Arrangement 0.2c update AC CHARACTERISTICS (serial) 0.2d update PIN DESCRIPTIONS M/S 0.2e update ABSOLUTE MAXIMUM RATINGS and DC CHARACTERISTICS 0.2f update Master and Slave reference example. 0.3 update Pad Center Coordinates (1/65 , 1/49 , 1/33 , 1/55 , 1/53 Duty) page 3..17 0.3a update Pad Diagram page2 and v5 regulator voltage diagram(figure 9) page35 0.3b Logic power supply VDD – VSS = 1.8V to 3.3 V (+10% Range), VOUT= -13V (+10% Range) 0.3c Modify page-38 The temperature grade of the Internal Power Supply for ST7565S (-0.05%/°C) Figure 14 0.4 Delete recommended to connect an external resistor to stabilize potentials of V1, V2, V3 and V4 0.5 Modify Tdh (data hold time) and page53,54 initial flow 0.6a Solve Font issue. Fix Page 2 values. Redraw some figures. Rewrite some description for easy understanding. Fix Word problems. 0.6b Modify mistake if Status Read. 0.6c Add I/O Pin ITO Resister Limitation. Modify the mistake of The Reset Circuit. Ver 0.6c 72/72 2009/09/07