A3948 DMOS Full-Bridge PWM Motor Driver Discontinued Product These parts are no longer in production The device should not be purchased for new design applications. Samples are no longer available. Date of status change: April 28, 2007 Recommended Substitutions: NOTE: For detailed information on purchasing options, contact your local Allegro field applications engineer or sales representative. Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use. Data Sheet 29319.36A 3948 DMOS FULL-BRIDGE PWM MOTOR DRIVER CP2 2 CP1 3 PHASE 4 OSC 5 GROUND 6 GROUND 7 LOGIC SUPPLY 8 ENABLE 99 DATA 10 CLOCK 11 STROBE 12 NC θ VBB LOGIC 1 V DD SERIAL PORT CP CHARGE PUMP A3948SLB (SOIC) NC ÷ 24 VREG 23 RANGE 22 NO CONNECTION 21 OUTB 20 LOAD SUPPLY 19 GROUND 18 GROUND 17 SENSE 16 OUTA 15 NO CONNECTION 14 MODE 13 REF Dwg. PP-069A Note that the A3948SLB(SOIC) and A3948SB (DIP) do not share a common terminal assignment. ABSOLUTE MAXIMUM RATINGS Load Supply Voltage, VBB .................. 50 V Output Current, IOUT ........................ ±1.5 A Logic Supply Voltage, VDD ................ 7.0 V Input Voltage, VIN .... -0.3 V to VDD + 0.3 V Sense Voltage, VS .......................... 0.55 V Reference Voltage, VREF .................. 5.5 V Package Power Dissipation (TA = 25°C), PD A3948SB ................................. 3.1 W* A3948SLB ............................... 1.6 W* Operating Temperature Range, TA ............................... -20°C to +85°C Junction Temperature, TJ ............................................ +150°C Storage Temperature Range, TS ............................. -55°C to +150°C Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150°C. * Per SEMI G42-88 Specification. Designed for pulse-width modulated (PWM) current control of dc motors, the A3948SB and A3948SLB are capable of continuous output currents to ±1.5 A and operating voltages to 50 V. Internal fixed offtime PWM current-control timing circuitry can be programmed via a serial interface to operate in slow, fast, and mixed current-decay modes. Similar devices with outputs rated to ±2 A are available as the A3958SB/SLB. PHASE and ENABLE input terminals are provided for use in controlling the speed and direction of a dc motor with externally applied PWM-control signals. The ENABLE input can be programmed via the serial port to PWM the bridge in fast or slow current decay. Internal synchronous rectification control circuitry is provided to reduce power dissipation during PWM operation. Internal circuit protection includes thermal shutdown with hysteresis, and crossover-current protection. Special power-up sequencing is not required. The A3948SB/SLB is supplied in a choice of two power packages, a 24-pin plastic DIP with a copper batwing tab (package suffix ‘B’), and a 24-lead plastic SOIC with a copper batwing tab (package suffix ‘LB’). In both cases, the power tab is at ground potential and needs no electrical isolation. FEATURES ■ ■ ■ ■ ■ ■ ■ ±1.5 A, 50 V Continuous Output Rating Low rDS(on) Outputs Programmable Mixed, Fast, and Slow Current-Decay Modes Serial Interface Controls Chip Functions Synchronous Rectification for Low Power Dissipation Internal UVLO and Thermal-Shutdown Circuitry Crossover-Current Protection Always order by complete part number: Part Number Package RθJA RθJT A3948SB 24-pin batwing DIP 40°C/W 6°C/W A3948SLB 24-lead batwing SOIC 77°C/W 6°C/W 3948 DMOS FULL-BRIDGE PWM MOTOR DRIVER FUNCTIONAL BLOCK DIAGRAM VBB VDD CHARGE PUMP BANDGAP VDD CREG TSD LOAD SUPPLY CP CP1 CP2 + LOGIC SUPPLY CHARGE PUMP UNDERVOLTAGE & FAULT DETECT BANDGAP REGULATOR VREG CONTROL LOGIC PHASE ENABLE SYNC RECT MODE SYNC RECT DISABLE PWM MODE INT PWM MODE EXT MODE PHASE ENABLE OSC GATE DRIVE OUTA SENSE CS ZERO CURRENT DETECT FIXED OFF PROGRAMMABLE BLANK DECAY PWM TIMER CLOCK DATA STROBE OUTB SLEEP MODE SERIAL PORT CURRENT SENSE RANGE RS REFERENCE BUFFER & DIVIDER REF VREF RANGE Dwg. FP-048 1 24 CP CP1 2 23 VREG PHASE 3 22 RANGE OSC 4 21 OUTB GROUND 5 20 LOAD SUPPLY GROUND 6 19 GROUND GROUND 7 18 GROUND GROUND 8 17 SENSE LOGIC SUPPLY 99 16 OUTA ENABLE 10 15 MODE DATA 11 14 REF CLOCK 12 13 STROBE CHARGE PUMP θ VBB LOGIC CP2 V DD ÷ SERIAL PORT A3948SB (DIP) Note that the A3948SLB (SOIC) and A3948SB (DIP) do not share a common terminal assignment. Dwg. PP-069-1A 2 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 2001, 2002 Allegro MicroSystems, Inc. 3948 DMOS FULL-BRIDGE PWM MOTOR DRIVER ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 50 V, VDD = 5.0 V, VSENSE = 0.5 V, fPWM < 50 kHz (unless noted otherwise) Limits Characteristics Symbol Test Conditions Min. Typ. Max. Units Output Drivers Load Supply Voltage Range Output Leakage Current Output On Resistance Body Diode Forward Voltage Load Supply Current VBB IDSS rDS(on) VF IBB Operating 20 – 50 V During sleep mode 0 – 50 V VOUT = VBB – <1.0 20 µA VOUT = 0 V – <-1.0 -20 µA Source driver, IOUT = -1.5 A – 500 550 mΩ Sink driver, IOUT = 1.5 A – 300 350 mΩ Source diode, IF = -1.5 A – 1.0 1.3 V Sink diode, IF = 1.5 A – 1.0 1.3 V fPWM < 50 kHz – 4.0 7.0 mA Charge pump on, outputs disabled – 2.0 5.0 mA Sleep Mode – – 20 µA 4.5 5.0 5.5 V Control Logic Logic Supply Voltage Range VDD Operating Logic Input Voltage VIN(1) 2.0 – – V VIN(0) – – 0.8 V Logic Input Current (all inputs except ENABLE) IIN(1) VIN = 2.0 V – <1.0 20 µA IIN(0) VIN = 0.8 V – <-2.0 -20 µA ENABLE Input Current IIN(1) VIN = 2.0 V – 40 100 µA IIN(0) VIN = 0.8 V – 16 40 µA OSC input frequency fOSC Operating 1.8 – 6.1 MHz OSC input duty cycle dcOSC Operating 40 – 60 % OSC input hysteresis – Operating 200 – 400 mV Input Hysterisis – All digital inputs except OSC 50 – 100 mV 0.0 – VDD - 0.1 V Reference Input Volt. Range VREF Operating Reference Input Current IREF VREF = 2.5 V – – ±0.5 µA Comparator Input Offset Volt. VIO VREF = 0 V – 0 ±5.0 mV Continued next page … www.allegromicro.com 3 3948 DMOS FULL-BRIDGE PWM MOTOR DRIVER ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 50 V, VDD = 5.0 V, VSENSE = 0.5 V, fPWM < 50 kHz (unless noted otherwise), continued. Limits Characteristics Symbol Test Conditions Min. Typ. Max. Units Control Logic – 0 ±15 mV D14 = High 9.9 10 10.2 – D14 = Low 4.95 5.0 5.05 – PWM change to source ON – 600 – ns PWM change to source OFF – 100 – ns PWM change to sink ON – 600 – ns PWM change to sink OFF – 100 – ns Phase change to sink ON – 600 – ns Phase change to sink OFF – 100 – ns Phase change to source ON – 600 – ns Phase change to source OFF – 100 – ns TJ – 165 – °C ∆TJ – 15 – °C 3.90 4.2 4.45 V 0.05 0.10 – V fPWM < 50 kHz – 6.0 10 mA Sleep Mode, Inputs < 0.5 V – – 2.0 mA Buffer Input Offset Volt. VIO Reference Divider Ratio – Propagation Delay Times Thermal Shutdown Temp. Thermal Shutdown Hysteresis UVLO Enable Threshold UVLO Hysteresis Logic Supply Current tpd UVLO Increasing VDD ∆UVLO IDD NOTES: 1. Typical Data is for design information only. 2. Negative current is defined as coming out of (sourcing) the specified device terminal. 4 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 3948 DMOS FULL-BRIDGE PWM MOTOR DRIVER FUNCTIONAL DESCRIPTION Serial Interface. The A3948 is controlled via a 3-wire (clock, data, strobe) serial port. The programmable functions allow maximum flexibility in configuring the PWM to the motor drive requirements. The serial data is clocked in starting with D19. Bit D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 Function Blank Time LSB Blank Time MSB Off Time LSB Off Time Bit 1 Off Time Bit 2 Off Time Bit 3 Off Time MSB Fast Decay Time LSB Fast Decay Time Bit 1 Fast Decay Time Bit 2 Fast Decay Time MSB Sync. Rect. Mode Sync. Rect. Enable External PWM Mode Enable Phase Reference Range Select Internal PWM Mode Test Use Only Sleep Mode D0 – D1 Blank Time. The current-sense comparator is blanked when any output driver is switched on, according to the table below. fosc is the oscillator input frequency. D1 0 0 1 1 D0 0 1 0 1 Blank Time 4/fosc 6/fosc 12/fosc 24/fosc D2 – D6 Fixed-Off Time. A five-bit word sets the fixed-off time for internal PWM current control. The off time is defined by toff = (8[1 + N]/fosc) - 1/fosc where N = 0 … 31 For example, with an oscillator frequency of 4 MHz, the off time will be adjustable from 1.75 µs to 63.75 µs in increments of 2 µs. www.allegromicro.com D7 – D10 Fast Decay Time. A four-bit word sets the fast-decay portion of the fixed-off time for the internal PWM control circuitry. This will only have impact if the mixed-decay mode is selected (via bit D17 and the MODE input terminal). For tfd > toff, the device will effectively operate in the fast-decay mode. The fast decay portion is defined by tfd = (8[1 + N]/fosc) - 1/fosc where N = 0 … 15 For example, with an oscillator frequency of 4 MHz, the fast decay time will be adjustable from 1.75 µs to 31.75 µs in increments of 2 µs. D11 Synchronous Rectification Mode. The active mode prevents reversal of load current by turning off synchronous rectification when a zero current level is detected. The passive mode will allow reversal of current but will turn off the synchronous rectifier circuit if the load current inversion ramps up to the current limit set by VREF/RS. D11 0 1 Mode Active Passive D12 Synchronous Rectification Enable. D12 0 1 Synchronous Rect. Disabled Enabled D13 External PWM Decay Mode. Bit D13 determines the current-decay mode when using ENABLE chopping for external PWM current control. D13 0 1 Mode Fast Slow D14 Enable Logic. Bit D14, in conjunction with ENABLE, determines if the output drivers are in the chopped (OFF)(ENABLE = D14) or ON (ENABLE ≠ D14) state. ENABLE 0 1 0 1 D14 0 0 1 1 Mode Chopped On On Chopped 5 3948 DMOS FULL-BRIDGE PWM MOTOR DRIVER FUNCTIONAL DESCRIPTION (continued) D15 Phase Logic. Bit D15, in conjunction with PHASE, determines if the device is operating in the forward (PHASE ≠ D15) or reverse (PHASE = D15) state. PHASE D15 State 0 0 Reverse 1 0 Forward 0 1 Forward 1 1 Reverse OUTA OUTB Low High High Low High Low Low High D19 Sleep Mode. Bit D19 selects a Sleep mode to minimize power consumption when not in use. This disables much of the internal circuitry including the regulator and charge pump. On power up the serial port is initialized to all 0s. Bit D19 should be programmed high for 1 ms before attempting to enable any output driver. D16 Gm Range Select. Bit D16, in conjunction with RANGE, determines if VREF is divided by 5 (RANGE ≠ D16) or by 10 (RANGE = D16). RANGE 0 1 0 1 D16 0 0 1 1 D19 0 1 Divider ÷10 ÷5 ÷5 ÷10 D17 Internal PWM Mode. Bit D17, in conjunction with MODE, selects slow (MODE ≠ D17) or mixed (MODE = D17) current decay. MODE D17 0 0 1 0 0 1 1 1 D18 Test Mode. Bit D18 low (default) operates the device in normal mode. D18 is only used for testing purposes. The user should never change this bit. Current-Decay Mode Mixed Slow Slow Mixed Sleep Mode Sleep Normal Serial Port Write Timing Operation. Data is clocked into the shift register on the rising edge of the CLOCK signal. Normally STROBE will be held high, only brought low to initiate a write cycle. Refer to diagram below and these specifications for the minimum timing requirements. A.DATA setup time ......................................... 15 ns B.DATA hold time ........................................... 10 ns C.Setup STROBE to CLOCK rising edge ....... 50 ns D.CLOCK high pulse width ............................ 50 ns E.CLOCK low pulse width .............................. 50 ns F.Setup CLOCK rising edge to STROBE ....... 50 ns G.STROBE pulse width ................................... 50 ns Serial Port Write Timing STROBE C D E F G CLOCK A DATA B D19 D18 D0 Dwg. WP-038 6 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 3948 DMOS FULL-BRIDGE PWM MOTOR DRIVER FUNCTIONAL DESCRIPTION (continued) VREG. This internally generated voltage is used to operate the sink-side DMOS outputs. The VREG terminal should be decoupled with a 0.22 µF capacitor to ground. VREG is internally monitored and in the case of a fault condition, the outputs of the device are disabled. Charge Pump. The charge pump is used to generate a gate-supply voltage greater than VBB to drive the sourceside DMOS gates. A 0.22 µF ceramic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.22 µF ceramic capacitor should be connected between CP and VBB to act as a reservoir to operate the high-side DMOS devices. The CP voltage is internally monitored and, in the case of a fault condition, the source outputs of the device are disabled. Shutdown. In the event of a fault (excessive junction temperature, or low voltage on CP or VREG) the outputs of the device are disabled until the fault condition is removed. At power up, or in the event of low VDD, the UVLO circuit disables the drivers and resets the data in the serial port to all zeros. A watchdog circuit will also reset the data in the absence of an OSC signal. PWM Timer Function. The PWM timer is programmable via the serial port (bits D2 – D10) to provide off-time PWM signals to the control circuitry. In the mixed current-decay mode, the first portion of the off time operates in fast decay, until the fast decay time count (serial bits D7 – D10) is reached, followed by slow decay for the rest of the off-time period (bits D2 – D6). If the fast decay time is set longer than the off time, the device effectively operates in fast decay mode. Bit D17, in conjunction with MODE, selects mixed or slow decay. PWM Blank Timer. When a source driver turns on, a current spike occurs due to the reverse recovery currents of the clamp diodes and/or switching transients related to distributed capacitance in the load. To prevent this current spike from erroneously resetting the source-enable latch, the sense comparator is blanked. The blank timer runs after the off-time counter (see bits D2 – D6) to provide the programmable blanking function. The blank timer is reset when ENABLE is chopped or PHASE is changed. For external PWM control, a PHASE change or ENABLE on will trigger the blanking function. www.allegromicro.com Synchronous Rectification. When a PWM off cycle is triggered, either by an ENABLE chop command or internal fixed off-time cycle, load current will recirculate according to the decay mode selected by the control logic. The A3948 synchronous rectification feature will turn on the opposite pair of DMOS outputs during the current decay and effectively short out the body diodes with the low rDS(on) driver. This will reduce power dissipation significantly and can eliminate the need for external Schottky diodes. Synchronous rectification can be configured in active mode, passive mode, or disabled via the serial port (bits D11 and D12). The active or passive mode selection has no impact in slow-decay mode. With synchronous rectification enabled, the slow-decay mode serves as an effective brake mode. Current Regulation. Load current is regulated by an internal fixed off-time PWM control circuit. When the outputs of the DMOS H bridge are turned on, the current increases in the motor winding until it reaches a trip value determined by the external sense resistor (RS), the applied analog reference voltage (VREF), the RANGE logic level, and serial data bit D16: When RANGE = D16 ........... ITRIP = VREF/10RS When RANGE ≠ D16 ............ ITRIP = VREF/5RS At the trip point, the sense comparator resets the sourceenable latch, turning off the source driver. The load inductance then causes the current to recirculate for the serial-port-programmed fixed off-time period. The current path during recirculation is determined by the configuration of slow/mixed current-decay mode (D17) and the synchronous rectification control bits (D11 and D12). Note that the sense voltage (VS) must not be greater than 0.55 V (absolute maximum rating). Therefore, if the reference divider is set to 5, VREF must not be greater than 2.75 V; if the reference divider is set to 10, VREF must not be greater than 5.5 V (absolute maximum rating). 7 3948 DMOS FULL-BRIDGE PWM MOTOR DRIVER APPLICATIONS INFORMATION Current Sensing. To minimize inaccuracies in sensing the ITRIP current level, which may be caused by ground trace IR drops, the sense resistor should have an independent ground return to the ground terminal of the device. For low-value sense resistors the IR drops in the PCB sense resistor’s traces can be significant and should be taken into account. The use of sockets should be avoided as they can introduce variation in RS due to their contact resistance. The maximum value of RS is given as RS ≤ 0.5/ITRIP. Braking. The braking function is implemented by driving the device in slow-decay mode via serial port bit D13, enabling synchronous rectification via bit D12, and chopping with the combination of D14 and the ENABLE input terminal. Because it is possible to drive current in either direction through the DMOS drivers, this configuration effectively shorts out the motor-generated BEMF as long as the ENABLE chop mode is asserted. It is important to note that the internal PWM current-control circuit will not limit the current when braking, because the current does not flow through the sense resistor. The maximum brake current can be approximated by VBEMF/ RL. Care should be taken to ensure that the maximum ratings of the device are not exceeded in worst-case braking situations of high speed and high inertial loads. Layout. The printed wiring board should use a heavy ground plane. For optimum electrical and thermal performance*, the driver should be soldered directly onto the board. The ground side of RS should have an individual path to the ground terminals of the device. This path should be as short as is possible physically and should not have any other components connected to it. It is recommended that a 0.1 µF capacitor be placed between SENSE and ground as close to the device as possible; the load supply terminal, VBB, should be decoupled with an electrolytic capacitor (> 47 µF is recommended) placed as close to the device as is possible. * The thermal resistance and absolute maximum allowable package power dissipation specified on page 1 is measured on typical two-sided PCB with minimal copper ground area. See also, Application Note 29501.5, Improving Batwing Power Dissipation. Thermal Protection. Circuitry turns off all drivers when the junction temperature reaches 165°C typically. It is intended only to protect the device from failures due to excessive junction temperatures and should not imply that output short circuits are permitted. Thermal shutdown has a hysteresis of approximately 15°C. 8 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 3948 DMOS FULL-BRIDGE PWM MOTOR DRIVER Terminal List Terminal Name CP Terminal Description Reservoir capacitor (typically 0.22 µF) A3948SLB (SOIC) A3948SB (DIP) 1 24 CP1 & CP2 The charge pump capacitor (typically 0.22 µF) 2&3 1&2 PHASE Logic input for direction control (see also D15) 4 3 Logic-level oscillator (square wave) input 5 4 6, 7 5, 6, 7, 8* VDD, the low voltage (typically 5 V) supply 8 9 Logic input for enable control (see also D14) 9 10 Logic-level input for serial interface 10 11 Logic input for serial port (data is entered on rising edge) 11 12 Logic input for serial port (active on rising edge) 12 13 VREF, the load current reference input volt. (see also D16) 13 14 Logic input for PWM mode control (see also D17) 14 15 No (Internal) Connection 15 — One of two DMOS bridge outputs to the motor 16 16 Sense resistor 17 17 18, 19 18, 19* VBB, the high-current, 20 V to 50 V, motor supply 20 20 One of two DMOS bridge outputs to the motor 21 21 No (Internal) connection 22 — RANGE Logic Input for VREF range control (see also D16) 23 22 VREG Regulator decoupling capacitor (typically 0.22 µF) 24 23 OSC GROUND LOGIC SUPPLY ENABLE DATA CLOCK STROBE REF MODE NO CONNECT OUTA SENSE GROUND LOAD SUPPLY OUTB NO CONNECT Grounds Grounds * For the A3948SB DIP only, there is an indeterminate resistance between the substrate grounds (pins 6, 7, 18, and 19) and the grounds at pins 5 and 8. Pins 5 and 8, and 6, 7, 18, or 19 must be connected together externally. www.allegromicro.com 9 3948 DMOS FULL-BRIDGE PWM MOTOR DRIVER A3948SB Dimensions in Inches (controlling dimensions) 24 0.014 0.008 13 NOTE 1 0.430 MAX 0.280 0.240 0.300 BSC 1 0.070 0.045 6 7 0.100 1.280 1.230 12 0.005 BSC MIN 0.210 MAX 0.015 0.150 0.115 MIN 0.022 0.014 Dwg. MA-001-25A in Dimensions in Millimeters (for reference only) 24 0.355 0.204 13 NOTE 1 10.92 MAX 7.11 6.10 7.62 BSC 1 1.77 1.15 6 7 2.54 32.51 31.24 12 BSC 0.13 MIN 5.33 MAX 0.39 3.81 2.93 MIN 0.558 0.356 NOTES: 1. 2. 3. 4. 5. 10 Dwg. MA-001-25A mm Webbed lead frame. Leads 6, 7, 18, and 19 are internally one piece. Exact body and lead configuration at vendor’s option within limits shown. Lead spacing tolerance is non-cumulative. Lead thickness is measured at seating plane or below. Supplied in standard sticks/tubes of 15 devices. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 3948 DMOS FULL-BRIDGE PWM MOTOR DRIVER A3948SLB Dimensions in Inches (for reference only) 24 13 0.0125 0.0091 0.419 0.394 0.2992 0.2914 0.050 0.016 0.020 0.013 1 2 3 0.050 0.6141 0.5985 BSC 0° TO 8° NOTE 1 NOTE 3 0.0926 0.1043 0.0040 MIN. Dwg. MA-008-25A in Dimensions in Millimeters (controlling dimensions) 24 13 0.32 0.23 10.65 10.00 7.60 7.40 1.27 0.40 0.51 0.33 1 2 3 15.60 15.20 1.27 BSC 0° TO 8° NOTE 1 NOTE 3 2.65 2.35 0.10 MIN. NOTES: 1. 2. 3. 4. Dwg. MA-008-25A mm Exact body and lead configuration at vendor’s option within limits shown. Lead spacing tolerance is non-cumulative. Webbed lead frame. Leads 6, 7, 18, and 19 are internally one piece. Supplied in standard sticks/tubes of 31 devices or add “TR” to part number for tape and reel. www.allegromicro.com 11 3948 DMOS FULL-BRIDGE PWM MOTOR DRIVER The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. 12 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000