LatticeSC PCI Express x4 Evaluation Board
User’s Guide
September 2009
Revision: EB31_01.2
LatticeSC PCI Express x4 Evaluation Board
User’s Guide
Lattice Semiconductor
Introduction
This user’s guide describes the LatticeSC PCI Express x4 Evaluation Board featuring the LatticeSC
LFSCM3GA80EP1-6FC1152C FPGA device. This stand-alone evaluation PCB provides a functional platform for
development and rapid prototyping of applications that require high-speed SERDES interfaces and/or PCI Express
protocols.
The evaluation board includes provisioning to connect high-speed SERDES channels via SMA connectors to test
and measurement equipment. The board is manufactured using standard FR4 dielectric and through-hole vias.
The nominal impedance is 50-ohm for single-ended traces and 100-ohm for differential traces.
The board has several debugging and analyzing features for complete user evaluation of the LatticeSC device. This
user’s guide is intended to be referenced in conjunction with evaluation design tutorials to demonstrate the LatticeSC FPGA.
Figure 1. LatticeSC PCI Express x4 Evaluation Board
PCI Express
Cable Connectors
SERDES I/O
LVDS I/O
DDR2
SDRAM
PCI Express x4
Edge
LatticeSC-80
1152 fpBGA
Test LEDs
Mictor Connector
for Logic Analyzer
Features
• LatticeSCM-80 device in 1152 fcBGA package
• SERDES interface to x4 PCI Express edge fingers
• Two x1 PCI Express cable connections
• DDR2 memory device
• SERDES high-speed interface SMA test points and clock connections
• Power connections and power sources
• ispVM® programming support
2
Clock I/O
Power
Supplies
LatticeSC PCI Express x4 Evaluation Board
User’s Guide
Lattice Semiconductor
• On-board and external reference clock sources
• Interchangeable clock oscillators
• ORCAstra demonstration software interface via standard ispVM JTAG connection
• Various high-speed layout structures
• User-defined input and output points
• SMA connectors included (10) for high-speed clock or data interfacing
• Performance monitoring via test headers, LEDs and switches
This user’s guide includes top-level functional descriptions of the various portions of the evaluation board, descriptions of the on-board connectors, diodes and switches and a complete set of schematics of the board. Figure 2
shows the functional partitioning of the board.
Additional Resources
For additional information and resources related to this board, including updated documentation and hardware/software demos, please see the Lattice web site at www.latticesemi.com/boards and navigate to the appropriate page for this board.
A PCI Express demonstration is also available on-line, including a GUI and drivers for a PCI Express solution using
this board.
Lattice makes its best effort to provide evaluation board designs to help users with evaluation and development.
However it remains the user's responsibility to verify proper and reliable operation of Lattice products in their end
application by consulting documentation provided by Lattice. Differences in component selection and/or PCB layout
in the user's application may significantly affect circuit performance and reliability.
Figure 2. Evaluation Board Block Diagram
PCI Express x1
Cable Connector
PCI Express Card
Edge Fingers
PCI Express x1
Cable Connector
LatticeSC
1152 fcBGA
PCI Express x4
DDR2
Memory
84 fBGA
LVDS
Bus Loop
LVDS SMAs
4-bit
Input/Output
LatticeSC Device
This board features a LatticeSC FPGA with a 1.2V core supply. It can accommodate all pin compatible LatticeSC
devices in the 1152-ball fpBGA (1mm pitch) package. A complete description of this device can be found in the LatticeSC/M Family Data Sheet.
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Note: The connections referenced in this document refer to the LFSCM3GA80 device. Available I/Os and associated sysIO™ banks may differ for other densities within this device family.
Applying Power to the Board
The LatticeSC PCI Express x4 Evaluation Board is ready to power on. The evaluation board can be supplied with
power from an AC wall-type transformer power supply shipped with the board. Or it can be supplied from a benchtop supply via terminal screw connections. It also has provisions to be supplied from the PCI Express edge fingers
from a host board.
To supply power from the factory-supplied wall transformer, simply connect the output connection of the power cord
to J3 and plug the wall transformer into an AC wall outlet.
Power Supplies
(see Appendix A, Figure 9)
The evaluation board incorporates an alternate scheme to provide power to the board. The board is equipped to
accept a main supply via the TB1 connection. This connection is provided to use with a bench-top supply adjusted
to provide a nominal 12V DC.
All input power sources and on-board power supplies are fused with surface mounted fuses and have green LEDs
to indicate power GOOD status of the intermediate supplies
Table 1. Board Power Supply Fuses- (see Appendix A, Figure 9)
F1
1.0V/1.2V Fuse
F2
3.3V Fuse
F3
1.5V Fuse
F4
1.2V Fuse
F5
2.5V Fuse
F6
1.8V Fuse
Table 2. Board Power Supply Indicators- (see Appendix A, Figure 9)
D14
1.0V/1.2V VCC Core Source Good Indicator
D15
1.5V Source Good Indicator
D16
1.8V Source Good Indicator
D12
2.5V Source Good Indicator
D13
3.3V Source Good Indicator
D17
1.2V Source Good Indicator
Alternatively, external power can be connected rather than the wall transformer power pack.
Table 3. Board Supply Disconnects- (see Appendix A, Figure 9)
TB1
Screw terminal for 12V DC Pin1(square PCB pad) -> +12V DC Pin2 -> Ground
PCI Express Power Interface
(see Appendix A, Figure 10)
Power can be sourced to the board via the PCB Edge Finger (CN1). This interface allows the user to provide power
from a PCI Express host board.
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Programming/FPGA Configuration
(see Appendix A, Figure 7)
A programming header is provided on the evaluation board, providing access to the LatticeSC JTAG port.
Note: An ispDOWNLOAD® Cable is included with each ispLEVER® design tool shipment. Cables may also be purchased separately from Lattice.
ispVM Download Interface
J2 is a10-pin JTAG connector used in conjunction with the ispVM System software and ispDOWNLOAD Cable to
program and control the device.
Table 4. JTAG Programming Connector (see Appendix A, Figure 7)
Pin 1
VCC
Pin 2
TDO
Pin 3
TDI
Pin 4
PROGRAMN
Pin 5
NC
Pin 6
TMS
Pin 7
GND
Pin 8
TCK
Pin 9
DONE
Pin 10
INITN
Programming Daisy Chain
This board includes two Lattice programmable devices that can be programmed in a daisy chain. A jumper setting
of J93 controls the chain. Both devices are in the programming chain from the JTAG header J2 with jumpers across
Pins{1-2} and Pins{3-4}. If the user desires to only program U1, only a jumper should be across Pins{2-4}.
Download Procedures
Requirements
• PC with ispVM System v.14.3 (or later) programming management software, installed with appropriate drivers
(USB driver for USB Cable, Windows NT/2000/XP parallel port driver for ispDOWNLOAD Cable). Note: An option
to install these drivers is included as part of the ispVM System set-up.
• ispDOWNLOAD Cable (HW-USBN-2A, HW-DLN-3C, etc.)
JTAG Download
The LatticeSC device can be configured easily via its JTAG port. The device is SRAM-based; it must remain powered on to retain its configuration when programmed in this fashion.
1. Connect the ispDOWNLOAD cable to the appropriate header. J2 is used for the 1x10 cable.
Important Note: The board must be un-powered when connecting, disconnecting, or reconnecting the ispDOWNLOAD Cable. Always connect the ispDOWNLOAD Cable's GND pin (black wire), before connecting any
other JTAG pins. Failure to follow these procedures can in result in damage to the LatticeSC FPGA device and
render the board inoperable.
2. Connect the LatticeSC Evaluation Board to the appropriate power sources and power up the board.
3. Start the ispVM System software.
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Lattice Semiconductor
4. Press the SCAN button located in the toolbar. The LatticeSC device should be automatically detected.
Figure 3. ispVM Main Window
5. Double-click the device to open the device information dialog. In the device information dialog, click the Browse
button located under Data File. Locate the desired bitstream file (.bit). Click OK to both dialog boxes.
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Figure 4. Device Information Dialog Box
6. Click the green GO button. This will begin the download process into the device. Upon successful download, the
device will be operational.
Configuration Status Indicators
(see Appendix A, Figure 7)
These LEDs indicate the status of configuration to the FPGA.
• D1 illuminated (red) – This indicates that the programming was aborted or reinitialized driving the INITN output
low.
• D4 illuminated (green) – This indicates the successful completion of configuration by releasing the open collector
DONE output pin.
• D11 illuminated (green) – Flashes to indicate TDI activity.
• D21 illuminated (red) – This indicates that PROGRAMN is low.
• D23 illuminated (red) – This indicates that GSRN is low.
PROGRAMN & RESETN
(see Appendix A, Figure 7)
These push-button switches assert/de-assert the logic levels on the PROGRAMN (SW5) and RESETN (SW4).
Depressing the button drives a logic level “0” to the device.
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MODE [3:0]
(see Appendix A, Figure 7)
The FPGA MODE pins are set on the board for a particular programming mode via the SW6 DIP switch. JTAG programming is independent of the MODE pins and is always available to the user. Pushing in (depressing) the switch
is ON and sets the value to 0.
LatticeSC devices support many configuration modes. Listed below are the configuration modes supported on this
board. The modes are either directly supported or emulated using the CPLD on board.
Table 5. Configuration Mode Selections
MODE3 SW6-4
MODE2 SW6-3
MODE1 SW6-2
MODE0 SW6-1
Configuration Mode
0 (ON)
1 (OFF)
0 (ON)
1 (OFF)
SPI Flash
1 (OFF)
0 (ON)
0 (ON)
0 (ON)
Master Serial
1 (OFF)
1 (OFF)
1 (OFF)
1 (OFF)
Slave Serial
1 (OFF)
1 (OFF)
0 (ON)
0 (ON)
Master Parallel
0 (ON)
1 (OFF)
1 (OFF)
0 (ON)
Master Byte
1 (OFF)
0 (ON)
0 (ON)
1 (OFF)
Slave Parallel
X (don’t care)
X (don’t care)
X (don’t care)
X (don’t care)
ispJTAG
Bank1 VCCIO
(see Appendix A, Figure 8)
VCCIO1 can be selected on the board to be either 3.3V or 2.5V using J107.
A jumper shunt placed between pin 1 and pin 2 will connect 2.5V. A jumper shunt between pin 2 and pin 3 will connect 3.3V. The user must pay attention to the design and select the correct supply for VCCIO1.
On-Board Flash Memory
(see Appendix A, Figure 7)
Three memory devices (U3 and U22) are on board for non-volatile configuration memory storage. SW3 is used to
control writing and reading from the memory. U3 is an 8M, 8-pin SOIC Flash device and U22 is a 64M, 16-pin
TSSOP Flash device. U22 is located on the bottom side (secondary) of the PCB.
Refer to TN1100, SPI Serial Flash Programming Using ispJTAG in LatticeSC Devices for recommended procedures and software usage.
To use both SPI Flash devices to program the LatticeSC device, the user must write to the Flash devices individually. This is accomplished by setting SW3 accordingly. Writing to Flash #1 (U22), close 3 and 5 switch positions
(ON) and open all others.
Writing to Flash #2 (U3), close 2 and 4 switch positions (ON) and open all others.
For reading from the Flash devices individually, use the same switch settings as described for writing. For reading
from both Flash devices in a cascading format, close switch positions (1, 3, 4, 5, 8).
FPGA Clock Management
(see Appendix A, Figure 14)
The evaluation board includes various features for generating and managing on-board clocks. The clocks are generated from either input provided from SMAs (see Table 6) or from crystal oscillators (Y1 and Y3). Y1 is socketed
for interchangeability and Y3 is a 312.5MHz surface-mount with an enable/disable jumper (J102). Y4 and Y5 also
can be selected using J108 to disable Y5.
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When Y3 or Y5 are enabled, the user should remove Y1 or Y4 respectively to eliminate contention issues between
the clock sources.
There are several resistor stuffing options that may be needed based on the user’s requirements, R183 and R184
are left OPEN by factory default allowing connection to SMA inputs via R181 and R182. R181 and R182 are factory
populated with 0-ohm resistors. To utilize the Y1 or Y3 oscillators, the user should move the 0-ohms resistors from
R183 and R184 to R181 and R182.
This scenario is the same for R208 and R209 with R212 and R213 respectively.
A 100-ohm termination is optionally available and needs to be added to R185 and R186 if the SMA clock input are
not used. R185 and R186 are left OPEN at the factory and provide input termination to the B and A SERDES
Quads respectively.
Table 6. Reference Clock Input SMA Connections
J91
Reference + Input PCS361
J92
Reference - Input PCS361
J110
Reference + Input PCS360
J111
Reference - Input PCS360
A 100.0MHz surface-mounted oscillator (Y2) is also provided and fanned-out to three general-purpose FPGA
inputs.
SERDES
(see Appendix A, Figure 10)
SERDES Reference Clock
The 50-ohm terminated SMA connectors provide the supply reference clocks directly to the LatticeSC device. This
device will drive clocks to both SERDES quads via 100-ohm LVDS signaling. On-board clock oscillators mentioned
in the previous sections can be chosen to drive the same SERDES reference clocks.
SERDES Channels
Surface Mounted SMA Connections
(see Appendix A, Figure 10)
DC coupled top-mounted SMA connectors connect to the SERDES Tx and Rx channels of Quad B SERDES on
the left side (PCS 361). These pins are directly coupled to the designated SMA connector creating a path for both
input and output differential data.
Table 7. SERDES Connectors (see Appendix A, Figure 10)
J11
B_HDINN0_L
J6
B_HDINP0_L
J20
B_HDINN1_L
J16
B_HDINP1_L
J27
B_HDINN2_L
J23
B_HDINP2_L
J31
B_HDINN3_L
J28
B_HDINP3_L
J10
B_HDOUTN0_L
J5
B_HDOUTP0_L
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J19
B_HDOUTN1_L
J15
B_HDOUTP1_L
J26
B_HDOUTN2_L
J22
B_HDOUTP2_L
J30
B_HDOUTN3_L
J28
B_HDOUTP3_L
PCI Express x1 Cable Connectors
PCI Express x1 Cable Connectors (CON1 and CON2) are provided to demonstrate cable capabilities of the
SERDES channels. These cable connectors conform with the PCI Express Cable Specifications. A simple cable
loopback connected between the connectors can be used to evaluate this feature.
SERDES SMPTE Channels
(see Appendix A, Figure 10)
A single-channel 75-ohm SERDES channel is connected to BNC edge connectors. These connections are provided to connect to SMPTE video equipment. The channels include the appropriate passive components for
interoperability to SMPTE devices.
Table 8. SERDES SMPTE BNC Connectors (see Appendix A, Figure 10)
J9
A_HDINN1_L
J4
A_HDINP1_L
J21
A_HDOUTN1_L
J14
A_HDOUTP1_L
SERDES PCI Express Channels
(see Appendix A, Figure 10)
This board is equipped to communicate directly as an add-on card to a PCI Express host. It is designed with edgefingers (CN1) to fit directly into an x4 host receptacle. Power can be supplied directly from the PCI Express host via
the edge-finger connections.
FPGA Test Pins
General-purpose FPGA pins are available for user applications. FPGA pins are connected to switches and LEDS
designated according to the following table.
Table 9. FPGA Test Pins (see Appendix A, Figure 7)
Switch
BGA
Netname
LED
BGA
NetName
SW2D
A20
Switch1
D2
A19
RED1
SW2C
K22
Switch2
D5
J21
YELLOW1
SW2B
K21
Switch3
D7
H21
GREEN1
BLUE1
SW2A
G20
Switch4
D9
B18
SW1D
F20
Switch5
D3
A18
RED2
SW1C
J22
Switch6
D6
H20
YELLOW2
SW1B
H22
Switch7
D8
H19
GREEN2
SW1A
B19
Switch8
D10
E19
BLUE2
Note: LEDs will illuminate if connected to an un-programmed FPGA pin. It is recommended that a pull-down be
programmed on FPGA output pins.
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Logic Analysis Connection (LA1)
(see Appendix A, Figure 13)
Agilent single-ended probes designed for connection to the supplies. Tyco/AMP’s 2-767004-2 MICTOR connector
can be easily attached for signal bus analysis. Connections to general-purpose I/O pins are provided to the boardready 38-pin MICTOR connector.
Figure 5. Cable Assembly for Logic Analysis (Not Included)
Table 10. Mictor Connector Connections
Site
BGA
Signal
Mictor Pin #
PR77A
AB4
LA1
5
PR77B
AC4
LA2
6
PR77C
Y11
LA3
7
PR77D
AA11
LA4
8
PR78A
AE1
LA5
9
PR78B
AF1
LA6
10
PR78C
AB5
LA7
11
PR78D
AC5
LA8
12
PR80A
AD2
LA9
13
PR80B
AE2
LA10
14
PR80C
AD5
LA11
15
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Table 10. Mictor Connector Connections (Continued)
Site
BGA
Signal
Mictor Pin #
PR80D
AE5
LA12
16
PR81A
AE3
LA13
17
PR81B
AF3
LA14
18
PR81C
AA10
LA15
19
PR81D
AB10
LA16
20
PR82A
AJ1
LA17
21
PR82B
AK1
LA18
22
PR82C
AB8
LA19
23
PR82D
AC8
LA20
24
PR84A
AF2
LA21
25
PR84B
AG2
LA22
26
PR84C
AC6
LA23
27
PR84D
AD6
LA24
28
PR85A
AE4
LA25
29
PR85B
AF4
LA26
30
PR85C
AF5
LA27
31
PR85D
AF6
LA28
32
PR86A
AH2
LA29
33
PR86B
AJ2
LA30
34
PR86C
AC7
LA31
35
PR86D
AD7
LA32
36
PR89A
AH3
LA33
37
PR89B
AJ3
LA34
38
17-Segment LED Display
(see Appendix A, Figure 12)
General-purpose FPGA pins are connected to a 17-segment display according to the following table. These pins
can be driven low to illuminate the display segments.
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Table 11. 17-Segment LED Display
Segment
BGA
A
AC33
B
AA30
C
AD34
D
AA28
E
AA33
F
AB34
G
AA29
H
Y31
K
Y32
M
W24
N
W33
P
Y34
R
W26
S
V34
T
W25
U
U33
DP
Y27
A
H
B
K M N
U
G
P
T S
F
C
R
E
D
DP
Test SMA Connections
General-purpose FPGA pins are available via SMA test connections. These connections are designed to permit
the evaluation of several FPGA I/O buffer types. The use of several termination schemes permits easy interfaces
for each buffer type.
Table 12. FPGA I/O Test SMA Connectors
SMA
Designation
Name
1152
BGA
LFSC80 Signal
Termination Description
Termination
Resistor(s)
See Appendix A, Figure 12
J36
LVDS_INP0
PL22A
E34
DC-Coupled
n/a
J38
LVDS_INN0
PL22B
F34
DC-Coupled
n/a
J33
LVDS_INP1
PL24A
F33
DC-Coupled
n/a
J35
LVDS_INN1
PL24B
G33
DC-Coupled
n/a
J40
LVDS_INP2
PL25A
K30
DC-Coupled
n/a
J42
LVDS_INN2
PL25B
L30
DC-Coupled
n/a
J44
LVDS_INP3
PL26A
G34
DC-Coupled
n/a
J46
LVDS_INN3
PL26B
H34
DC-Coupled
n/a
J37
LVDS_OUTP0
PL17A
F31
100-ohm Differential Termination
J32
LVDS_OUTN0
PL17B
G31
100-ohm Differential Termination
J34
LVDS_OUTP1
PL18A
D33
100-ohm Differential Termination
J39
LVDS_OUTN1
PL18B
E33
100-ohm Differential Termination
J41
LVDS_OUTP2
PL20A
F32
100-ohm Differential Termination
J43
LVDS_OUTN2
PL20B
G32
100-ohm Differential Termination
J45
LVDS_OUTP3
PL21A
H30
100-ohm Differential Termination
J47
LVDS_OUTN3
PL21B
J30
100-ohm Differential Termination
PR16A/URC_PLLC_IN_A
F5
50-ohm Ground Termination
R114
R116
R117
R118
See Appendix A, Figure 13
J48
URC_PLLT
13
R166
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Table 12. FPGA I/O Test SMA Connectors (Continued)
SMA
Designation
Name
1152
BGA
LFSC80 Signal
J49
URC_PLLC
PR16B/URC_PLLT_IN_A
G5
J50
PCLKT3_1
PR50C
J51
PCLKC3_1
PR50D
Termination Description
Termination
Resistor(s)
50-ohm Ground Termination
R167
U6
50-ohm Ground Termination
R168
V6
50-ohm Ground Termination
R169
High Speed Test Point
DP1
(see Appendix A, Figure 12)
General-purpose FPGA pins are available via a differential test pad. These connections allow a high-impedance
probe to measure the performance of a coupled- differential output buffer pair.
DDR2 Memory
U18
(see Appendix A, Figure 11)
The LatticeSC Evaluation Board is equipped with an 84-BGA DDR2 SDRAM memory device such as a Micron
MT47H16M16BG-3 device. The DDR2 memory interface includes a 16-bit wide device. The evaluation board
includes termination of address and command signals. It includes all power and external components needed to
demonstrate the memory controller of the LatticeSC device.
Ordering Information
Description
Ordering Part Number
LatticeSC PCI Express x4 Evaluation Board
China RoHS Environment-Friendly
Use Period (EFUP)
LFSC80E-P4-EV
10
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail:
[email protected]
Internet: www.latticesemi.com
Revision History
Date
Version
July 2007
01.0
Initial release.
Change Summary
December 2007
01.1
Updated FPGA Clock Management text section.
September 2009
01.2
Updated On-Board Flash Memory text section.
© 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as
listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of
their respective holders. The specifications and information herein are subject to change without notice.
14
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2
Title
Cover Page
1
of
11
Rev
3.0
C
D
Date:
Size
C
1
Sheet
1
SC80 X4 PCI EXPRESS Card
Project
A
3
2
A
4
Board will meet PCI Express Electromechanical
Specification Rev 1.0
Add-in card form factor for standard height and full length
4.376" Height x 9.5" Length
3
B
5
LatticeSC
x4 PCI Express Platform
Evaluation Board
4
B
C
D
5
Lattice Semiconductor
LatticeSC PCI Express x4 Evaluation Board
User’s Guide
Appendix A. Schematics
Figure 6. Cover Page
A
B
C
C1
R35
R161
4_7K-0603SMT
4
2
GSRN
5
4
6
3
2Y
1Y
Momentary Switch
B3F-1150
3
1
2
SW5
Momentary Switch
B3F-1150
3
PROGRAMN
PROGRAMN
R36
1
2
3
4
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
12
11
8
7
6
5
16
15
14
13
12
11
10
9
5
4
2
1
3
1
Q_1
SCSN
Q_0
OUT1
OUT2
MAX6817
IN2
IN1
U4
FLASH_DIS
3_3V
SN74LVC125A/SO14
2A
2OE_N
1A
1OE_N
U6A
3_3V
M25P80-FLASH
S#
VCC
Q HOLD#
CLK
W#
GND
DI
U3
FLASH1
FLASH0
M25P64-FLASH
HOLD# CK
VCC
D
DU8
DU1
DU2
DU7
DU6
DU3
DU5
DU4
S#
VSS
Q
W#
U22
TDA10H0SK1
1
SW4
SCSN_1
Q_1
WRITE_PROT_N
WRITE_PROT_N
SCSN_0
Q_0
FLASH_DIS
FPGA RESETN/GSRN
VCCIO1
C2
DATA1
20
19
18
17
16
15
14
13
12
11
C3
3_3V
100NF-0603SMT
10
9
8
7
6
5
4
3
2
1
R33
R67
4_7K-0603SMT
10NF-0603SMT
SW3
4_7K-0603SMT
3_3V
5
VCC
R160
4_7K-0603SMT
4_7K-0603SMT
10
9
8
7
6
5
4
3
2
1
R37
100NF-0603SMT
R16
10K-0603SMT
GND
2
R38
100R-0603SMT
6
4
3_3V
3_3V 3_3V
2
D4
R18
4_7K-0603SMT
PP11
[11] INITN
[11] DONE
1
R17
4_7K-0603SMT
R11
10K-0603SMT
DONE
INITN
4
DONE indicator will light when
configuration is successfully
completed
1
LED-SMT1206_RED
D1
R4
680R-0603SMT
R
A16
A15
B15
K13
K14
F15
G15
K16
D1
C1
M9
L9
B33
J8
L16
D14
G14
M16
M15
K17
J27
K27
M26
L26
C33
D34
B2
C34
K8
LED-SMT1206_RED
D21
680R-0603SMT
R162
VCCIO1
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
TCK
TDI_SC
TDO_SC
TMS_SC
GSRN
PROGRAMN
WRN
CS0N
CS1
SCSN
SI
SCK
INITN
DONE
LOADER_CK
R20
4_7K-0603SMT
VCCIO1
VCCIO1 INITN indicator will light
if an error occurs during
configuration programming
LED-SMT1206_RED
D23
680R-0603SMT
R170
VCCIO1
[11] GSRN
[11] PROGRAMN
[11] DATA[0..7]
[11] LOADER_CK
M0
M1
M2
M3
R21
4_7K-0603SMT
VCCIO1
R22
4_7K-0603SMT
8
7
6
5
Q3
2N2222/SOT23
R31
4_7K-0603SMT
WRITE_PROT_N
FLASH_DIS
CS0N
CS1
WRN
SCSN_0
SCSN_1
DATA0
100R-0603SMT
R26
10K-0603SMT
R32
4_7K-0603SMT
VCCIO1
R6
D
LED-SMT1206_GREEN
R25
10K-0603SMT
4_7K-0603SMT
Y
GSRN
R19
4_7K-0603SMT
Y
PROGRAMN
ON
R56
4_7K-0603SMT
4
SW8
4
3
Momentary Switch
B3F-1150
2
1
PUSH
BUTTON
#2
Momentary Switch
B3F-1150
3
1
2
SW7
PUSH
BUTTON
#1
3_3V
CONFIG/TOP
LFSC1152BGA
1
SW2A
SWITCH4
3
1
OUT2
OUT1
MAX6817
IN2
IN1
U24
PB2
4
3
PB1
6
3_3V
G21
F21
M19
M20
E21
D21
K19
L19
E20
D20
L20
L21
B20
A20
K22
K21
G20
F20
J22
H22
B19
A19
J21
H21
B18
A18
H20
H19
E19
D19
L18
K18
C19
C20
J19
J18
F18
E18
H18
G18
B17
A17
H17
G17
F17
E17
L17
C16
C15
H16
H15
E16
D16
J17
J16
E15
D15
H13
J13
B16
H14
J14
E14
L14
L15
F14
470R
R41
3_3V
TMS_SC
PCIE_PERSTN
OSC_IN_4
BLUE2
[11] TDI_XO
[11] TDO_XO
1
JUMPER1
J95
TDI_BUF
[11] TMS_XO
0R-0603SMT
PB1
PB2
SWITCH1
SWITCH2
SWITCH3
SWITCH4
SWITCH5
SWITCH6
SWITCH7
SWITCH8
RED1
YELLOW1
GREEN1
BLUE1
RED2
YELLOW2
GREEN2
BLUE2
470R
9 RN1H
8
EXB2HV471JV
GREEN2
YELLOW2
470R
6
11 RN1F
EXB2HV471JV
7
10 RN1G
EXB2HV471JV
RED2
470R
BLUE1
470R
12 RN1E
5
EXB2HV471JV
GREEN1
YELLOW1
RED1
470R
4
13 RN1D
EXB2HV471JV
470R
3
14 RN1C
EXB2HV471JV
470R
15 RN1B
2
EXB2HV471JV
16 RN1A
1
EXB2HV471JV
PT51A/D15
PT51B/A21
PT51C/DP1
PT51D/D14
PT52A/MPITEAN
PT52B/A18
PT52C/A20
PT52D/A19
PT53A/A17
PT53B/A15
PT53C/D13
PT53D/A16
PT55A/A14
PT55B/A13
PT55C/D12
PT55D/D11
PT56A/A12
PT56B/A11
PT56C/D31/PCLKT1_7
PT56D/D30/PCLKC1_7
PT57A/A10
PT57B/A9
PT57C/D29/PCLKT1_6
PT57D/D28/PCLKC1_6
PT59A/A8
PT59B/A7
PT59C/VREF1_1
PT59D/D27
PT60A/A6
PT60B/A5
PT60C/D26/PCLKT1_5
PT60D/D25/PCLKC1_5
PT61A/A4
PT61B/A3
PT61C/A2
PT61D/A1
PT63A/A0
PT63B/MPIRTRYN
PT63C/D24/PCLKT1_4
PT63D/DP3/PCLKC1_4
PT65A/MPICLK/PCLKT1_0
PT65B/PCLKC1_0
PT65C/DP2
PT65D/D23
PT66A/MPIACKN
PT66B/DP0
PT66D/EXTDONEO
PT67A/EXTCLKP2I
PT67B/EXTCLKP2O
PT67C/D22/PCLKT1_1
PT67D/D21/PCLKC1_1
PT69A/EXTCLKP1I
PT69B/EXTCLKP1O
PT69C/D20/PCLKT1_2
PT69D/D19/PCLKC1_2
PT70A/EXTDONEI
PT70B/DOUT
PT70C/D18
PT70D/VREF2_1
PT71A/QOUT
PT71C/D17/PCLKT1_3
PT71D/D16/PCLKC1_3
PT75A/RDN
PT75C/D10
PT75D/D9
PT77B/D8
3
SW2B
SWITCH3
12
4
SW2C
SWITCH2
6
SW2D
SWITCH1
9
10
6
SW1D
SWITCH5
3
SW1B
SWITCH7
4
SW1C
SWITCH6
10
LFSC
1152BGA
PT71B/D0
PT73A/D1
PT73B/D2
PT73C/D3
PT73D/D4
PT74A/D5
PT74B/D6
PT74C/D7
TCK
TDI
TDO
TMS
RESETN
PROGRAMN
PT74D/WRN
PT75B/CS0N
PT77A/CS1
PT77C/LDCN
PT77D/HDC
PT66C/RDY
M0
M1
M2
M3
INITN
DONE
CCLK
RDCFGN
MPIIRQN
U1F
7
7
9
1
0
11
1
0
11
1
0
8
1
0
2
1
0
8
1
0
R197
SW6
SW DIP-3 CTS 194-4MST
100NF-0603SMT
1
0
5
5
1
0
4_7K-0603SMT
R194
4_7K-0603SMT
3_3V
J100
4.7K
2
4
2
2
4
6
1
3
5
HEADER 3X2
J105
2
4.7K
1
3
JUMPER1
J103
1
[5]
R15
680R-0603SMT
R12
680R-0603SMT
R10
680R-0603SMT
HEADER 2X2
[9]
RN3C
EXBV8V472JV
2
RED1
1
RN2A
1
16
470R-1206SMT
R1
1
[11]
TMS
4.7K
JUMPER1
J94
2
TDI_SC
TDO_SC
LOCAL_TDO
4.7K
2
TCK
3
RN2E
RN2G
4
6
OUT Y2
OUT Y1
TCK
4
6
OUT Y2
OUT Y1
NC7WZ16-MACO6A/Fairchild TinyLogic
R34
220R-0603SMT
D11
LED-SMT1206_GREEN
This LED
indicates activity
on TDI.
TDI_BUF
BLUE2
RN2F
8
EXB2HV103JV
10K
6
11
1
3_3V
10
1
3_3V
IN A2
IN A1
U5
U7
IN A2
IN A1
3
1
Q8
2N2222/SOT23
1
Date:
Size
C
Title
3
LOCAL_TMS
LOCAL_TCK
DONE
INITN
LOCAL_TDO
LOCAL_TDI
PROGRAMN
VCC
TCK
TMS
NC
7
1
HEADER 10
INITN
GND
ispEN_N
TDI
TDO
DONE
J2
2
3
4
5
6
8
9
10
Configuration/Testpoints
LED-SMT1206_BLUE
D10
Q9
2N2222/SOT23
12_0V
1
Sheet
2
SC80 X4 PCI EXPRESS Card
Project
91
LED-SMT1206_GREEN
D8
Q7
2N2222/SOT23
of
3_3V
FROM ISPVM CABLE
EXB2HV103JV
10K
RN2H
LED-SMT1206_YELLOW
D6
Q5
2N2222/SOT23
12_0V
470R-1206SMT
R24
1
13
470R-1206SMT
EXB2HV103JV
10K
7
RN2D
EXB2HV103JV
10K
4
LED-SMT1206_RED
D3
Q2
2N2222/SOT23
12_0V
470R-1206SMT
R14
1
15
470R-1206SMT
LED-SMT1206_BLUE
D9
GREEN2
RN2B
EXB2HV103JV
10K
2
12_0V
470R-1206SMT
R2
R28
12_0V
Q6
2N2222/SOT23
LED-SMT1206_GREEN
D7
YELLOW2
RED2
1
R27
12
1
LED-SMT1206_YELLOW
D5
Q4
2N2222/SOT23
12_0V
470R-1206SMT
EXB2HV103JV
10K
5
14
1
R23
EXB2HV103JV
10K
RN2C
NC7WZ16-MACO6A/Fairchild TinyLogic
BLUE1
GREEN1
YELLOW1
12_0V
470R-1206SMT
R13
EXB2HV103JV
10K
LED-SMT1206_RED
D2
Q1
2N2222/SOT23
12_0V
R8
680R-0603SMT
RN3D
R9
680R-0603SMT
R7
680R-0603SMT
R5
680R-0603SMT
R3
680R-0603SMT
RN3B
2
C497
4_7K-0603SMT
R30
GND
7
5
VCC
1
RN3A
LOCAL_TDO 8
TCK
2
7
1
SW1A
SWITCH8
R195
4_7K-0603SMT
3
6
TMS
1
2
3
4
220R-0603SMT
G
3
2
R
2
Y
3
2
G
3
2
B
12
GND
2
R196
4_7K-0603SMT
4
TDI_BUF 5
R
3
5
3
C4
100NF-0603SMT
3
2
C7
VCC
GND
2
5
VCC
GND
2
100NF-0603SMT
VCCIO1
R29
4
4_7K-0603SMT
R
3
2
Y
3
2
G
3
2
B
3
2
16
11
C6
5
Rev
3.0
100NF-0603SMT
A
B
C
D
Lattice Semiconductor
LatticeSC PCI Express x4 Evaluation Board
User’s Guide
Figure 7. Configuration/Testpoints
A
B
C
2_5V
1_8V
C12
C36
100NF-0603SMT
C42
5
4
2
1UF-16V-0805SMT
VDDQ
VREF
SD
U8
C37
SC_VTT
LP2996-SO8
MC_VREF_REG
+
C38
VTT
VSENSE
C43
C29
8
3
+ C47
3_3V
22UF-16V_TANTBSMT
C44
22UF-16V_TANTBSMT
C213
C214
C215
C216
C217
C218
C220
R199
VTT_6_7
0R-0805SMT
C219
TP4
C221
TESTPOINT
TESTPOINT
TESTPOINT
U1H
C451
C460
C459
C456
C457
C458
C454
C453
C455
C452
5
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
4
PP7
AB22
AB13
AA21
AA18
AA19
AA16
AA17
AA14
V21
Y20
Y18
Y17
Y15
V14
W21
W19
W16
W14
V20
V18
V17
V15
U20
U18
U17
U15
T21
T19
T16
T14
U21
R20
R18
R17
R15
U14
P21
P18
P19
P16
P17
P14
N22
N13
U1J
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
1_8V
LFSC1152BGA
VCC CORE
LFSC
1152BGA
LFSC1152BGA
SUPPLIES
LFSC
1152BGA
VCC_CORE
VCC12
VCC12
VCC12
VCC12
VCC12
VCC12
VCC12
VCC12
VCC12
VCC12
VCC12
VCC12
VCC12
VCC12
VCC12
VCC12
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCJ
VTT_2
VTT_2
VTT_2
VTT_3
VTT_3
VTT_3
VTT_4
VTT_4
VTT_4
VTT_5
VTT_5
VTT_5
VTT_6
VTT_6
VTT_6
VTT_7
VTT_7
VTT_7
XRES
PROBE_VCC
PROBE_GND
TEMP
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
C212
VCC_CORE
PP9
VTT_2_3
R198
0R-0805SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
C35
[6] MC_VREF_REG
100NF-0603SMT
C13
C10
1_8V
R39
4_7K-0603SMT
47UF-16V_TANTBSMT
C11
D
1UF-16V-0805SMT
C49
1UF-16V-0805SMT
1
1UF-16V-0805SMT
2
1UF-16V-0805SMT
100NF-0603SMT
1
2
10UF-16V_TANTBSMT
C448
C447
C449
C442
C445
C446
C444
C443
C279
C280
C281
C282
C283
C284
C285
C286
C485
C484
C486
C479
C482
C483
C481
C480
C494
C493
C495
C488
C491
C492
C490
C489
+ C30
1_5V
+ C39
2_5V
VDDTX
VDDRX
VDDP
1_5V
C34
A_VDDOB0_L
A_VDDOB0_R
A_VDDOB1_L
A_VDDOB1_R
A_VDDOB2_L
A_VDDOB2_R
A_VDDOB3_L
A_VDDOB3_R
A_VDDP_L
A_VDDP_R
A_VDDRX0_L
A_VDDRX0_R
A_VDDRX1_L
A_VDDRX1_R
A_VDDRX2_L
A_VDDRX2_R
A_VDDRX3_L
A_VDDRX3_R
A_VDDTX0_L
A_VDDTX0_R
A_VDDTX1_L
A_VDDTX1_R
A_VDDTX2_L
A_VDDTX2_R
A_VDDTX3_L
A_VDDTX3_R
VDDAX25_L
VDDAX25_R
C31
F29
F6
F28
F7
F27
F8
F26
F9
H25
H10
C32
C3
C29
C6
C28
C7
C25
C10
E30
E5
E29
E6
E28
E7
E27
E8
M23
M12
U1B
PP8
3
VDDAX25 PROBE POINT
PP5
VDDIB PROBE POINT
ANALOG POWER
LFSC
1152BGA
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
C496
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
C487
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
C278
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
C450
3
100NF-0603SMT
C239
VDDRX
100NF-0603SMT
C240
VDDTX
C16
C467
C26
C17
10NF-0603SMT
C241
10NF-0603SMT
C243
10NF-0603SMT
C21
100NF-0603SMT
C469
VDDP
C15
C28
100NF-0603SMT
C242
100NF-0603SMT
C463
100NF-0603SMT
C468
C27
C18
10NF-0603SMT
C244
10NF-0603SMT
C461
10NF-0603SMT
C465
2
100NF-0603SMT
C245
100NF-0603SMT
C462
100NF-0603SMT
C466
D25
D10
D24
D11
D23
D12
D22
D13
L22
L13
G25
G10
G24
G11
G23
G12
G22
G13
K25
K10
L25
L10
K24
K11
L24
L11
PP4
C502
2
C464
VDDTX
VDDRX
VDDP
1_5V
10NF-0603SMT
C246
10NF-0603SMT
C247
10NF-0603SMT
VDDOB PROBE POINT
C25
B_VDDOB0_L
B_VDDOB0_R
B_VDDOB1_L
B_VDDOB1_R
B_VDDOB2_L
B_VDDOB2_R
B_VDDOB3_L
B_VDDOB3_R
B_VDDP_L
B_VDDP_R
B_VDDRX0_L
B_VDDRX0_R
B_VDDRX1_L
B_VDDRX1_R
B_VDDRX2_L
B_VDDRX2_R
B_VDDRX3_L
B_VDDRX3_R
B_VDDTX0_L
B_VDDTX0_R
B_VDDTX1_L
B_VDDTX1_R
B_VDDTX2_L
B_VDDTX2_R
B_VDDTX3_L
B_VDDTX3_R
22UF-16V_TANTBSMT
LFSC1152BGA
+ C24
JUMPER1
C501
1
J106
C503
3_3V
2_5V
2_5V
1_2V
1
FB3
C20
BLM41PG600SN1
FB7
BLM41PG600SN1
FB5
BLM41PG600SN1
+ C19
1_8V
PP2
1
1.8V PROBE POINT
2
+ C8
PP1
PP64
2.5V PROBE POINT
C9
2
C499
J107
HEADER 3X1
VCCIO1 SELECT
+ C498
100NF-0603SMT
100NF-0603SMT
10NF-0603SMT
10NF-0603SMT
C500
VCCIO1
2
3
3
2
VCC12 PROBE POINT
22UF-16V_TANTBSMT
22UF-16V_TANTBSMT
N14
P13
AA13
AB14
AB21
AA22
P22
N21
AB20
AB15
Y22
Y13
2_5V
R22
R13
N20
VCCAUX PROBE POINT
N15
M21
M22
+ C40
C41
N23
PP13
P23
T22
U22
V23
V22
W22
AA23
AB23
AC23
AC22
AC21
AB19
AB18
AC17
AB17
AB16
AC14
AC13
AC12
AB12
AA12
W13
V13
U13
T13
C48
U12
P12
N12
M14
M13
M18
N19
N18
SC_VTT
N17
R40
N16
0R-0603SMT
C2
VTT_2_3 N11
R12
T12
W12
Y12
AB11
AD13
AC15
0.9V VTT PROBE POINT
AC16
AC19
AC20
PP3
AD22
+ C22
VTT_6_7
C23 +
AB24
W23
Y23
N24
R23
T23
AF28
AF7
AF8
AF27
TESTPOINT
C14
100NF-0603SMT
100UF-FKSMT
6
7
AVIN
PVIN
GND
1
C54
1
2
R43
1K-0603SMT
TP1
1
TP2
1
TP3
1
1
+ C53
1UF-16V-0805SMT
1
2
2_5V
A_VDDIB0_L
D32
A_VDDIB1_L
D31
A_VDDIB2_L
D30
A_VDDIB3_L
D29
B_VDDIB0_L
D28
B_VDDIB1_L
D27
B_VDDIB3_L
E26
B_VDDIB2_L
D26
A_VDDIB0_R
D3
1UF-16V-0805SMT
22UF-16V_TANTBSMT
1
1
22UF-16V_TANTBSMT
1
1UF-16V-0805SMT
2
2
22UF-16V_TANTBSMT
4
22UF-16V_TANTBSMT
1
2
100NF-0603SMT
A_VDDIB1_R
D4
100NF-0603SMT
A_VDDIB3_R
D6
A_VDDIB2_R
D5
100NF-0603SMT
D9
B_VDDIB1_R
D8
100NF-0603SMT
B_VDDIB0_R
D7
100NF-0603SMT
B_VDDIB2_R
100NF-0603SMT
B_VDDIB3_R
E9
100NF-0603SMT
1UF-16V-0805SMT
Date:
Size
C
Title
+ C51
VDDRX
+ C45
VDDTX
+ C32
VDDP
1UF-16V-0805SMT
1_2V
1
2
1
2
100NF-0603SMT
5
1UF-16V-0805SMT
22UF-16V_TANTBSMT
22UF-16V_TANTBSMT
C52
C46
C33
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VCCIO7
PP12
VDDRX PROBE POINT
PP10
VDDTX PROBE POINT
PP6
VDDP PROBE POINT
LFSC1152BGA
VCCIO
LFSC
1152BGA
1
Sheet
3
SC80 X4 PCI EXPRESS Card
Project
1
VCCIO1PROBE POINT
U1I
D17
C18
F16
G19
K12
K15
J20
L23
J9
J25
E3
G6
H4
K7
L3
M11
N6
P4
R9
T7
U3
V4
W6
Y10
AA3
AB7
AC10
AD4
AE6
AG3
AK4
AF9
AD12
AF15
AJ7
AH10
AJ13
AH16
AM5
AL8
AM11
AL14
AM17
AE20
AE23
AE26
AJ19
AH22
AJ25
AH28
AL18
AM21
AL24
AM27
AL30
AK32
AG31
AE28
AD32
AC24
AB29
AA31
Y26
W28
V32
U31
T29
R25
P32
N28
M25
L31
K29
H32
G28
E31
Power Supplies
22UF-16V_TANTBSMT
1UF-16V-0805SMT
1UF-16V-0805SMT
1UF-16V-0805SMT
1
2
1
2
1
17
2
of
11
Rev
3.0
A
B
C
D
Lattice Semiconductor
LatticeSC PCI Express x4 Evaluation Board
User’s Guide
Figure 8. Power Supplies
A
B
C
TESTPOINT
R164
0R-0805SMT
1
TP15
TP13
1
R163
0R-0805SMT
C70
10UF-16V_TANTBSMT
3_3VIN
1
1
TP11
1
TP9
TP7
1
C63
10UF-16V_TANTBSMT
3_3VIN
TESTPOINT
TESTPOINT
TESTPOINT
TESTPOINT
TESTPOINT
TP5
5
1
TP16
TP14
1
TP12
1
TP10
1
TP8
1
1
TP6
TESTPOINT
TESTPOINT
TESTPOINT
TESTPOINT
TESTPOINT
TESTPOINT
GND Pads
Distributed around the board
C73
2
4
5
100NF-0603SMT
1_5V
R75
1
3
1.8V
C74
22UF-16V_TANTBSMT
1_8V
C66
C75
4
12_0V
R77
OPEN-0805SMT
12_0V
1
2
U14
1
2
GND
VIN
GND
VIN
U10
R53
1
10K-0603SMT
LED-SMT1206_GREEN
D16
1_8V
1.8V
R46
470R-1206SMT
12_0V
Q12
2N2222/SOT23
R165
OPEN-0805SMT
R52
1
10K-0603SMT
3
VOUT
R59
0R-0603SMT
5
6
1.2V
0R-0603SMT
R73
SC1592
TAB
R81
1M-0603SMT
8
U25
3
ILIM
IN
CNTL
GND
OUT
SENSE
EN
VCCA
R71
100K-0603SMT
1_8K-0603SMT
R62
C71
10UF-16V_TANTBSMT
SENSE
BOURNS-3224W-10K
R64
PTH12060W
VOUT
5
6
R55
100K-0603SMT
1_2V
R54
1
10K-0603SMT
LED-SMT1206_GREEN
D17
C58
10UF-16V_TANTBSMT
SENSE
BOURNS-3224W-10K
R60
PTH12060W
Q13
2N2222/SOT23
1.2V
R47
470R-1206SMT
12_0V
1
2
3
4
5
6
7
R202
10K-0603SMT
VCCA
VCCA
12_0V
R200
100R-0805SMT
GND
R204
49_9R-0603SMT 100R-0603SMT
R203
R201
12_0V
0R-0603SMT
C60
10UF-16V_TANTBSMT
R48
D18
LED-SMT1206_GREEN
12V
INPUT
GOOD
12_0V
470R-1206SMT
2
12_0V
2
1
R74
OPEN-0805SMT
1
2
U15
12_0V
2
GND
VIN
OPEN-0805SMT
R63
3_3VIN
5
6
0R-0603SMT
R72
R70
100K-0603SMT
2.5V
R79
2_2K-0603SMT
5
R61
Date:
Size
C
Title
3
1
SET VALUE
1V= 36.5K
1.2V=17.4K
330UF-FKSMT
C62
+
DC/DC Conversion
1
12_0V
JUMPER1
J98
R66
15_4K/SMT0603
R156
24K/SMT0603
1
1
Sheet
4
SC80 X4 PCI EXPRESS Card
Project
J3
2
F1
F1251CT-ND
10A Fast-Blo SMT Socketed Fuse
F5
F1228CT-ND
5A Fast-Blo SMT Socketed Fuse
HEADER 3x1
ADJ
1.2V
J60
330UF-FKSMT
C69
+
2_5V
2
1V
0R-0603SMT
C61
10UF-16V_TANTBSMT
SENSE
6
R58
100K-0603SMT
VCC_CORE
100UF-FKSMT
+
C56
+
470UF-FKSMT
12_0V
12_0V
C55
1
Male Power Jack 2.1mm
22HP037
3
POWER INPUT
VOUT
BOURNS-3224W-10K
R65
PTH03010W
C68
10UF-16V_TANTBSMT
SENSE
VOUT
BOURNS-3224W-10K
R80
GND
VIN
SC
VCC_CORE
4.32K Typical
PTH12060W
1
2
U11
GND
+12VDC
Terminal Block/ED1202DS
TB1
VCC12 power supply must always
be higher than VCC Core,
or if lower, then well within 150mV
of VCC Core
R50
150R-0603SMT
3.3V
D13
LED-SMT1206_GREEN
3_3V
F2
F1228CT-ND
5A Fast-Blo SMT Socketed Fuse
F4
F1228CT-ND
5A Fast-Blo SMT Socketed Fuse
330UF-FKSMT
C72
+
1_2V
330UF-FKSMT
C59
+
3_3V
3.3V
R49
100R-0603SMT
2.5V
D12
LED-SMT1206_GREEN
2_5V
3_3VIN
POWER RAIL GOOD INDICATORS
LED-SMT1206_GREEN
D15
1_5V
1.5V
R45
470R-1206SMT
F3
F1228CT-ND
5A Fast-Blo SMT Socketed Fuse
F6
F1228CT-ND
5A Fast-Blo SMT Socketed Fuse
C65
22UF-16V_TANTBSMT
124R-0603SMT
BOURNS-3224W-5K
R101
AMS1503CT
OUTPUT
VCONTROL
SENSE
ADJUST_GND
R68
1
3
124R-0603SMT
BOURNS-3224W-2K
R78
AMS1503CT
VCC_CORE
R51
Q11
1
10K-0603SMT
2N2222/SOT23
LED-SMT1206_GREEN
D14
1.5V
Q10
2N2222/SOT23
OUTPUT
VCONTROL
SENSE
ADJUST_GND
VPOWER
U12
VPOWER
U16
C64
2
4
5
R44
470R-1206SMT
VCC
CORE
12_0V
G
3
2
D
100NF-0603SMT
G
4
G
12_0V
OPEN-0603SMT
2
5
R76
8
G
3
2
R69
3_3K-0603SMT
9
G
3
2
G
3
100NF-0603SMT
MUP
10
INHIBIT#
9
2
100NF-0603SMT
MUP
8
TRACK
10
INHIBIT#
3
MDWN
ADJUST
4
3_3_TRIM
GND
G
9
3
MUP
9
MDWN
8
TRACK
10
INHIBIT#
3
MUP
GND
7
MDWN
ADJUST
4
CORE_TRIM
TRACK
7
ADJUST
4
1_2_TRIM
8
TRACK
7
GND
10
INHIBIT#
3
MDWN
ADJUST
4
2_5_TRIM
GND
18
7
of
11
Rev
3.0
A
B
C
D
Lattice Semiconductor
LatticeSC PCI Express x4 Evaluation Board
User’s Guide
Figure 9. DC/DC Conversion
A
B
C
D
[8] PCIE_CLKP
[8] PCIE_CLKN
[2] PCIE_PERSTN
R224
0R-0603SMT
[8] 2_CREFCLK[8] 2_CREFCLK+
R222
0R-0603SMT
100NFX5R-0402SMT
PRSNT1#
+12V
+12V
GND
JTAG2
JTAG3
JTAG4
JTAG5
+3.3V
+3.3V
PERST#
GND
REFCLK+
REFCLKGND
PERp0
PERn0
GND
RSVD_A19
GND
PERp1
PERn1
GND
GND
PERp2
PERn2
GND
GND
PERp3
PERn3
GND
RSVD_A32
CN1
+12V
+12V
RSVD_B3
GND
SMCLK
SMDAT
GND
+3.3V
JTAG1
3.3Vaux
WAKE#
RSVD_B12
GND
PETp0
PETn0
GND
PRSNT3#
GND
PETp1
PETn1
GND
GND
PETp2
PETn2
GND
GND
PETp3
PETn3
GND
RSVD_B30
PRSNT4#
GND
x1
x4
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
x4
PETp3
PETn3
PETp2
PETn2
PETp1
PETn1
x1
PETp0
PETn0
1
JUMPER1
J97
PCIE_3V3
1
X4 PCIe Board Fingers
PCI Express x4 Edge Finger Conn.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
R190
4_02K-0603SMT
CON2_HDOUTP
PRSNT SELECT
HEADER 2X2
2
4
J96
R189
4_02K-0603SMT
CON2_HDOUTN
C521
A_HDOUTN3_L
A_HDOUTP3_L
C520
B1
B2
B3
B4
B5
B6
B7
B8
B9
A_HDOUTN0_L
A_HDOUTP0_L
2
TP17
TESTPOINT
R223
0R-0603SMT
R221
0R-0603SMT
5
B side = Primary Component Side(TOP)
A side = Secondary Component Side(BOTTOM)
PERp3
PERn3
PERp2
PERn2
PERp1
PERn1
PERp0
PERn0
PCIE_CLKP
PCIE_CLKN
PCIE_3V3
12_0V
100NFX5R-0402SMT
1
3
GND
RSVD
CWAKE#
CPRSNT#
GND
PWR
CPWRON
PETn0
PETp0
X1 PCIE RECPT
PERn0
PERp0
RSVD
SB_RTN
CREFCLKCREFCLK+
PWR_RTN
CPERST#
GND
A_HDOUTN3_L
A1
A2
A3
A4
A5
A6
A7
A8
A9
B1
B2
B3
B4
B5
B6
B7
B8
B9
CON1_HDOUTP
C519
GND
RSVD
CWAKE#
CPRSNT#
GND
PWR
CPWRON
PETn0
PETp0
CON1_HDOUTN
C518
X1 PCIE RECPT
PERn0
PERp0
RSVD
SB_RTN
CREFCLKCREFCLK+
PWR_RTN
CPERST#
GND
CON2
A1
A2
A3
A4
A5
A6
A7
A8
A9
A_HDOUTP3_L
2_CREFCLK2_CREFCLK+
A_HDINN3_L
A_HDINP3_L
1_CREFCLK1_CREFCLK+
A_RESP_L
[8] 1_CREFCLK[8] 1_CREFCLK+
A_HDINN0_L
A_HDINP0_L
100NFX5R-0402SMT
CON1
100NFX5R-0402SMT
A_HDOUTP0_L
A_RESP_R
4
CON2_HDOUTP
CON2_HDOUTN
3G_361_INP0
3G_361_INN0
3G_361_INP1
3G_361_INN1
3G_361_INP2
3G_361_INN2
3G_361_INP3
3G_361_INN3
3G_361_OUTP0
3G_361_OUTN0
3G_361_OUTP1
3G_361_OUTN1
3G_361_OUTP2
3G_361_OUTN2
3G_361_OUTP3
3G_361_OUTN3
A_HDINP3_L
A_HDINN3_L
CON1_HDOUTP
CON1_HDOUTN
A_HDOUTP1_L
A_HDOUTN1_L
A_HDINP0_L
A_HDINN0_L
A_HDINP1_L
A_HDINN1_L
U1A
A_HDINP0_L
A_HDINN0_L
A_HDINP1_L
A_HDINN1_L
A_HDINP2_L
A_HDINN2_L
A_HDINP3_L
A_HDINN3_L
A_HDOUTP0_L
A_HDOUTN0_L
A_HDOUTP1_L
A_HDOUTN1_L
A_HDOUTP2_L
A_HDOUTN2_L
A_HDOUTP3_L
A_HDOUTN3_L
B_HDINP0_L
B_HDINN0_L
B_HDINP1_L
B_HDINN1_L
B_HDINP2_L
B_HDINN2_L
B_HDINP3_L
B_HDINN3_L
B_HDOUTP0_L
B_HDOUTN0_L
B_HDOUTP1_L
B_HDOUTN1_L
B_HDOUTP2_L
B_HDOUTN2_L
B_HDOUTP3_L
B_HDOUTN3_L
B_REFCLKP_L
A_REFCLKP_L
A_RXREFCLK_L
A_REFCLKN_L
A_REFCLKP_L
A32
B32
A29
B29
A28
B28
A25
B25
A31
B31
A30
B30
A27
B27
A26
B26
E25
F25
E24
F24
E23
F23
E22
F22
A24
B24
A23
B23
A22
B22
A21
B21
SMPTE_360_INP1
SMPTE_360_INN1
A_HDOUTP1_L
A_HDOUTN1_L
BNC-Trompeter/UCBBJE20-7
1
J21
BNC-Trompeter/UCBBJE20-7
1
J14
BNC-Trompeter/UCBBJE20-7
1
J9
A_HDINP1_L
A_HDINN1_L
2.7UF-0603SMT
C112
2.7UF-0603SMT
C111
VIDEO BNCs
BNC-Trompeter/UCBBJE20-7
1
J4
LVDS Ref Clk Terminations
Place close to U1
[9] A_RXREFCLK_L
[9] A_REFCLKN_L
[9] A_REFCLKP_L
LOOPp
LOOPn
3
SERDES
LFSC-1152BGA
3
LFSC1152BGA
J31
Rosenberger 32K153-400E3
J29
Rosenberger 32K153-400E3
J27
Rosenberger 32K153-400E3
J23
Rosenberger 32K153-400E3
J20
Rosenberger 32K153-400E3
J16
Rosenberger 32K153-400E3
J11
Rosenberger 32K153-400E3
[9]
J10
Rosenberger 32K153-400E3
J15
Rosenberger 32K153-400E3
J19
Rosenberger 32K153-400E3
J22
Rosenberger 32K153-400E3
J26
Rosenberger 32K153-400E3
J28
Rosenberger 32K153-400E3
J30
Rosenberger 32K153-400E3
3G_361_INN0
3G_361_INP1
3G_361_INN1
3G_361_INP2
3G_361_INN2
3G_361_INP3
3G_361_INN3
1
1
1
1
1
1
1
2
J5
Rosenberger 32K153-400E3
3G_361_INP0
3G SMAs
B_REFCLKP_L
[9]
B_HDINP0_R
B_HDINN0_R
B_HDINP1_R
B_HDINN1_R
B_HDINP2_R
B_HDINN2_R
B_HDINP3_R
B_HDINN3_R
B_HDOUTP0_R
B_HDOUTN0_R
B_HDOUTP1_R
B_HDOUTN1_R
B_HDOUTP2_R
B_HDOUTN2_R
B_HDOUTP3_R
B_HDOUTN3_R
2
1
B_REFCLKN_L
OPEN-0603SMT
A_REFCLKN_L
OPEN-0603SMT
B_REFCLKP_L
A3
B3
A6
B6
A7
B7
A10
B10
A4
B4
A5
B5
A8
B8
A9
B9
E10
F10
E11
F11
E12
F12
E13
F13
A11
B11
A12
B12
A13
B13
A14
B14
B_REFCLKN_L
A_HDINP0_R
A_HDINN0_R
A_HDINP1_R
A_HDINN1_R
A_HDINP2_R
A_HDINN2_R
A_HDINP3_R
A_HDINN3_R
A_HDOUTP0_R
A_HDOUTN0_R
A_HDOUTP1_R
A_HDOUTN1_R
A_HDOUTP2_R
A_HDOUTN2_R
A_HDOUTP3_R
A_HDOUTN3_R
B_HDINP0_R
B_HDINN0_R
B_HDINP1_R
B_HDINN1_R
B_HDINP2_R
B_HDINN2_R
B_HDINP3_R
B_HDINN3_R
B_HDOUTP0_R
B_HDOUTN0_R
B_HDOUTP1_R
B_HDOUTN1_R
B_HDOUTP2_R
B_HDOUTN2_R
B_HDOUTP3_R
B_HDOUTN3_R
B_REFCLKN_L
J6
Rosenberger 32K153-400E3
R186
R185
A_RESP_L
A_HDOUTN0_L
4
A_RESP_R
5
2
2
2
2
A_REFCLKP_L
A_REFCLKN_L
A_REFCLKP_R
A_REFCLKN_R
RESERVED1
ULC_RESP
RESERVED2
URC_RESP
B_REFCLKP_L
B_REFCLKN_L
B_REFCLKP_R
B_REFCLKN_R
RESERVED3
RESERVED4
RESERVED5
RESERVED6
G27
H27
G8
H8
G26
H26
G9
H9
H24
J24
H11
J11
H23
J23
H12
J12
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
19
2
C104
50
C103
PETn2
B_HDINN1_R
50
100NFX5R-0402SMT
PETn3
PETp2
B_HDINP1_R
50
3G_361_OUTP0
3G_361_OUTN0
3G_361_OUTP1
3G_361_OUTN1
3G_361_OUTP2
3G_361_OUTN2
3G_361_OUTP3
3G_361_OUTN3
1
1
1
1
1
1
1
50
1
B_HDOUTP3_R
B_HDOUTN3_R
B_HDOUTP2_R
50
50
B_HDOUTN1_R
50
B_HDOUTN2_R
B_HDOUTP1_R
50
B_HDOUTP0_R
B_HDOUTN0_R
50
C105
C107
C109
Date:
Size
C
Title
C110
C108
C106
PERn0
PERp0
PERn1
PERp1
PERn2
PERp2
PERn3
PERp3
1
Sheet
5
SC80 X4 PCI EXPRESS Card
Project
SERDES
100NFX5R-0402SMT
100NFX5R-0402SMT
100NFX5R-0402SMT
100NFX5R-0402SMT
100NFX5R-0402SMT
100NFX5R-0402SMT
100NFX5R-0402SMT
B_HDINN3_R
50
50
PETn0
B_HDINP3_R
50
50
PETn1
PETp0
B_HDINP2_R
B_HDINN2_R
50
50
PETp1
PETp3
B_HDINP0_R
B_HDINN0_R
50
1
of
11
Rev
3.0
A
B
C
D
Lattice Semiconductor
LatticeSC PCI Express x4 Evaluation Board
User’s Guide
Figure 10. SERDES
A
B
R105
1K-0603SMT
1_8V
R108
1K-0603SMT
1_8V
1_8V
R103
4_7K-0603SMT
BLM41PG600SN1
FB9
R107
OPEN-0603SMT
10NF-0603SMT
1K_ADJ/SMT3MM
VDDL
+ C132
C131
R106
10NF-0603SMT
10NF-0603SMT
C
1_8V
C142
C151
100NF-0603SMT
5
22UF-16V_TANTBSMT
C125
10NF-0603SMT
R104
0R-0603SMT
C143
C152
C130
100NF-0603SMT
100NF-0603SMT
1_8V
10NF-0603SMT
10NF-0603SMT
C141
C150
100NF-0603SMT
C113
C133
C144
C153
C114
5
4
C115
8
3
PP58
C124
C118
LP2996-SO8
VTT
VSENSE
+ C123
1_8V
+ C117
1_8V
VDDQ
VREF
SD
47UF-16V_TANTBSMT
C119
C120 +
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VREF
VDDL
VSSDL
U18B
C122 +
10UF-16V_TANTBSMT
R113
1K_ADJ/SMT3MM
R110
R109
1_8V
DDR2-SDRAM-84FBGA
A1
E1
J9
M9
R1
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
A3
E3
J3
N1
P9
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
J2
J1
J7
C121
1UF-16V-0805SMT
1UF-16V-0805SMT
C134
C145
C154
1UF-16V-0805SMT
100NF-0603SMT
100NF-0603SMT
6
7
AVIN
PVIN
1
GND
22UF-16V_TANTBSMT
U17
C135
22UF-16V_TANTBSMT
100NF-0603SMT
10NF-0603SMT
10NF-0603SMT
1UF-16V-0805SMT
10NF-0603SMT
100UF-FKSMT
2
C136
100NF-0603SMT
C116
1UF-16V-0805SMT
C146
C155
1
2
100NF-0603SMT
100NF-0603SMT
1
U18A
PP63
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
LDQS
LDQS#/NU
UDQS
UDQS#/NU
LDM
UDM
CK
CK#
CKE
WE#
RAS#
CAS#
ODT
CS#
BA0
BA1
NC_A2
NC_E2
NC_R8
RFU_L1
RFU_R3
RFU_R7
4
B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
F7
E8
B7
A8
F3
B3
J8
K8
K2
K3
K7
L7
K9
L8
L2
L3
A2
E2
R8
L1
R3
R7
OPEN-0603SMT
R112
DDR2-SDRAM-84FBGA
2
D
C148
100NF-0603SMT
100NF-0603SMT
DDR_VTT
MC_VREF_REG
MC_VREF
R111
0R-0603SMT
MemIntf_DQ15
MemIntf_DQ14
MemIntf_DQ13
MemIntf_DQ12
MemIntf_DQ11
MemIntf_DQ10
MemIntf_DQ9
MemIntf_DQ8
MemIntf_DQ7
MemIntf_DQ6
MemIntf_DQ5
MemIntf_DQ4
MemIntf_DQ3
MemIntf_DQ2
MemIntf_DQ1
MemIntf_DQ0
MemIntf_A0
MemIntf_A1
MemIntf_A2
MemIntf_A3
MemIntf_A4
MemIntf_A5
MemIntf_A6
MemIntf_A7
MemIntf_A8
MemIntf_A9
MemIntf_A10
MemIntf_A11
MemIntf_A12
MemIntf_DQS0
MemIntf_DQS0#
MemIntf_DQS1
MemIntf_DQS1#
MemIntf_DM0
MemIntf_DM1
MemIntf_K
MemIntf_K#
MemIntf_CE0#
MemIntf_WE#
MemIntf_RAS#
MemIntf_CAS#
MemIntf_ODT0
MemIntf_CS0#
MemIntf_BA0
MemIntf_BA1
C147
R102
0R-0603SMT
1K-0603SMT
1K-0603SMT
PP59
[3]
MC_VREF
MemIntf_DQS1
MemIntf_DQS1#
MemIntf_DQS0
MemIntf_DQS0#
MemIntf_DM1
MemIntf_DQ7
MemIntf_DQ8
MemIntf_DQ9
MemIntf_DQ10
MemIntf_DQ11
MemIntf_DQ12
MemIntf_DQ13
MemIntf_DQ14
MemIntf_DQ15
MemIntf_K
MemIntf_K#
MemIntf_DM0
MemIntf_DQ0
MemIntf_DQ1
MemIntf_DQ2
MemIntf_DQ3
MemIntf_DQ4
MemIntf_DQ5
MemIntf_DQ6
MemIntf_CE0#
MemIntf_A12
MemIntf_A10
MemIntf_A11
MemIntf_A4
MemIntf_A5
MemIntf_A6
MemIntf_A7
MemIntf_A8
MemIntf_A9
MemIntf_A2
MemIntf_A3
MemIntf_A0
MemIntf_A1
MC_VREF
MemIntf_ODT0
MemIntf_BA0
MemIntf_BA1
MemIntf_CS0#
MemIntf_CAS#
MemIntf_WE#
MemIntf_RAS#
U1C
BANK 5
LFSC1152BGA
BOTTOM
PB65A
PB65B
PB65C
PB65D
PB66A
PB66B
PB66C
PB99D
PB66D
PB67A
PB67B
PB67C
PB67D
PB69A
PB69B
PB69C
PB69D
PB70A
PB70B
PB70C
PB70D
PB71A
PB71B
PB71C
PB71D
PB73A
PB73B
PB73C
PB73D
PB74A/PCLKT4_2
PB74B/PCLKC4_2
PB74C/PCLKT4_7
PB74D/PCLKC4_7
PB75A/PCLKT4_1
PB75B/PCLKC4_1
PB75C/PCLKT4_6
PB75D/PCLKC4_6
PB77A/PCLKT4_0
PB77B/PCLKC4_0
PB77C/VREF2_4
PB77D
PB79A/PCLKT4_5
PB79B/PCLKC4_5
PB79C/DIFFR_4
PB79D
PB80A/PCLKT4_3
PB80B/PCLKC4_3
PB80C/PCLKT4_4
PB80D/PCLKC4_4
PB83A
PB83B
PB99A
PB99B
PB99C
PB101A
PB101B
PB101C
PB101D
PB104A
PB104B
PB104C
PB104D
PB107A
PB107B
PB107C
PB107D
PB109A
PB109B
PB109C
PB109D
PB111A
PB111B
PB111C
PB111D
PB113A
PB113B
PB113C
PB113D
PB115A
PB115B
PB115C
PB115D
PB117A
PB117B
PB117C
PB117D
PB119A
PB119B
PB119C
PB119D
PB121A
PB121B
PB121C
PB121D
PB123A
PB123B
PB123C/VREF1_4
PB123D
PB124A/LRC_DLLT_IN_C/LRC_DLLT_FB_D
PB124B/LRC_DLLC_IN_C/LRC_DLLC_FB_D
PB124C
PB124D
PB125A/LRC_PLLT_IN_A/LRC_PLLT_FB_B
PB125B/LRC_PLLC_IN_A/LRC_PLLC_FB_B
PB125C/LRC_DLLT_IN_D/LRC_DLLT_FB_C
PB125D/LRC_DLLC_IN_D/LRC_DLLC_FB_C
LFSC
1152BGA
PB3A/LLC_PLLT_IN_A/LLC_PLLT_FB_B
PB3B/LLC_PLLC_IN_A/LLC_PLLC_FB_B
PB3C/LLC_DLLT_IN_C/LLC_DLLT_FB_D
PB3D/LLC_DLLC_IN_C/LLC_DLLC_FB_D
PB4A/LLC_DLLT_IN_D/LLC_DLLT_FB_C
PB4B/LLC_DLLC_IN_D/LLC_DLLC_FB_C
PB4C
PB4D
PB5A
PB5B
PB5C
PB5D/VREF1_5
PB7A/ODT0
PB7B
PB7C
PB7D
PB9A
PB9B
PB9C
PB9D
PB11A
PB11B
PB11C
PB11D
PB13A
PB13B
PB13C
PB13D
PB15A
PB15B
PB15C
PB15D
PB17A
PB17B
PB17C
PB17D
PB19A
PB19B
PB19C
PB19D
PB21A
PB21B
PB21C
PB21D
PB24A
PB24B
PB24C
PB24D
PB27A
PB27B
PB27C
PB27D
PB29A
PB29B
PB29C
PB29D
PB45A
PB45B
PB48A/PCLKT5_3
PB48B/PCLKC5_3
PB48C/PCLKT5_4
PB48D/PCLKC5_4
PB49A/PCLKT5_5
PB49B/PCLKC5_5
PB49C/DIFFR_5
PB49D
PB51A/PCLKT5_0
PB51B/PCLKC5_0
PB51C
PB51D/VREF2_5
PB52A/PCLKT5_1
PB52B/PCLKC5_1
PB52C/PCLKT5_6
PB52D/PCLKC5_6
PB53A/PCLKT5_2
PB53B/PCLKC5_2
PB53C/PCLKT5_7
PB53D/PCLKC5_7
PB55A
PB55B
PB55C
PB55D
PB56A
PB56B
PB56C
PB56D
PB57A
PB57B
PB57C
PB57D
PB59A
PB59B
PB59C
PB59D
PB60A
PB60B
PB60C
PB60D
PB61A
PB61B
PB61C
PB61D
PB63A
PB63B
PB63C
PB63D
BANK 6
AP17
AP16
AJ17
AH17
AN17
AN16
AE17
AF13
AD17
AK17
AK16
AG17
AF17
AM16
AM15
AJ15
AJ14
AL16
AL15
AG16
AF16
AP15
AP14
AH15
AH14
AP13
AP12
AK13
AK12
AN15
AN14
AE16
AD16
AK15
AK14
AG15
AG14
AM13
AM12
AJ12
AJ11
AL13
AL12
AH12
AH11
AN13
AN12
AD14
AD15
AP11
AP10
AN11
AN10
AF14
AM10
AM9
AE14
AE13
AP9
AP8
AK11
AK10
AL10
AL9
AF12
AF11
AN9
AN8
AG11
AG10
AP7
AP6
AG13
AG12
AN7
AN6
AK9
AK8
AP5
AP4
AD11
AE11
AM7
AM6
AJ9
AJ8
AP3
AN3
AF10
AE10
AL7
AL6
AK7
AK6
AN5
AN4
AH9
AH8
AM3
AM4
AG9
AG8
AN2
AM2
AJ6
AH6
3
VTT
U18 Pin
X1
U1 Pin
2
2
DDR_VTT
A3
B3
C3
D3
E3
F3
G3
H3
J3
A3
B3
C3
D3
E3
F3
G3
H3
J3
CTS-RT1402B7
A3
B3
C3
D3
E3
F3
G3
H3
J3
C237
C275
C276
C337
C338
C361
R1=50 Ohm
C362
R1
C394
R1
A1
B1
C1
D1
E1
F1
G1
H1
J1
C395
RP1
A1
B1
C1
D1
E1
F1
G1
H1
J1
C396
C397
MemIntf_A9
MemIntf_A10
MemIntf_A11
MemIntf_A12
MemIntf_A0
MemIntf_A1
MemIntf_A2
MemIntf_A3
MemIntf_A4
MemIntf_A5
MemIntf_A6
MemIntf_A7
MemIntf_A8
Date:
Size
C
Title
R1
R1
RP2
A1
B1
C1
D1
E1
F1
G1
H1
J1
MemIntf_WE#
MemIntf_RAS#
MemIntf_CAS#
MemIntf_BA1
MemIntf_BA0
MemIntf_CS0#
MemIntf_ODT0
MemIntf_CE0#
1
Sheet
6
SC80 X4 PCI EXPRESS Card
Project
DDR2
R1=50 Ohm
A1
B1
C1
D1
E1
F1
G1
H1
J1
of
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
C398
CTS-RT1402B7
A3
B3
C3
D3
E3
F3
G3
H3
J3
C236
1
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
C360
SP67
SP61
SP64
SP58
SP66
SP65
SP60
SP59
SP63
SP62
SP57
SP37
DDR_VTT
Termination
at end of line
X1
needs to be matched length
for all traces
X2
ALL Memory controller
buses, clocks, and control
traces must be 50 Ohm
Transmission lines
AM33
AN33
AH29
AJ29
AM32
AM31
AG27
AG26
AL29
AL28
AH27
AH26
AN32
AP32
AF25
AE25
AN31
AN30
AK29
AK28
AP31
AP30
AD24
AE24
AM29
AM28
AJ27
AJ26
AP29
AP28
AK27
AK26
AN29
AN28
AG25
AG24
AL26
AL25
AG23
AG22
AN27
AN26
AF24
AF23
AP27
AP26
AK25
AK24
AN25
AN24
AE22
AE21
AM26
AM25
AF22
AF21
AN23
AN22
AP25
AP24
AD21
AD20
AL23
AL22
AH24
AH23
AM23
AM22
AJ24
AJ23
AN21
AN20
AE19
AD19
AK21
AK20
AK23
AK22
AP23
AP22
AG21
AG20
AL20
AL19
AG19
AF19
AP21
AP20
AH21
AH20
AM20
AM19
AJ21
AJ20
AK19
AK18
AE18
AD18
AN19
AN18
AG18
AF18
AP19
AP18
AJ18
AH18
3
C126
2_5V
10NF-0603SMT
10NF-0603SMT
+
10NF-0603SMT
C127
100NF-0603SMT
C139
4
C137
100NF-0603SMT
C128
10NF-0603SMT
C140
1_8V
1
2
1
1
1
1
1
1
1
1
C129
1
100NF-0603SMT
2_5V
C149
MemIntf_A[0:12]
100NF-0603SMT
C2
5
10NF-0603SMT
1
1
J2
J2
H2
H2
F2
F2
G2
G2
A2
100NF-0603SMT
1
J2
J2
H2
H2
G2
G2
F2
F2
D2
D2
B2
B2
A2
A2
C2
C2
E2
E2
E2
E2
D2
D2
B2
B2
20
A2
MemIntf_DQ[0:15]
10NF-0603SMT
C138
MemIntf_A[0:12]
C2
11
Rev
3.0
A
B
C
D
Lattice Semiconductor
LatticeSC PCI Express x4 Evaluation Board
User’s Guide
Figure 11. DDR2
21
A
5
J41
Johnson 142-0711-201
J43
Johnson 142-0711-201
J45
Johnson 142-0711-201
J47
Johnson 142-0711-201
LVDS_INP_2
LVDS_INN_2
LVDS_INP_3
LVDS_INN_3
1
1
1
1
R121
1K_ADJ/SMT3MM
R120
R119
LVDS_OUTP_2
LVDS_OUTN_2
LVDS_OUTP_3
LVDS_OUTN_3
1
1
1
1
PP60
LVDS_OUTN_1
1
4
BOURNS-3224W-202E-2K
R154
DP1
3
R155
OPEN-0603SMT
R153
100R-0603SMT
1
[9] OSC_IN_1
3
LVDS_INP_0
LVDS_INN_0
LVDS_INP_1
LVDS_INN_1
LVDS_INP_2
LVDS_INN_2
LVDS_INP_3
LVDS_INN_3
LVDS_PROBEP
LVDS_PROBEN
VREF_BANK7
LVDS_OUTP_3
LVDS_OUTN_3
VREF_BANK7
LVDS_OUTP_2
LVDS_OUTN_2
LVDS_OUTP_1
LVDS_OUTN_1
BANK7
U1D
LFSC
1152BGA
LFSC1152BGA
BANK6
LEFT
2
PL50A/PCLKT6_0
PL50B/PCLKC6_0
PL50C/PCLKT6_1
PL50D/PCLKC6_1
PL51A
PL51B
PL51C/PCLKT6_3
PL51D/PCLKC6_3
PL52A
PL52B
PL52C/PCLKT6_2
PL52D/PCLKC6_2
PL55A
PL55B
PL55C/VREF1_6
PL55D
PL56A
PL56B
PL56C
PL56D
PL57A
PL57B
PL57C
PL57D
PL59A
PL59B
PL60A
PL60B
PL60C
PL60D
PL61A
PL61B
PL63A
PL63B
PL63C
PL63D
PL64A
PL64B
PL65A
PL65B
PL65C
PL65D
PL67A
PL67B
PL68A
PL68B
PL69A
PL69B
PL76A
PL76B
PL76C
PL76D/DIFFR_6
PL77A
PL77B
PL77C
PL77D
PL78A
PL78B
PL78C
PL78D
PL80A
PL80B
PL80C
PL80D
PL81A
PL81B
PL81C
PL81D
PL82A
PL82B
PL82C
PL82D
PL84A
PL84B
PL84C
PL84D
PL85A
PL85B
PL85C
PL85D
PL86A
PL86B
PL86C
PL86D
PL89A
PL89B
PL89C
PL89D/VREF2_6
PL90A
PL90B
PL90C
PL90D
PL91A
PL91B
PL91C
PL91D
PL93A
PL93B
PL93C/LLC_DLLT_IN_E/LLC_DLLT_FB_F
PL93D/LLC_DLLC_IN_E/LLC_DLLC_FB_F
PL94A
PL94B
PL94C
PL94D
PL95A/LLC_DLLT_IN_F/LLC_DLLT_FB_E
PL95B/LLC_DLLC_IN_F/LLC_DLLC_FB_E
PL95C/LLC_PLLT_IN_B/LLC_PLLT_FB_A
PL95D/LLC_PLLC_IN_B/LLC_PLLC_FB_A
PL16A/ULC_PLLT_IN_A/ULC_PLLT_FB_B/DEBUG_BUS11
PL16B/ULC_PLLC_IN_A/ULC_PLLC_FB_B/DEBUG_BUS10
PL16C/DEBUG_BUS13
PL16D
PL17A/ULC_DLLT_IN_C/ULC_DLLT_FB_D/DEBUG_BUS9
PL17B/ULC_DLLC_IN_C/ULC_DLLC_FB_D/DEBUG_BUS8
PL17C/ULC_PLLT_IN_B/ULC_PLLT_FB_A
PL17D/ULC_PLLC_IN_B/ULC_PLLC_FB_A
PL18A/ULC_DLLT_IN_D/ULC_DLLT_FB_C
PL18B/ULC_DLLC_IN_D/ULC_DLLC_FB_C
PL18C/DEBUG_BUS12
PL18D/VREF2_7/DEBUG_BUS6
PL20A
PL20B
PL20C
PL20D
PL21A
PL21B
PL21C
PL21D
PL22A
PL22B
PL24A
PL24B
PL25A
PL25B
PL26A
PL26B
PL29A/TESTCFGN
PL29B/DEBUG_BUS7
PL29C/VREF1_7/DEBUG_BUS5
PL29D/DIFFR_7/DEBUG_BUS4
PL31A
PL31B
PL31C
PL31D
PL33A
PL33B
PL33C
PL33D
PL35A
PL35B
PL35C
PL35D
PL37A
PL37B
PL37C
PL37D
PL39A
PL39B
PL39C
PL39D
PL41A
PL41B
PL41C
PL41D
PL42A
PL42B
PL42C
PL42D
PL43A
PL43B
PL43C
PL43D
PL46A
PL46B
PL46C
PL46D
PL47A/PCLKT7_1/DEBUG_BUS3
PL47B/PCLKC7_1/DEBUG_BUS2
PL47C/PCLKT7_3
PL47D/PCLKC7_3
PL48A/PCLKT7_0/DEBUG_BUS1
PL48B/PCLKC7_0/DEBUG_BUS0
PL48C/PCLKT7_2/DEBUG_BUS14
PL48D/PCLKC7_2/DEBUG_BUS15
T32
T31
U29
V29
T30
U30
U27
V27
R34
T34
U28
V28
V30
W30
W27
Y27
T33
U33
V25
W25
U34
V34
V26
W26
W34
Y34
V33
W33
V24
W24
W32
Y32
W31
Y31
Y29
AA29
AA34
AB34
Y33
AA33
Y28
AA28
AC34
AD34
Y30
AA30
AB33
AC33
AB32
AC32
AA26
AA27
AB31
AC31
Y24
AA24
AE34
AF34
AB30
AC30
AD33
AE33
AD30
AE30
AE32
AF32
AA25
AB25
AJ34
AK34
AB27
AC27
AF33
AG33
AC29
AD29
AE31
AF31
AF30
AF29
AH33
AJ33
AC28
AD28
AH32
AJ32
AD27
AE27
AG34
AH34
AC26
AB26
AK33
AL33
AG30
AH30
AL34
AM34
AJ30
AK30
AJ31
AH31
AD26
AD25
AL32
AL31
AG29
AG28
12
4 RN5D
8
9
13
3 RN7C
4 RN6D
5 RN6E
13
12
TP_01
TP_02
TP_03
TP_04
TP_05
TP_06
TP_07
TP_08
TP_09
TP_10
TP_11
TP_12
TP_13
TP_14
TP_15
TP_16
6
2 RN6B
15
EXB2HV121JV
150R 14
Date:
Size
C
D20
18
1
Debug Testpoints
2_5V
1
Sheet
7
SC80 X4 PCI EXPRESS Card
Project
Differential I/O Test SMAs
TP18
TP19
TP20
TP21
TP22
TP23
TP24
TP25
TP26
TP27
TP28
TP29
TP30
TP31
TP32
TP33
LTP-587HR/16-SEGMENT
2
8 RN6H
9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
7 RN6G
10
16
5
6 RN6F
4
1 RN6A
11
3
8 RN5H
9
16
15
17
5 RN5E
10
7 RN5G
6 RN5F
12
11
Title
7
11
3 RN5C
13
14
14
10
R159
150R-0603SMT
13
4 RN7D
EXB2HV121JV
150R
15
2 RN4B
A
B
J39
Johnson 142-0711-201
LVDS_INN_1
1
LVDS_OUTP_1
1
LVDS_OUTP_0
LVDS_OUTN_0
OSC_IN_1
F30
G30
H28
J28
F31
G31
N25
P25
D33
E33
H29
J29
F32
G32
P26
N26
H30
J30
L28
M28
E34
F34
F33
G33
K30
L30
G34
H34
J31
K31
L27
M27
J32
K32
L29
M29
H33
J33
N27
P27
K33
L33
M30
N30
M31
N31
P24
R24
M32
N32
P28
R28
J34
K34
P30
R30
M33
N33
U25
T25
L34
M34
P29
R29
N34
P34
R27
T27
R32
R31
U24
T24
P33
R33
T26
U26
B
VREF_BANK7
J34
Johnson 142-0711-201
LVDS_INP_1
1
LVDS_OUTN_0
1
2
C
2_5V
J32
Johnson 142-0711-201
LVDS_INN_0
1
LVDS_OUTP_0
1
1
3
D
J46
Johnson 142-0711-201
J44
Johnson 142-0711-201
J42
Johnson 142-0711-201
J40
Johnson 142-0711-201
J35
Johnson 142-0711-201
J33
Johnson 142-0711-201
J37
Johnson 142-0711-201
LVDS_INP_0
1
4
E
C
D
J38
Johnson 142-0711-201
J36
Johnson 142-0711-201
2
2
2
2
2
2
2
2
2
2
2
2
R114
100R-0603SMT
R116
100R-0603SMT
R117
100R-0603SMT
5
F
2
G
1K-0603SMT
H
C156
K
1K-0603SMT
M
10NF-0603SMT
N
2
P
2
R
2
S
R118
100R-0603SMT
T
2
U
R115
1_1K-0603SMT
DP
2
of
11
Rev
3.0
A
B
C
D
Lattice Semiconductor
LatticeSC PCI Express x4 Evaluation Board
User’s Guide
Figure 12. Differential I/O Test SMAs
22
A
B
C
5
R128
1K_ADJ/SMT3MM
R127
R126
2_5V
R123
1K_ADJ/SMT3MM
R124
R122
VREF_BANK3
VREF_BANK2
PP62
PP61
J48
Johnson 142-0711-201
1
4
R166
4
J49
Johnson 142-0711-201
51R-0603SMT
[5] PCIE_CLKP
[5] PCIE_CLKN
LA1
LA3
LA5
LA7
LA9
LA11
LA13
LA15
LA17
LA19
LA21
LA23
LA25
LA27
LA29
LA31
LA33
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
2_767004
5V SCL
GND SDA
CLK1 CLK
8
7
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
38
37
LA1
[9] OSC_IN_2
[5] 1_CREFCLK[5] 1_CREFCLK+
R167
1
R125
1_1K-0603SMT
2_5V
C157
C158
1K-0603SMT
1K-0603SMT
1K-0603SMT
1K-0603SMT
10NF-0603SMT
10NF-0603SMT
1
2
1
2
D
5
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
LOOP_P0
LOOP_N0
1_CREFCLK1_CREFCLK+
LOOP_P1
LOOP_N1
OSC_IN_2
LOOP_P15
LOOP_N15
LOOP_P14
LOOP_N14
LOOP_P13
LOOP_N13
LOOP_P12
LOOP_N12
LOOP_P11
LOOP_N11
LOOP_P10
LOOP_N10
LOOP_P9
LOOP_N9
LOOP_P8
LOOP_N8
LOOP_P7
LOOP_N7
LOOP_P6
LOOP_N6
VREF_BANK2
LOOP_P5
LOOP_N5
LOOP_P4
LOOP_N4
LOOP_P3
LOOP_N3
VREF_BANK2
LOOP_P2
LOOP_N2
LOOP_P1
LOOP_N1
LOOP_P0
LOOP_N0
PLL_CLK_INP
PLL_CLK_INN
LA2
LA4
LA6
LA8
LA10
LA12
LA14
LA16
LA18
LA20
LA22
LA24
LA26
LA28
LA30
LA32
LA34
3
3
F5
G5
H7
J7
F4
G4
N10
P10
D2
E2
H6
J6
F3
G3
P9
N9
H5
J5
L7
M7
E1
F1
F2
G2
K5
L5
G1
H1
J4
K4
L8
M8
J3
K3
L6
M6
H2
J2
N8
P8
K2
L2
M5
N5
M4
N4
P11
R11
M3
N3
P7
R7
J1
K1
P5
R5
M2
N2
U10
T10
L1
M1
P6
R6
N1
P1
R8
T8
R3
R4
U11
T11
P2
R2
T9
U9
BANK2
U1K
LFSC1152BGA
RIGHT
BANK3
2
PR50A/PCLKT3_0
PR50B/PCLKC3_0
PR50C/PCLKT3_1
PR50D/PCLKC3_1
PR51A
PR51B
PR51C/PCLKT3_3
PR51D/PCLKC3_3
PR52A
PR52B
PR52C/PCLKT3_2
PR52D/PCLKC3_2
PR55A
PR55B
PR55C/VREF1_3
PR55D
PR56A
PR56B
PR56C
PR56D
PR57A
PR57B
PR57C
PR57D
PR59A
PR59B
PR60A
PR60B
PR60C
PR60D
PR61A
PR61B
PR63A
PR63B
PR63C
PR63D
PR64A
PR64B
PR65A
PR65B
PR65C
PR65D
PR67A
PR67B
PR68A
PR68B
PR69A
PR69B
PR76A
PR76B
PR76C
PR76D/DIFFR_3
PR77A
PR77B
PR77C
PR77D
PR78A
PR78B
PR78C
PR78D
PR80A
PR80B
PR80C
PR80D
PR81A
PR81B
PR81C
PR81D
PR82A
PR82B
PR82C
PR82D
PR84A
PR84B
PR84C
PR84D
PR85A
PR85B
PR85C
PR85D
PR86A
PR86B
PR86C
PR86D
PR89A
PR89B
PR89C
PR89D/VREF2_3
PR90A
PR90B
PR90C
PR90D
PR91A
PR91B
PR91C
PR91D
PR93A
PR93B
PR93C/LRC_DLLT_IN_E/LRC_DLLT_FB_F
PR93D/LRC_DLLC_IN_E/LRC_DLLC_FB_F
PR94A
PR94B
PR94C
PR94D
PR95A/LRC_DLLT_IN_F/LRC_DLLT_FB_E
PR95B/LRC_DLLC_IN_F/LRC_DLLC_FB_E
PR95C/LRC_PLLT_IN_B/LRC_PLLT_FB_A
PR95D/LRC_PLLC_IN_B/LRC_PLLC_FB_A
LFSC
1152BGA
PR16A/URC_PLLT_IN_A/URC_PLLT_FB_B
PR16B/URC_PLLC_IN_A/URC_PLLC_FB_B
PR16C
PR16D
PR17A/URC_DLLT_IN_C/URC_DLLT_FB_D
PR17B/URC_DLLC_IN_C/URC_DLLC_FB_D
PR17C/URC_PLLT_IN_B/URC_PLLT_FB_A
PR17D/URC_PLLC_IN_B/URC_PLLC_FB_A
PR18A/URC_DLLT_IN_D/URC_DLLT_FB_C
PR18B/URC_DLLC_IN_D/URC_DLLC_FB_C
PR18C
PR18D/VREF2_2
PR20A
PR20B
PR20C
PR20D
PR21A
PR21B
PR21C
PR21D
PR22A
PR22B
PR24A
PR24B
PR25A
PR25B
PR26A
PR26B
PR29A
PR29B
PR29C/VREF1_2
PR29D/DIFFR_2
PR31A
PR31B
PR31C
PR31D
PR33A
PR33B
PR33C
PR33D
PR35A
PR35B
PR35C
PR35D
PR37A
PR37B
PR37C
PR37D
PR39A
PR39B
PR39C
PR39D
PR41A
PR41B
PR41C
PR41D
PR42A
PR42B
PR42C
PR42D
PR43A
PR43B
PR43C
PR43D
PR46A
PR46B
PR46C
PR46D
PR47A/PCLKT2_1
PR47B/PCLKC2_1
PR47C/PCLKT2_3
PR47D/PCLKC2_3
PR48A/PCLKT2_0
PR48B/PCLKC2_0
PR48C/PCLKT2_2
PR48D/PCLKC2_2
2
T3
T4
U6
V6
T5
U5
U8
V8
R1
T1
U7
V7
V5
W5
W8
Y8
T2
U2
V10
W10
U1
V1
V9
W9
W1
Y1
V2
W2
V11
W11
W3
Y3
W4
Y4
Y6
AA6
AA1
AB1
Y2
AA2
Y7
AA7
AC1
AD1
Y5
AA5
AB2
AC2
AB3
AC3
AA9
AA8
AB4
AC4
Y11
AA11
AE1
AF1
AB5
AC5
AD2
AE2
AD5
AE5
AE3
AF3
AA10
AB10
AJ1
AK1
AB8
AC8
AF2
AG2
AC6
AD6
AE4
AF4
AF5
AF6
AH2
AJ2
AC7
AD7
AH3
AJ3
AD8
AE8
AG1
AH1
AC9
AB9
AK2
AL2
AG5
AH5
AL1
AM1
AJ5
AK5
AJ4
AH4
AD9
AD10
AL3
AL4
AG6
AG7
VREF_BANK3
LA1
LA2
LA3
LA4
LA5
LA6
LA7
LA8
LA9
LA10
LA11
LA12
LA13
LA14
LA15
LA16
LA17
LA18
LA19
LA20
LA21
LA22
LA23
LA24
LA25
LA26
LA27
LA28
LA29
LA30
LA31
LA32
LA33
LA34
LOOP_P14
LOOP_N14
LOOP_P15
LOOP_N15
LOOP_P12
LOOP_N12
LOOP_P13
LOOP_N13
LOOP_P10
LOOP_N10
LOOP_P11
LOOP_N11
LOOP_P8
LOOP_N8
LOOP_P9
LOOP_N9
LOOP_P7
LOOP_N7
LOOP_P6
LOOP_N6
LOOP_P4
LOOP_N4
2_CREFCLK2_CREFCLK+
LOOP_P5
LOOP_N5
VREF_BANK3
LOOP_P2
LOOP_N2
PCLK_CLK_INP
PCLK_CLK_INN
LOOP_P3
LOOP_N3
R129
1_1K-0603SMT
Date:
Size
C
Title
1
2
[5]
[5]
Differential I/O Loops
51R-0603SMT
2
1
Sheet
8
SC80 X4 PCI EXPRESS Card
Project
51R-0603SMT
1
J51
Johnson 142-0711-201
R168
2_CREFCLK2_CREFCLK+
R169
1
of
11
Rev
3.0
J50
Johnson 142-0711-201
A
B
C
D
Lattice Semiconductor
LatticeSC PCI Express x4 Evaluation Board
User’s Guide
Figure 13. Differential I/O Loops
2
51R-0603SMT
2
A
B
C
D
5
1
1
R134
1_6R-0603SMT
C162
3_3V
JUMPER1
J101
1_6R-0603SMT
C505
R205
2
J102
HEADER 2X1
100NF-0603SMT
3_3V
JUMPER1
J109
2
J108
HEADER 2X1
C504
+
+
2
1
2
1
100NF-0603SMT
NC
DIS#
6
NC
DIS#
14
Q_N
Q
Q
Q
Q_N
Q_N
4
J110
Johnson 142-0711-201
5
1
8
1
R214
4
B_OSC_P
B_OSC_N
R208
J111
Johnson 142-0711-201
82R-0603SMT
R211
R183
J92
Johnson 142-0711-201
R207
130R-0603SMT
3_3V
51R-0603SMT
R210
82R-0603SMT
3_3V
51R-0603SMT
R206
130R-0603SMT
1
A_OSC_N
82R-0603SMT
R138
A_OSC_P
R136
130R-0603SMT
3_3V
4
R143
3_3V
R137
82R-0603SMT
Y4
110-93-314-41-001
Y5
CW-P423F-312.5MHZ
Q
1
8
J91
Johnson 142-0711-201
5
4
Y3
CW-P423F-312.5MHZ
Q_N
R135
130R-0603SMT
Y1
110-93-314-41-001
VDD
GND
C161
1
2
1
2
100NF-0603SMT
1
2
1
2
10UF-16V_TANTBSMT
10UF-16V_TANTBSMT
C163
C506
VCC
GND
3
100NF-0603SMT
6
VCC
GND
3
1
R144
0R-0603SMT
51R-0603SMT
R215
R212
OPEN-0603SMT
R209
51R-0603SMT
0R-0603SMT
1
OPEN-0603SMT
R181
0R-0603SMT
R184
OPEN-0603SMT
2
5
3
[5]
[5]
A_REFCLKP_L
A_REFCLKN_L
[5]
B_REFCLKN_L
R213
OPEN-0603SMT
R182
0R-0603SMT
[5]
B_REFCLKP_L
3
[7] OSC_IN_1
[8] OSC_IN_2
100NF-0603SMT
C165
2
[5] A_RXREFCLK_L
OSC_IN_1
OSC_IN_2
3_3V
2
GND
N/C
CY2304-1
REF
FBK
CLKA1 VDD
CLKA2 CLKB2
GND CLKB1
U20
Y2
OUT
Vcc
8
7
6
5
2
1
51R-0603SMT
1
J99
Johnson 142-0711-201
R157
1
2
3
4
3
4
CTS-CB3LV-3C-100.00MHZ
2
7
14
VDD
GND
7
2
2
23
2
Date:
Size
C
Title
RX_REFCLK
10NF-0603SMT
100NF-0603SMT
1
Sheet
9
SC80 X4 PCI EXPRESS Card
Project
FLASH_CLK [11]
OSC_IN_4 [2]
C167
C166
Clocks
OSC_IN_4
3_3V
1
of
11
Rev
3.0
A
B
C
D
Lattice Semiconductor
LatticeSC PCI Express x4 Evaluation Board
User’s Guide
Figure 14. Clocks
24
A
B
C
D
K26
K9
V12
AC18
U23
M17
K23
K20
J15
L12
F19
G16
D18
C17
AP33
AP2
AN34
AN1
AM8
AL5
AM30
AL27
AM24
AL21
AM18
AL17
AM14
AL11
AK31
AK3
AJ28
AH25
AJ22
AH19
AJ16
AH13
AJ10
AH7
AG32
AG4
AF26
AD23
AF20
AE15
AE12
AE9
AE29
AE7
AD31
AD3
AC25
AC11
AB28
AB6
AA32
AA20
AA15
AA4
Y25
Y19
Y16
Y9
W29
W20
W18
W17
W15
W7
V31
Y21
V19
V16
Y14
V3
U32
R21
U19
U16
R14
U4
T28
T20
T18
T17
T15
T6
R26
R19
R16
R10
P31
P20
P15
P3
N29
N7
M24
M10
L32
L4
K28
K6
J26
J10
H31
H3
G29
G7
E32
E4
C31
C30
C27
C26
C24
C23
C22
C21
C14
C13
C12
C11
C9
C8
C5
C4
B34
B1
A33
A2
U1E
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
M HOLE2
M HOLE2
5
MH2
MH1
LFSC1152BGA
VSS
LFSC
1152BGA
5
M HOLE2
MH3
VCCIO7
VCCIO6
VCCIO3
VCCIO2
VCCIO1
VCCAUX
VCC12
VDDTX
VDDRX
VDDP
VDDOB
VCC CORE
C171
C172
C173
C174
C175
C176
C177
C178
C179
C180
C181
C182
C183
C184
C196
C197
C198
C199
C200
C201
C202
C203
C204
C205
C206
C207
C208
C209
C210
C211
C223
C224
C225
C226
C227
C228
C229
C230
C231
C232
C233
C234
C435
C434
C432
C249
C250
22PF-0402SMT
C251
C253
1000PF-0402SMT
C274
C252
2_5V
C254
C255
C256
VDDAX25
22PF-0402SMT
C277
C257
C258
C259
C260
C438
C437
C436
C262
C263
C264
C265
C266
C267
C268
C269
C270
C271
C272
C273
C441
C440
C439
C288
C289
C290
C291
C292
C293
C294
C295
C296
C297
C298
C299
C429
C428
C427
C185
C186
C187
C188
C189
2
C190
C191
C192
C193
C194
C301
C302
C303
C304
C305
C306
C307
C308
C309
C310
C311
C312
C313
C314
C315
C316
C317
C318
HSTL
VTT
C50
SC_VTT
C57
C67
C430
C431
NC1
NC2
NC3
NC4
A1
A34
AP1
AP34
C319
C320
C321
NO CONNECT
DEVICE PINS
LFSC1152BGA
U1G
C322
C323
C324
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
C433
C325
C326
C411
C422
C423
1
C424
C426
C425
C328
C329
C330
C331
C332
C333
C334
C335
C336
C352
C353
C354
C355
C356
C357
C358
C359
C383
C376
C384
C377
C385
C386
2_5V
C378
C387
C388
C379
C389
C364
C365
C366
C367
C368
C369
2_5V
C370
C371
C372
C373
C374
C380
C381
C390
C391
C392
C393
4
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
C375
2_5V
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
C363
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
C382
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
C351
2_5V
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
C327
2_5V
3
C400
C401
C402
C403
C404
C405
1_8V
C406
C407
C408
C409
C410
C340
C341
C342
C343
C344
1_8V
C345
C346
C347
C348
C349
C350
2
Date:
Size
C
Title
1
Sheet
10
SC80 X4 PCI EXPRESS Card
Project
VSS/Decoupling
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
C339
VCCIO5
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
C399
VCCIO4
of
11
Rev
3.0
1000PF-0402SMT 1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT 1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
C300
2_5V
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT 1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT 1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
C287
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT 1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT 1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
C261
VDDTX
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT 1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT 1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
C248
VDDRX
1000PF-0402SMT
C235
C238
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT 1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT 1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
C222
VDDP
1_2V
C170
1000PF-0402SMT
1000PF-0402SMT 1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT 1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
C195
VCC_CORE
1_5V
C169
ALL CAPS PLACED UNDER BGA
3
1000PF-0402SMT
1000PF-0402SMT 1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT 1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
C168
VCC_CORE
4
A
B
C
D
Lattice Semiconductor
LatticeSC PCI Express x4 Evaluation Board
User’s Guide
Figure 15. VSS Decoupling
A
B
C
2_5V
JUMPER1
3
4
2
5
Momentary Switch
B3F-1150
1
SW9
CPLD RESET
1
J112
R218
1K-0603SMT
2
J113
HEADER 2X1
R217
2_2K-0603SMT
3_3V
[2] DATA[0..7]
1
2
GSRN
3_3V
DONE
INITN
[2] TCK
[2] TDI_XO
[2] TDO_XO
[2] TMS_XO
[2]
[2]
[2]
[2] PROGRAMN
[2] LOADER_CK
R216
4_7K-0603SMT
R219
1K-0603SMT
TCK
TDI_XO
TDO_XO
TMS_XO
4
M1
P13
P10
N7
N8
P11
N13
N1
N3
N4
P1
M12
M2
M3
M4
M6
M7
B1
L3
A3
A2
M9
N12
P4
M5
N5
P3
K12
N14
A4
DONE
GSRN
A1
J2
H2
G1
A5
P8
M8
J3
K1
E3
B7
P5
INITN
PROGRAMN
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
LOADER_CK
4
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
SLEEPN
TCK
TDI
TDO
TMS
FUNC_RESET
FPGA_RESETN
FPGA_DONE
FPGA_INITN
TSALL
FPGA_PROGRAMN
FPGA_DATA_0
FPGA_DATA_1
FPGA_DATA_2
FPGA_DATA_3
FPGA_DATA_4
FPGA_DATA_5
FPGA_DATA_6
FPGA_DATA_7
FPGA_CCLK
U26
C511
C512
10NF-0603SMT
P7
100NF-0603SMT
C5
3_3V
C513
100NF-0603SMT
LCMXO1200C-CSBGA132
Lattice
FPGA
Loader
N2
D
5
A10
1
2
C517
100NF-0603SMT
G12
VCC
C7
VCC
H3
VCC
GND
A7
VCCAUX
P6
VCC
GND
B4
VCCAUX
GND
D13
GND
E1
GND
F1
GND
J14
GND
C9
VCCIO0
B11
VCCIO1
E12
VCCIO2
L12
VCCIO3
GND
L2
C514
3
3
FLASH_ADDRESS_0
FLASH_ADDRESS_1
FLASH_ADDRESS_2
FLASH_ADDRESS_3
FLASH_ADDRESS_4
FLASH_ADDRESS_5
FLASH_ADDRESS_6
FLASH_ADDRESS_7
FLASH_ADDRESS_8
FLASH_ADDRESS_9
FLASH_ADDRESS_10
FLASH_ADDRESS_11
FLASH_ADDRESS_12
FLASH_ADDRESS_13
FLASH_ADDRESS_14
FLASH_ADDRESS_15
FLASH_ADDRESS_16
FLASH_ADDRESS_17
FLASH_ADDRESS_18
FLASH_ADDRESS_19
FLASH_ADDRESS_20
FLASH_ADDRESS_21
FLASH_DQ_31
FLASH_DQ_30
FLASH_DQ_29
FLASH_DQ_28
FLASH_DQ_27
FLASH_DQ_26
FLASH_DQ_25
FLASH_DQ_24
FLASH_DQ_23
FLASH_DQ_22
FLASH_DQ_21
FLASH_DQ_20
FLASH_DQ_19
FLASH_DQ_18
FLASH_DQ_17
FLASH_DQ_16
FLASH_DQ_15
FLASH_DQ_14
FLASH_DQ_13
FLASH_DQ_12
FLASH_DQ_11
FLASH_DQ_10
FLASH_DQ_9
FLASH_DQ_8
FLASH_DQ_7
FLASH_DQ_6
FLASH_DQ_5
FLASH_DQ_4
FLASH_DQ_3
FLASH_DQ_2
FLASH_DQ_1
FLASH_DQ_0
CLOCK
FLASH_WE_N
FLASH_WP_N
FLASH_RESET_N
FLASH_OE_N
FLASH_CE_N
FLASH_RD/BY
FLASH_ADV_N
FLASH_CE1_N
FLASH_CE0_N
10NF-0603SMT
K3
VCCIO6
D2
VCCIO7
M10
VCCIO4
GND
L13
VCCIO5
GND
N11
GND
P2
GND
P9
B6
A6
B3
B5
A9
B9
C10
B10
C11
A11
D14
C8
A14
B8
C14
B12
C13
A13
B13
A12
C12
B14
F12
H14
N10
N6
M14
M13
H13
H12
C6
C2
K14
P12
L14
M11
G2
E2
E14
D12
J12
G14
J13
F14
F13
E13
D3
C4
J1
H1
N9
K13
G13
G3
A8
K2
L1
P14
C1
B2
D1
F2
F3
C3
FLASH_D31
FLASH_D30
FLASH_D29
FLASH_D28
FLASH_D27
FLASH_D26
FLASH_D25
FLASH_D24
FLASH_D23
FLASH_D22
FLASH_D21
FLASH_D20
FLASH_D19
FLASH_D18
FLASH_D17
FLASH_D16
FLASH_D15
FLASH_D14
FLASH_D13
FLASH_D12
FLASH_D11
FLASH_D10
FLASH_D9
FLASH_D8
FLASH_D7
FLASH_D6
FLASH_D5
FLASH_D4
FLASH_D3
FLASH_D2
FLASH_D1
FLASH_D0
FLASH_CLK
FLASH_WE_N
FLASH_WP_N
FLASH_RESET_N
FLASH_OE_N
FLASH_CE_N
FLASH_RD/BY
FLASH_ADV_N
FLASH_IND/WAITN
FLASH_CLK_INPUT
FLASH_A0
FLASH_A1
FLASH_A2
FLASH_A3
FLASH_A4
FLASH_A5
FLASH_A6
FLASH_A7
FLASH_A8
FLASH_A9
FLASH_A10
FLASH_A11
FLASH_A12
FLASH_A13
FLASH_A14
FLASH_A15
FLASH_A16
FLASH_A17
FLASH_A18
FLASH_A19
FLASH_CLK
[9]
2_5V
R220
1K-0603SMT
2_5V
FLASH_A[0..19]
1
C516
JUMPER1
J115
2
12_0V
J114
HEADER 3X1
FLASH_RD/BY
FLASH_WP_N
FLASH_WE_N
A4
F5
H4
K6
J3
J6
FLASH_ADV_N
J5
FLASH_CE_N
FLASH_OE_N
J7
D3
C2
C1
B1
A1
A2
B2
B3
C3
C4
B4
B5
C6
A6
B6
B7
A7
A8
B8
C8
10NF-0603SMT
FLASH_IND/WAITN
FLASH_A19
FLASH_A18
FLASH_A17
FLASH_A16
FLASH_A15
FLASH_A14
FLASH_A13
FLASH_A12
FLASH_A11
FLASH_A10
FLASH_A9
FLASH_A8
FLASH_A7
FLASH_A6
FLASH_A5
FLASH_A4
FLASH_A3
FLASH_A2
FLASH_A1
FLASH_A0
100NF-0603SMT
C515
2
2
1
1
3
3
2
2
U23
ACC
RY/BY#
WP#
WE#
ADV#
OE#
CE#
IND/WAIT#
A19/NC
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
K1
G1
G8
E8
E1
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
2_5V
K5
A3
VCC
VCC
VSS
VSS
VSS
VSS
C7
K8
MCH
MCH
NC
NC
NC
NC
NC
K7
C5
D4
D5
J4
25
F1
A5
K4
F8
C507
C508
Date:
Size
C
C509
1
Sheet
11
SC80 X4 PCI EXPRESS Card
Project
C510
10NF-0603SMT
FLASH_D[0..31]
100NF-0603SMT
Parallel Flash
FLASH_RESET_N
Title
FLASH_CLK_INPUT
K2
FLASH_D31
FLASH_D30
FLASH_D29
FLASH_D28
FLASH_D27
FLASH_D26
FLASH_D25
FLASH_D24
FLASH_D23
FLASH_D22
FLASH_D21
FLASH_D20
FLASH_D19
FLASH_D18
FLASH_D17
FLASH_D16
FLASH_D15
FLASH_D14
FLASH_D13
FLASH_D12
FLASH_D11
FLASH_D10
FLASH_D9
FLASH_D8
FLASH_D7
FLASH_D6
FLASH_D5
FLASH_D4
FLASH_D3
FLASH_D2
FLASH_D1
FLASH_D0
10NF-0603SMT
K3
D6
D7
D8
E6
E5
E7
F6
F7
G7
G5
G6
H8
H6
H7
H5
J8
J1
J2
H1
H2
H3
G3
G4
G2
F2
F3
F4
E2
D1
E3
E4
D2
29CD032G
RST#
CLK
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
100NF-0603SMT
1
of
11
Rev
3.0
A
B
C
D
Lattice Semiconductor
LatticeSC PCI Express x4 Evaluation Board
User’s Guide
Figure 16. Parallel Flash