A3969: Dual Full-Bridge PWM Motor Driver

A3969
Dual Full-Bridge PWM Motor Driver
Last Time Buy
This part is in production but has been determined to be
LAST TIME BUY. This classification indicates that the product is
obsolete and notice has been given. Sale of this device is currently
restricted to existing customer applications. The device should not be
purchased for new design applications because of obsolescence in the
near future. Samples are no longer available.
Date of status change: November 1, 2010
Deadline for receipt of LAST TIME BUY orders: April 30, 2011
Recommended Substitutions:
For existing customer transition, and for new customers or new applications, contact Allegro Sales.
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
A3969
Dual Full-Bridge PWM Motor Driver
Features and Benefits
Description
▪
▪
▪
▪
▪
▪
▪
▪
The A3969 is designed to drive both windings of a two-phase
bipolar stepper motor. The device includes two H-bridges
capable of continuous output currents of ±650 mA and operating
voltages to 30 V. Motor winding current can be controlled by
the internal fixed-frequency, pulse-width modulated (PWM),
current-control circuitry. The peak load current limit is set by
the user’s selection of a reference voltage and current-sensing
resistors.
±650 mA continuous output current
30 V output voltage rating
Internal fixed-frequency PWM current control
Satlington® sink drivers
User-selectable blanking window
Internal ground-clamp and flyback diodes
Internal thermal-shutdown circuitry
Crossover-current protection and UVLO protection
The fixed-frequency pulse duration is set by a user-selected
external RC timing network. The capacitor in the RC timing
network also determines a user-selectable blanking window that
prevents false triggering of the PWM current-control circuitry
during switching transitions.
To reduce on-chip power dissipation, the H-bridge power
outputs have been optimized for low saturation voltages. The
sink drivers feature the Allegro® patented Satlington® output
structure. The Satlington outputs combine the low voltage drop
of a saturated transistor and the high peak current capability
of a Darlington.
Package: 28 pin QFN (suffix ET)
Continued on the next page…
Approximate scale
Typical Application
+3.3 V
+24 V
+3.3 V
20 kΩ
10 kΩ
680 pF
56 kΩ
0.5 Ω
22
23
24
25
26
27
28
47 μF
1
21
2
20
3
19
4
18
LOGIC
LOGIC
17
5
DS3969, Rev. 2
14
13
12
10
7
11
VBB
8
PH2
6
9
EN2
0.5 Ω
16
EN1
15
PH1
A3969
Dual Full-Bridge PWM Motor Driver
Description (continued)
For each bridge, a PHASE input controls load-current polarity by
selecting the appropriate source and sink driver pair. For each
bridge, an ENABLE input, when held high, disables the output
drivers. Special power-up sequencing is not required. Internal circuit
protection includes thermal shutdown with hysteresis, ground-clamp
and flyback diodes, and crossover-current protection.
The A3969 is supplied in a 28-pin QFN lead (Pb) free plastic package
with exposed thermal pad and 100% matte tin leadframe plating. It
has a 5 x 5 mm footprint and 0.90 mm nominal height.
Selection Guide
Part Number
A3969SETTR-T
Packing*
Tape, 3000 pieces/reel
*Contact Allegro for additional packing options
Package
5 x 5 mm QFN, 28 pin
Absolute Maximum Ratings
Characteristic
Load Supply Voltage
Symbol
Notes
Rating
Units
30
V
Peak
±750
mA
Continuous. Output current rating may be limited by duty
cycle, ambient temperature, and heat sinking. Under any set
of conditions, do not exceed the specified current rating or a
junction temperature of 150°C.
±650
mA
VBB
Output Current
IOUT
Logic Supply Voltage
VCC
7
V
Input Voltage
Vin
-0.3 to
VCC + 0.3
V
0.45
V
Sense Voltage
VS
Operating Ambient Temperature
TA
–20 to 85
ºC
Maximum Junction Temperature
TJ(max)
150
ºC
Tstg
–55 to 150
ºC
Storage Temperature
Range S
Thermal Characteristics* (additional data available on Allegro Web site)
Characteristic
Symbol
Package Thermal Resistance, Junction-to-Ambient
RθJA
Package Thermal Resistance, Junction-to-Tab
RθJT
Package Power Dissipation
PD(max)
Notes
Rating
4-layer PCB, based on JEDEC standard
RθJA = 32 °C/W, TA = 25°C
Units
32
°C/W
2
°C/W
3.9
W
* Per SEMI G42-88 Specification, Thermal Test Board Standardization for Measuring Junction-to-Ambient Thermal Resistance of Semiconductor
Packages.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
2
A3969
Dual Full-Bridge PWM Motor Driver
Functional Block Diagram
VCC
OUT 1A
OUT 2B
OUT 2A
OUT1B
VBB
PH1
PH2
CONTROL LOGIC1
UVLO
& TSD
CONTROL LOGIC2
V BB
EN1
UVLO
& TSD
PWM LATCH 1
BLANKING
GATE 1
R
CURRENT-SENSE
COMPARATOR 2
+
–
+
–
BLANKING
GATE 2
PWM LATCH 2
R
Q
SOURCE
ENABLE 2
SOURCE
ENABLE 1
EN2
CURRENT-SENSE
COMPARATOR 1
Q
S
S
÷4
GND
OSC
SENSE 1
REF
Dwg. FP-036-7
22 VBB
23 NC
25 RC
R2S
26 VCC
27 NC
28 OUT2B
CT
NC
1
21 OUT1B
SENSE2
2
20 NC
NC
3
19 SENSE1
GND
4
NC
5
EN2
6
PH2
7
18 NC
LOGIC
LOGIC
17 GND
16 EN1
NC 14
OUT1A 13
15 PH1
NC 12
GND 11
9
NC 10
8
VBB
NC
Pin-out Diagram
SENSE 2
R1S
OUT2A
RT
24 REF
RC
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
3
A3969
Dual Full-Bridge PWM Motor Driver
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 30 V, VCC = 3.0 V to 3.6 V, VREF = 1.7 V,
VS = 0 V, 56 kΩ and 680 pF RC to Ground (unless noted otherwise)
Limits
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Units
Operating, IOUT = ±650 mA, L = 3 mH
5
—
30
V
Output Drivers
Load Supply Voltage Range
VBB
Output Leakage Current
ICEX
Output Saturation Voltage
Clamp Diode Forward Voltage
Motor Supply Current
(No Load)
VCE(SAT)
VF
IBB(ON)
IBB(OFF)
VOUT = 30 V
—
<1.0
50
μA
VOUT = 0 V
—
<-1.0
-50
μA
Source Driver, IOUT = -400 mA
—
1.7
2.0
V
Source Driver, IOUT = -650 mA
—
1.8
2.1
V
Sink Driver, IOUT = +400 mA, VS = 0.425 V
—
0.3
0.5
V
Sink Driver, IOUT = +650 mA, VS = 0.425 V
—
0.7
1.3
V
IF = 400 mA
—
1.1
1.4
V
IF = 650 mA
—
1.4
1.6
V
VENABLE1 = VENABLE2 = 0.8 V
—
3.0
5.0
mA
VENABLE1 = VENABLE2 = 2.4 V
—
<1.0
200
μA
3.00
—
3.60
V
2.4
—
—
V
Control Logic
Logic Supply Voltage Range
VCC
Logic Input Voltage
VIN(1)
Operating
VIN(0)
—
—
0.8
V
IIN(1)
VIN = 2.4 V
—
<1.0
20
μA
IIN(0)
VIN = 0.8 V
—
<-20
-200
μA
Reference Input Volt. Range
VREF
Operating
0.1
–
1.7
V
Reference Input Current
IREF
-2.5
0
1.0
μA
Reference Divider Ratio
VREF/
VTRIP
3.8
4.0
4.2
—
Logic Input Current
Current-Sense Comparator
Input Offset Voltage
VIO
VREF = 0 V
-6.0
0
6.0
mV
Current-Sense Comparator
Input Voltage Range
VS
Operating
-0.3
—
0.425
V
Sense-Current Offset
ISO
IS – IOUT, 50 mA  IOUT  650 mA
12
18
24
mA
NOTES:
1. Typical Data is for design information only.
2. Negative current is defined as coming out of (sourcing) the specified device terminal.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
4
A3969
Dual Full-Bridge PWM Motor Driver
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 30 V, VCC = 3.0 V to 3.6 V, VREF = 1.7 V,
VS = 0 V, 56 kΩ and 680 pF RC to Ground (unless noted otherwise) (cont.)
Limits
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Units
22.9
25.4
27.9
kHz
—
1.0
1.4
μs
Control Logic (continued)
PWM RC Frequency
fosc
CT = 680 pF, RT = 56 k
PWM Propagation Delay Time
tPWM
Comparator Trip to Source OFF
Cycle Reset to Source ON
—
0.8
1.2
μs
Cross-Over Dead Time
tcodt
100  Load to 15 V
0.2
1.3
3.0
μs
Propagation Delay Times
tpd
IOUT = ±650 mA, 50% to 50%; VBB = 15 V:
ENABLE ON to Source ON
—
125
—
ns
ENABLE OFF to Source OFF
—
500
—
ns
ENABLE ON to Sink ON
—
200
—
ns
Thermal Shutdown Temp.
Thermal Shutdown Hysteresis
UVLO Enable Threshold
UVLO Hysteresis
Logic Supply Current
ENABLE OFF to Sink OFF
—
200
—
ns
PHASE Change to Sink ON
—
1500
—
ns
PHASE Change to Sink OFF
—
200
—
ns
PHASE Change to Source ON
—
1500
—
ns
PHASE Change to Source OFF
—
200
—
ns
TJ
—
165
—
°C
TJ
—
15
—
°C
—
2.75
3.0
V
VT(UVLO)+
Increasing VCC
0.07
0.10
—
V
ICC(ON)
VENABLE 1 = VENABLE 2 = 0.8 V
—
—
50
mA
ICC(OFF)
VENABLE 1 = VENABLE 2 = 2.4 V
—
—
9.0
mA
VT(UVLO)hys
NOTES:
1. Typical Data is for design information only.
2. Negative current is defined as coming out of (sourcing) the specified device terminal.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
5
A3969
Dual Full-Bridge PWM Motor Driver
FUNCTIONAL DESCRIPTION
Internal PWM Current Control. The A3969 dual
H-bridge is designed to drive both windings of a bipolar
stepper motor. Load current can be controlled in each motor winding by an internal fixed-frequency PWM control
circuit. The current-control circuitry works as follows:
when the outputs of the H-bridge are turned on, current increases in the motor winding. The load current is sensed by
the current-control comparator via an external sense resistor (RS). Load current continues to increase until it reaches
the predetermined value, set by the selection of external
current-sensing resistors and reference input voltage (VREF)
according to the equation:
ITRIP = IOUT + ISO = VREF/(4 RS)
where ISO is the sense-current error (typically 18 mA) due
to the base-drive current of the sink driver transistor.
At the trip point, the comparator resets the source-enable latch, turning off the source driver of that H-bridge.
The source turn off of one H-bridge is independent of the
other H-bridge. Load inductance causes the current to
recirculate through the sink driver and ground-clamp diode.
The current decreases until the internal clock oscillator sets
the source-enable latches of both H-bridges, turning on
the source drivers of both bridges. Load current increases
again, and the cycle is repeated.
The frequency of the internal clock oscillator is set by
the external timing components RTCT. The frequency can
be approximately calculated as:
fosc = 1/(RT CT + tblank)
where tblank is defined below.
The range of recommended values for RT and CT are
20 kΩ to 100 kΩ and 470 pF to 1000 pF respectively.
Nominal values of 56 kΩ and 680 pF result in a clock
frequency of 25 kHz.
Current-Sense Comparator Blanking. When the
source driver is turned on, a current spike occurs due to
the reverse-recovery currents of the clamp diodes and
switching transients related to distributed capacitance in
the load. To prevent this current spike from erroneously
resetting the source enable latch, the current-control comparator output is blanked for a short period of time when
the source driver is turned on. The blanking time is set by
the timing component CT according to the equation:
tblank = 1900 CT (μs).
A nominal CT value of 680 pF will give a blanking
time of 1.3 μs.
The current-control comparator is also blanked when
the H-bridge outputs are switched by the PHASE or ENABLE inputs. This internally generated blank time is
approximately 1 μs.
V
BB
V PHASE
See Enlargement A
+
I OUT
BRIDGE ON
BRIDGE
ON
ALL
OFF
0
SOURCE OFF
–
ALL OFF
BRIDGE
ON
I TRIP
Enlargement A
SOURCE
OFF
td
t
INTERNAL
OSCILLATOR
R TC T
RS
blank
Dwg. WM-003-2
Dwg. EP-006-16
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
6
A3969
Dual Full-Bridge PWM Motor Driver
FUNCTIONAL DESCRIPTION (continued)
Load Current Regulation. Due to internal logic and
switching delays (td), the actual load current peak will be
slightly higher than the ITRIP value. These delays, plus the
blanking time, limit the minimum value the current control
circuitry can regulate. To produce zero current in a winding, the ENABLE terminal should be held high, turning off
all output drivers for that H-bridge.
Logic Inputs. A logic high on the PHASE input results
in current flowing from OUTA to OUTB of that H-bridge.
A logic low on the PHASE input results in current flowing
from OUTB to OUTA. An internally generated dead time
(tcodt) of approximately 1 μs prevents cross-over current
spikes that can occur when switching the PHASE input.
A logic high on the ENABLE input turns off all four
output drivers of that H-bridge. This results in a fast current decay through the internal ground clamp and flyback
diodes. A logic low on the ENABLE input turns on the
selected source and sink driver of that H-bridge.
The ENABLE inputs can be pulse-width modulated
for applications that require a fast current-decay PWM. If
external current-sensing circuitry is used, the internal current-control logic can be disabled by connecting the RTCT
terminal to ground.
The REFERENCE input voltage is typically set with a
resistor divider from VCC. This reference voltage is internally divided down by 4 to set up the current-comparator
trip-voltage threshold. The reference input voltage range is
0 to 1.7 V.
Output Drivers. To minimize on-chip power dissipation,
the sink drivers incorporate a Satlington structure. The
Satlington output combines the low VCE(sat) features of a
saturated transistor and the high peak-current capability
of a Darlington (connected) transistor. A graph showing
typical output saturation voltages as a function of output
current is on the next page.
Miscellaneous Information. Thermal protection
circuitry turns off all output drivers should the junction
temperature reach +165 °C (typical). This is intended
only to protect the device from failures due to excessive
junction temperatures and should not imply that output
short circuits are permitted. Normal operation is resumed
when the junction temperature has decreased about 15°C.
The A3969 current control employs a fixed-frequency,
variable duty cycle PWM technique. As a result, the current-control regulation may become unstable if the duty
cycle exceeds 50%.
To minimize current-sensing inaccuracies caused
by ground trace IR drops, each current-sensing resistor
should have a separate return to the ground terminal of the
device. For low-value sense resistors, the I x R drops in
the printed-wiring board can be significant and should be
taken into account. The use of sockets should be avoided
as their contact resistance can cause variations in the effective value of RS.
The LOAD SUPPLY terminal, VBB, should be decoupled with an electrolytic capacitor (47 μF recommended)
placed as close to the device as physically practical. To
minimize the effect of system ground I x R drops on
the logic and reference input signals, the system ground
should have a low-resistance return to the load supply
voltage.
The frequency of the clock oscillator will determine
the amount of ripple current. A lower frequency will
result in higher current ripple, but reduced heating in the
motor and driver IC due to a corresponding decrease in
hysteretic core losses and switching losses respectively.
A higher frequency will reduce ripple current, but will
increase switching losses and EMI.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
7
A3969
Dual Full-Bridge PWM Motor Driver
OUTPUT SATURATION VOLTAGE IN VOLTS
2.5
Typical output saturation voltages showing Satlington sinkdriver operation.
TA = +25 C
2.0
SOURCE DRIVER
1.5
1.0
0.5
SINK DRIVER
0
200
300
400
500
600
700
OUTPUT CURRENT IN MILLIAMPERES
Dwg. GP-064-1A
TRUTH TABLE
PHASE
ENABLE
OUTA
OUTB
X
H
Off
Off
H
L
H
L
L
L
L
H
X = Irrelevant
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
8
A3969
Dual Full-Bridge PWM Motor Driver
Package ET, 28-Pin QFN
0.30
5.00 ±0.15
1.15
28
1
2
0.50
28
1
A
5.00 ±0.15
3.15
4.80
3.15
29X
D
SEATING
PLANE
0.08 C
C
4.80
C
+0.05
0.25 –0.07
PCB Layout Reference View
0.90 ±0.10
0.50
For Reference Only
(reference JEDEC MO-220VHHD-1)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
+0.20
0.55 –0.10
A Terminal #1 mark area
B
3.15
2
1
28
3.15
B Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
C Reference land pattern layout (reference IPC7351
QFN50P500X500X100-29V1M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
D Coplanarity includes exposed thermal pad and terminals
Copyright ©2005-2008, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Satlington® is a registered trademark of
Allegro MicroSystems, Inc. (Allegro), and Satlington devices are manufactured under U. S. Patent No. 5,684,427.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
9
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