A3973: Dual DMOS Full-Bridge Microstepping PWM Motor Driver

A3973
Dual DMOS Full-Bridge Microstepping PWM Motor Driver
Discontinued Product
This device is no longer in production. The device should not be
purchased for new design applications. Samples are no longer available.
Date of status change: November 1, 2010
Recommended Substitutions:
For existing customer transition, and for new customers or new applications, refer to the A3992.
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
A3973
Dual DMOS Full-Bridge Microstepping PWM Motor Driver
Features and Benefits
Description
▪±1 A, 35 V Continuous Output Rating
▪Low RDS(on) DMOS Output Drivers
▪Optimized Microstepping via 6-Bit Linear DACs
▪Programmable Mixed, Fast, and Slow Current Decay Modes
▪4 MHz Internal Oscillator for Digital Timing
▪Serial-Interface Controls Chip Functions
▪Synchronous Rectification for Low Power Dissipation
▪Internal UVLO and Thermal Shutdown Circuitry
▪Crossover-Current Protection
▪Precision 2 V Reference
▪Inputs Compatible with 3.3 or 5 V Control Signals
▪Sleep and Idle Modes
Designed for pulse-width modulated (PWM) current control
of bipolar microstepping stepper motors, the A3973 is capable
of continuous output currents to ±1 A and operating voltages
to 35 V. Internal fixed off-time PWM current-control timing
circuitry can be programmed via a serial interface to operate
in slow, fast, and mixed current-decay modes.
The desired load-current level is set via the serial port with
two 6-bit linear DACs in conjunction with a reference voltage.
The six bits of control allow maximum flexibility in torque
control for a variety of step methods, from microstepping to
full-step drive. Load current is set in 1.56% increments of the
maximum value.
Synchronous rectification circuitry allows the load current to
flow through the low RDS(on) of the DMOS output driver during
the current decay. This feature eliminates the need for external
clamp diodes in most applications, saving cost and external
component count, while minimizing power dissipation.
Packages:
Internal circuit protection includes thermal shutdown with
hysteresis, transient-suppression diodes, and crossover-current
protection. Special power-up sequencing is not required.
Package B, 24-pin DIP with
two batwing power tabs
The B package is a 24-lead DIP with two copper batwing power
tabs. The LB is a 24-lead SOICW with four internally fused
leads for enhanced power dissipation. These power tabs and
pins are at ground potential and need no electrical isolation.
The A3973 B and LB packages are electrically identical.
Package LB, 24 pin SOICW
with 4 fused leads
Not to scale
Pin-out Diagram
OSC
23
SLEEP
3
22
V REG
OUT 1B
4
21
OUT 2B
LOAD
SUPPLY 1
5
20
LOAD
SUPPLY
GROUND
6
19
GROUND
GROUND
7
18
GROUND
17
SENSE
16
OUT 2A
15
LOGIC
SUPPLY
14
MUX
13
REF
SENSE
1
8
OUT 1A
99
STROBE
10
CLOCK
11
DATA
12
V BB1
V BB2
6-BIT DAC
& LOGIC
CP2
V DD
SERIAL PORT
2
6-BIT DAC
& LOGIC
1
CP1
CHARGE
PUMP
24
VCP
2
2
Dwg. PP-069-3
29319.34 Rev. 4
Dual DMOS Full-Bridge
Microstepping PWM Motor Driver
A3973
Selection Guide
Part Number
Package
Packing
A3973SB-T*
24 pin DIP with two power tabs
15 pieces per tube
A3973SLBTR-T
24 pin SOICW with four internally fused pins
1000 pieces per reel
*Variant is in production but has been determined to be NOT FOR NEW DESIGN. This classification indicates that sale of the
variant is currently restricted to existing customer applications. The variant should not be purchased for new design applications because obsolescence in the near future is probable. Samples are no longer available. Status change: May 4, 2009.
Recommended alternative : A3992.
Absolute Maximum Ratings
Rating
Units
Load Supply Voltage
Characteristic
VBB
35
V
Output Current*
IOUT
±1.0
A
Logic Supply Voltage
VDD
7.0
V
Logic Input Voltage Range
VIN
–0.3 to VDD + 0.3
V
Reference Voltage
Symbol
Notes
VREF
3
V
Sense Voltage (DC)
VS
500
mV
Package Power Dissipation
PD
Package B
3.1
W
Package LB
2.2
W
Operating Ambient Temperature
TA
–20 to 85
ºC
Junction Temperature
TJ
150
ºC
Storage Temperature
Tstg
–55 to 150
ºC
Range S
*Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed
the specified current rating or a junction temperature of 150°C.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
Dual DMOS Full-Bridge
Microstepping PWM Motor Driver
A3973
FUNCTIONAL BLOCK DIAGRAM
0.22 µF
0.22 µF
22
LOGIC
SUPPLY
VREG
CP2
3
CP1
2
2V
UVLO AND
FAULT
DETECT
15
VDD
LOAD
SUPPLY
VCP
REGULATOR
CHARGE PUMP
1
BANDGAP
0.22 µF
VBB1
5
MUX 14
DMOS H-BRIDGE
6-BIT
LINEAR
DAC
SENSE1
+
VCP
OUT1A
6
9
PROGRAMMABLE
PWM TIMER
OSCILATOR
OSC
24
OUT1B
4
FIXED-OFF
BLANK
MIXED DECAY
OSC SELECT/
DIVIDER
8
SENSE1
CLOCK 11
CONTROL
LOGIC
SERIAL
PORT
DATA 12
GATE
DRIVE
PHASE 1/2
SYNC. RECT. MODE
SYNC. RECT. DISABLE
MODE 1/2
STROBE 10
DMOS H-BRIDGE
0.1 µF
20
VBB2
SLEEP 23
OUT2A
16
PROGRAMMABLE
PWM TIMER
2V
6
REF 13
OUT2B
21
FIXED-OFF
BLANK
MIXED DECAY
BUFFER
+
-
6-BIT
LINEAR
DAC
17
SENSE2
0.1 µF
6
7
18 19
GROUND
Dwg. FP-050-1
Copyright © 2000, Allegro MicroSystems, Inc.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
Dual DMOS Full-Bridge
Microstepping PWM Motor Driver
A3973
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 35 V, VDD = 5.0 V, VS = 0.5 V,
fPWM < 50 kHz (unless otherwise noted).
Characteristic
Min.
Typ.
Max.
Units
Operating
15
—
35
V
During sleep mode
0
—
35
V
Logic Supply Voltage Range
VDD
Operating
4.5
5.0
5.5
V
Load Supply Current
IBB
fPWM < 50 kHz —
—
8.0
mA
Operating, outputs disabled
—
—
6.0
mA
Sleep or idle mode
—
—
20
µA
fPWM < 50 kHz
—
—
12
mA
Outputs off
—
—
10
mA
Idle mode (D0 = 1, D18 = 0)
—
—
1.5
mA
Sleep mode —
—
100
µA
VOUT = VBB
—
<1.0
50
µA
VOUT = 0 V
—
<-1.0
-50
µA
Output On Resistance
Source driver, IOUT = –1.0 A
—
0.54
0.60
Ω
Sink driver, IOUT = 1.0 A
—
0.54
0.60
Ω
Body Diode Forward Voltage
Source diode, IF = 1.0 A
—
—
1.2
V
Sink diode, IF = 1.0 A
—
—
1.2
V
Load Supply Voltage Range
Logic Supply Current
Symbol
VBB
IDD
Test Conditions
Limits
Output Drivers
Output Leakage Current
IDSS
rDS(on)
VF
Control Logic
Logic Input Voltage
VIN(1)
2.0
—
—
V
VIN(0)
—
—
0.8
V
Logic Input Current
IIN(1)
VIN = 2.0 V
—
<1.0
20
µA
OSC Input Frequency Range
IIN(0)
fOSC
VIN = 0.8 V
Divide by one —
2.5
<-2.0
—
-20
6.0
µA
MHz
—
40
—
60
%
∆VIN
0.20
—
0.40
V
OSC Input Duty Cycle
Input Hysterisis
(D0 =1, D13 = 0, D14 = 1)
continued next page ...
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
Dual DMOS Full-Bridge
Microstepping PWM Motor Driver
A3973
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 35 V, VDD = 5.0 V, VS = 0.5 V,
fPWM < 50 kHz (unless otherwise noted).
Characteristics
Symbol
Test Conditions
Limits
Min.
Typ.
Max.
Units
OSC shorted to ground
3.0
4.0
5.0
MHz
ROSC = 51 kΩ
3.4
4.0
4.6
MHz
Relative to DAC reference buffer —
±1/2
—
LSB
Control Logic (continued)
Internal Oscillator
DAC Accuracy (total error)
fOSC
ET
output, D0 = 0, D17 = 0
Reference Input Voltage Range
VREF(EXT)
0.5
—
2.6
V
Reference Buffer Offset
VOS
—
±10
—
mV
Reference Divider Ratio
VREF/VS
D0 = 0, D18 = 0
—
8.0
—
—
D0 = 0, D18 = 1
—
4.0
—
—
Reference Input Current
VREF = 2.0 V
—
—
±0.5
µA
1.94
2.0
2.06
V
Gain (Gm) Error (note 3)
EG
D0 = 0, D17 = 0,
    D18 = 0, DAC = 63
    D18 = 0, DAC = 31
    D18 = 1, DAC = 63
—
—
—
0
0
0
±6
±9
±6
%
%
%
    D18 = 1, DAC = 15
—
0
±10
%
Comparator Input Offset Voltage
—
±5.0
—
mV
Propagation Delay Times
tpd
50% to 90%:
    PWM change to source on
    PWM change to source off
    PWM change to sink on
500
50
500
800
150
800
1200
350
1200
ns
ns
ns
    PWM change to sink off
50
150
350
ns
Crossover Dead Time
tdt
300
700
900
ns
Thermal Shutdown Temperature
TJ
—
165
—
°C
∆TJ
—
15
—
°C
3.9
4.2
4.45
V
0.05
0.10
—
V
Internal Reference Voltage Thermal Shutdown Hysteresis
UVLO Enable Threshold
UVLO Hysteresis
IREF
VREF(INT)
VIO
VUVLO
VREF = 0 V
Increasing VDD
∆VUVLO
NOTES: 1. Typical Data is for design information only.
2. Negative current is defined as coming out of (sourcing) the specified device terminal. 3. EG = [(VREF/Range) – VS]/(VREF/Range).
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
Dual DMOS Full-Bridge
Microstepping PWM Motor Driver
A3973
FUNCTIONAL DESCRIPTION
Serial Interface. The A3973SB/SLB is controlled via a
3-wire (clock, data, strobe) serial port. The programmable functions allow maximum flexibility in configuring the PWM to the
motor drive requirements. The serial data is written as two
19-bit words: 1 bit to select the word and 18 bits of data. The
serial data is clocked in starting with D18.
Word 0 Bit Assignments
Bit
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
Function
Word select = 0
Bridge 1, DAC, LSB
Bridge 1, DAC, bit 2
Bridge 1, DAC, bit 3
Bridge 1, DAC, bit 4
Bridge 1, DAC, bit 5
Bridge 1, DAC, MSB
Bridge 2, DAC, LSB
Bridge 2, DAC, bit 2
Bridge 2, DAC, bit 3
Bridge 2, DAC, bit 4
Bridge 2, DAC, bit 5
Bridge 2, DAC, MSB
Bridge 1 phase
Bridge 2 phase
Bridge 1 mode
Bridge 2 mode
REF select
Range select
D1 – D6 Bridge 1 Linear DAC. Six-bit word sets desired
current level for Bridge 1. Setting all six bits to zero disables
Bridge 1, with all drivers off (See current regulation section of
functional description).
D7 – D12 Bridge 2 Linear DAC. Six-bit word sets desired
current level for Bridge 2. Setting all six bits to zero disables
Bridge 2, with all drivers off (See current regulation section of
functional description).
D13 Bridge 1 Phase. This bit controls the direction of output
current for Load 1.
D13
OUT1A
OUT1B
0
1
L
H
H
L
D14 Bridge 2 Phase. This bit controls the direction of output
current for Load 2.
D14
OUT2A
OUT2B
0
1
L
H
H
L
D15 Bridge 1 Mode.
D15
Mode
0
1
Mixed-decay
Slow-decay
D16 Bridge 2 Mode.
D16
Mode
0
1
Mixed-decay
Slow-decay
D17 REF Select. This bit determines the reference input for
the 6-bit linear DACs.
D17
Reference Voltage
0
1
Internal 2 V
External (3 V max)
D18 Gm Range Select. This bit determines the scaling factor
(4 or 8) used.
D18
Divider
0
1
1/8
1/4
Load Current
ITRIP = VDAC/8RS
ITRIP = VDAC/4RS
continued next page ...
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
Dual DMOS Full-Bridge
Microstepping PWM Motor Driver
A3973
FUNCTIONAL DESCRIPTION (continued)
Word 1 Bit Assignments
Bit
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17 D18
Function
Word select = 1
Blank-time LSB
Blank-time MSB
Off-time LSB
Off-time bit 1
Off-time bit 2
Off-time bit 3
Off-time MSB
Fast-decay time LSB
Fast-decay time bit 1
Fast-decay time bit 2
Fast-decay time MSB
C0 oscillator control
C1 oscillator control
SR control bit 1
SR control bit 2
Reserved for testing
Reserved for testing
Idle mode
D1 – D2 Blank Time. These two bits set the blank time for
the current-sense comparator. When a source driver turns on, a
current spike occurs due to the reverse-recovery currents of the
clamp diodes and/or switching transients related to distributed
capacitance in the load. To prevent this current spike from erroneously resetting the source-enable latch, the sense comparator
is blanked. The blank timer runs after the off-time counter to
provide the programmable blanking function. The blank timer is
reset when PHASE is changed. D2
0
0
1
D1
0
1
0
Time
4/fOSC
6/fOSC
8/fOSC
1
1
12/fOSC
D3 – D7 Fixed Off Time. These five bits set the fixed off-time
for the internal PWM control circuitry. Fixed off-time is defined
by:
toff = [(1 + N) x 8/fOSC] - 1/fOSC
where N = 0….31
For example, with a master oscillator frequency of 4 MHz, the
fixed-off time will be adjustable from 1.75 µs to 63.75 µs in
increments of 2 µs.
D8 – D11 Fast Decay Time. These four bits set the fastdecay portion of fixed off-time for the internal PWM control
circuitry. The fast-decay portion is defined by:
tfd = [(1 + N) x 8/fOSC] - 1/fOSC
where N = 0….15
For example, with an oscillator frequency of 4 MHz, the fastdecay time will be adjustable from 1.75 µs to 31.75 µs in increments of 2 µs. For tfd > toff , the device will effectively operate
in fast-decay mode.
D12 – D13 Oscillator Control. A 4 MHz internal oscillator
is used for the timing functions and charge-pump clock. If more
precise control is required, an external oscillator can be input
to the OSC terminal. To accommodate a wider range of system
clocks, an internal divider is provided to generate the desired
MO frequency according to the following table:
D13 0
0
1
1
D12
0
1
0
1
OSC
4 MHz internal clock
External clock
External clock/2
External clock/4
D14 – D15 Synchronous Rectification.
D15
0
0
1
1
D14
0
1
0
1
Synchronous Rectifier
Active
Disabled
Passive
Low side only
The different modes of operation are in the synchronous rectification section of the functional description.
D16, D17. These bits are reserved for testing and should be
programmed to zero during normal operation.
D18 Idle Mode. The device can be placed in a low power
“idle” mode by writing a “0” to D18. The outputs will be disabled, the charge pump will be turned off, and the device will
draw a lower load supply currrent. The undervoltage monitor
circuit will remain active. D18 should be programmed high for
1 ms before attempting to enable any output driver.
continued next page ...
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
Dual DMOS Full-Bridge
Microstepping PWM Motor Driver
A3973
FUNCTIONAL DESCRIPTION (continued)
VREG. This internally generated supply voltage is used to run
the sink-side DMOS outputs. VREG is internally monitored and
in the case of a fault condition, the outputs of the device are
disabled. The VREG pin should be decoupled with a 0.22 µF
capacitor to ground.
Shutdown. In the event of a fault due to excessive junction
temperature, or low voltage on VCP or VREG, the outputs of the
device are disabled until the fault condition is removed. At
power up, or in the event of low VDD, the UVLO circuit disables
the drivers and resets the data in the serial port to zeros.
Current Regulation. The reference voltage can be set by analog input to the REF terminal, or via the internal 2 V precision
reference. The choice of reference voltage and sense resistor set
the maximum trip current.
ITRIPMAX = VREF/(Range x RS)
Synchronous Rectification. When a PWM off-cycle is
triggered, either by a bridge disable command or internal fixed
off-time cycle, the load current will recirculate according to the
decay mode selected by the control logic. The A3973SB/SLB
synchronous rectification feature will turn on the appropriate
MOSFET(s) during the current decay and effectively short out
the body diodes with the low rDS(on) driver. This will lower
power dissipation significantly and can eliminate the need for
external Schottky diodes for most applications.
Microstepping current levels are set according to the following
equations:
ITRIP = VDAC/(Range x RS)
VDAC = [(1 + DAC) x VREF]/64
where DAC input code equals 1 to 63 and Range is 4 or 8 as
selected by Word 0, D18. Programming the DAC input code to
zero disables the bridge, and results in minimum load current.
PWM Timer Function. The PWM timer is programmable via
the serial port to provide fixed off-time PWM signals to the control block. In mixed-decay mode, the first portion of the off time
operates in fast decay, until the fast-decay time count is reached,
followed by slow decay for the rest of the fixed off-time period. If the fast-decay time is set longer than the off-time, the device
effectively operates in fast-decay mode.
Oscillator. The PWM timer is based on an oscillator input,
typically 4 MHz. The A3973SB/SLB can be configured to
select either a 4 MHz internal oscillator or, if more precision is
required, an external clock can be connected to the OSC terminal. If an external clock is used, three internal divider choices
are selectable via the serial port to allow flexibility in choosing
fOSC, based on available system clocks. If the internal oscillator
option is used, the absolute accuracy is dependent on the process
variation of resistance and capacitance. A precision resistor can
be connected from the OSC terminal to VDD to further improve
the tolerance. The frequency will be:
fOSC = 204 x 109/ROSC
If the internal oscillator is used without the external resistor, the
OSC terminal should be connected to ground.
Sleep Mode. The input terminal SLEEP is dedicated to putting
the device into a minimum current draw mode. When pulled
low, the serial port will be reset to all zeros and all circuits will
be disabled.
Four distinct modes of operation can be configured with the two
serial port control bits:
1. Active Mode. Prevents reversal of load current by turning
off synchronous rectification when a zero current level is
detected.
2. Passive Mode. Allows reversal of current but will turn
off the synchronous rectifier circuit if the load current inversion ramps up to the current limit.
3. Disabled. MOSFET switching will not occur during load
recirculation. This setting would only be used with four
external clamp diodes per bridge.
4. Low Side Only. The low-side MOSFETs will switch on
during the off time to short out the current path through
the MOSFET body diode. With this setting, the high-side
MOSFETs will not synchronously rectify so four external
diodes from output to supply are recommended. This mode
is intended for use with high-power applications where it
is desired to save the expense of two external diodes per
bridge. In this mode, the sink-side MOSFETs are chopped
during the PWM off time. In all other cases, the source-side
MOSFETs are chopped in response to a PWM off command.
continued next page ...
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
Dual DMOS Full-Bridge
Microstepping PWM Motor Driver
A3973
APPLICATIONS INFORMATION
Current Sensing. To minimize inaccuracies in sensing the
IPEAK current level caused by ground-trace IR drops, the sense
resistor should have an independent ground return to the ground
terminal of the device. For low-value sense resistors, the IR
drops in the sense resistor’s PCB traces can be significant and
should be taken into account. The use of sockets should be
avoided as they can introduce variation in RS due to their contact
resistance.
Thermal Protection. Circuitry turns off all drivers when the
junction temperature reaches 165°C typically. It is intended
only to protect the device from failures due to excessive junction
temperature and should not imply that output short circuits are
permitted. Thermal shutdown has a hysteresis of approximately
15°C.
Layout. The printed wiring board should use a heavy ground
plane. For optimum electrical and thermal performance, the
driver should be soldered directly onto the board. The ground
side of RS should have an individual path to the ground pin(s) of
the driver. This path should be as short as physically possible
and should not have any other components connected to it. The
load supply pin, VBB, should be decoupled with an electrolytic
capacitor (>47 µF is recommended) placed as close to the driver
as is possible.
Serial Port Write Timing Operation. Data is clocked into
a shift register on the rising edge of CLOCK signal. Normally,
STROBE will be held high, and only will be brought low to
initiate a write cycle. The data is written MSB first, followed
by the word-select bit. Refer to serial port diagram for timing
requirements.
SLEEP
H
STROBE
C
D
E
F
G
CLOCK
A
DATA
B
D18
D17
D0
A. Minimum Data Setup Time........................................15 ns
B. Minimum Data Hold Time.........................................10 ns
C. Minimum Setup Strobe to Clock Rising Edge.........150 ns
D. Minimum Clock High Pulse Width............................40 ns
E. Minimum Clock Low Pulse Width.............................40 ns
F. Minimum Setup Clock Rising Edge to Strobe............50 ns
G. Minimum Strobe Pulse Width..................................150 ns
H. Minimum Setup Sleep to Strobe falling.....................50 µs
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
Dual DMOS Full-Bridge
Microstepping PWM Motor Driver
A3973
B Package, 24-Pin DIP
+0.25
30.10 –0.64
24
+0.10
0.38 –0.05
+0.76
6.35 –0.25
+0.38
10.92 –0.25
5.33 MAX
For Reference Only
(reference JEDEC MS-001 BE)
Dimensions in millimeters
7.62
A
1
2
+0.51
3.30 –0.38
1.27 MIN
+0.25
1.52 –0.38
2.54
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
0.018
0.46 ±0.12
LB Package, 24-Pin SOICW
15.40±0.20
4° ±4
24
+0.07
0.27 –0.06
10.30±0.33
7.50±0.10
A
1
24
2.20
9.60
+0.44
0.84 –0.43
2
0.25
24X
SEATING
PLANE
0.10 C
0.41 ±0.10
1.27
C
SEATING PLANE
GAUGE PLANE
1
2
0.65
1.27
B PCB Layout Reference View
2.65 MAX
0.20 ±0.10
For reference only
Pins 6 and 7, and 18 and 19 internally fused
Dimensions in millimeters
(Reference JEDEC MS-013 AD)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Reference pad layout (reference IPC SOIC127P1030X265-24M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
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The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
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