ADC12DL040 Dual 12-Bit, 40 MSPS, 3V, 210mW A/D Converter General Description Features The ADC12DL040 is a dual, low power monolithic CMOS analog-to-digital converter capable of converting analog input signals into 12-bit digital words at 40 Megasamples per second (MSPS). This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to minimize die size and power consumption while providing excellent dynamic performance and a 250 MHz Full Power Bandwidth. Operating on a single +3.0V power supply, the ADC12DL040 achieves 11.1 effective bits at nyquist and consumes just 210 mW at 40 MSPS, including the reference current. The Power Down feature reduces power consumption to 36 mW. n n n n n n n n The differential inputs provide a full scale differential input swing equal to 2 times VREF with the possibility of a singleended input. Full use of the differential input is recommended for optimum performance. The digital outputs from the two ADC’s are available on a single multiplexed 12-bit bus or on separate buses. Duty cycle stabilization and output data format are selectable using a quad state function pin. The output data can be set for offset binary or two’s complement. To ease interfacing to lower voltage systems, the digital output driver power pins of the ADC12DL040 can be connected to a separate supply voltage in the range of 2.4V to the analog supply voltage. This device is available in the 64-lead TQFP package and will operate over the industrial temperature range of −40˚C to +85˚C. An evaluation board is available to ease the evaluation process. Single +3.0V supply operation Internal sample-and-hold Internal reference Outputs 2.4V to 3.6V compatible Power down mode On-chip reference Duty Cycle Stabilizer Multiplexed Output Mode Key Specifications n n n n n n n n Resolution DNL SNR (fIN = 10 MHz) SFDR (fIN = 10 MHz) Data Latency Power Consumption -- Operating -- Power Down Mode 12 Bits ± 0.3 LSB (typ) 69 dB (typ) 85 dB (typ) 7 Clock Cycles 210 mW (typ) 36 mW (typ) Applications n n n n n n n Ultrasound and Imaging Instrumentation Communications Receivers Sonar/Radar xDSL Cable Modems DSP Front Ends Connection Diagram 20100201 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 2005 National Semiconductor Corporation DS201002 www.national.com ADC12DL040 Dual 12-Bit, 40 MSPS, 3V, 210mW A/D Converter February 2005 ADC12DL040 Ordering Information Industrial (−40˚C ≤ TA ≤ +85˚C) Package ADC12DL040CIVS 64 Pin TQFP ADC12DL040EVAL Evaluation Board Block Diagram 20100202 www.national.com 2 Pin No. Symbol Equivalent Circuit Description ANALOG I/O 15 2 VINA+ VINB+ 16 1 VINA− VINB− Differential analog input pins. With a 1.0V reference voltage the differential full-scale input signal level is 2.0 VP-P with each input pin voltage centered on a common mode voltage, VCM. The negative input pins may be connected to VCM for single-ended operation, but a differential input signal is required for best performance. VREF This pin is the reference select pin and the external reference input. If (VA - 0.3V) < VREF < VA, the internal 1.0V reference is selected. If AGND < VREF < (AGND + 0.3V), the internal 0.5V reference is selected. If a voltage in the range of 0.8V to 1.2V is applied to this pin, that voltage is used as the reference. VREF should be bypassed to AGND with a 0.1 µF capacitor when an external reference is used. 21 DF/DCS This is a four-state pin. DF/DCS = VA, output data format is offset binary with duty cycle correction applied to the input clock DF/DCS = AGND, output data format is 2’s complement, with duty cycle correction applied to the input clock. DF/DCS = VRMA or VRMB , output data is 2’s complement without duty cycle correction applied to the input clock DF/DCS = "float", output data is offset binary without duty cycle correction applied to the input clock. 13 5 VRPA VRPB 7 14 4 VRMA VRMB 12 6 VRNA VRNB These pins are high impedance reference bypass pins. All these pins should each be bypassed to ground with a 0.1 µF capacitor. A 10 µF capacitor should be placed between the VRPA and VRNA pins and between the VRPB and VRNB pins. VRMA and VRMB may be loaded to 1mA for use as a temperature stable 1.5V reference. The remaining pins should not be loaded. DIGITAL I/O 60 CLK Digital clock input. The range of frequencies for this input is as specified in the electrical tables with guaranteed performance at 40 MHz. The input is sampled on the rising edge. 22 41 OEA OEB OEA and OEB are the output enable pins that, when low, holds their respective data output pins in the active state. When either of these pins is high, the corresponding outputs are in a high impedance state. 3 www.national.com ADC12DL040 Pin Descriptions and Equivalent Circuits ADC12DL040 Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit (Continued) Description PD PD is the Power Down input pin. When high, this input puts the converter into the power down mode. When this pin is low, the converter is in the active mode. 11 MULTIPLEX When low, "A" and "B" data is present on it’s respective data output lines (Parallel Mode). When high, both "A" and "B" channel data is present on the "DA0:DA11" digital outputs (Multiplex Mode). The DB0/ABb pin is used to synchronize the data. 24–29 34–39 DA0–DA11 43–47 52–57 DB1–DB11 59 Digital data output pins that make up the 12-bit conversion results of their respective converters. DA0 and DB0 are the LSBs, while DA11 and DB11 are the MSBs of the output word. Output levels are TTL/CMOS compatible. Optimum loading is < 10pF. DB0/ABb When MULTIPLEX is low, this is DB0. When MULTIPLEX is high this is the ABb signal, which is used to synchronize the multiplexed data. ABb changes synchronously with the Multiplexed "A" and "B" channels. ABb is "high" when "A" channel data is valid and is "low" when "B" channel data is valid. 9, 18, 19, 62, 63 VA Positive analog supply pins. These pins should be connected to a quiet +3.0V source and bypassed to AGND with 0.1 µF capacitors located within 1 cm of these power pins, and with a 10 µF capacitor. 3, 8, 10, 17, 20, 61, 64 AGND 42 ANALOG POWER The ground return for the analog supply. DIGITAL POWER 33, 48 VD 32, 49 DGND 30, 51 23, 31, 40, 50, 58 www.national.com Positive digital supply pin. This pin should be connected to the same quiet +3.0V source as is VA and be bypassed to DGND with a 0.1 µF capacitor located within 1 cm of the power pin and with a 10 µF capacitor. The ground return for the digital supply. VDR Positive driver supply pin for the ADC12DL040’s output drivers. This pin should be connected to a voltage source of +2.4V to VD and be bypassed to DR GND with a 0.1 µF capacitor. If the supply for this pin is different from the supply used for VA and VD, it should also be bypassed with a 10 µF capacitor. VDR should never exceed the voltage on VD. All 0.1 µF bypass capacitors should be located within 1 cm of the supply pin. DR GND The ground return for the digital supply for the ADC12DL040’s output drivers. These pins should be connected to the system digital ground, but not be connected in close proximity to the ADC12DL040’s DGND or AGND pins. See Section 5 (Layout and Grounding) for more details. 4 Operating Ratings (Notes 1, 2) (Notes 1, 2) Operating Temperature If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VA, VD) −40˚C ≤ TA ≤ +85˚C +2.7V to +3.6V Output Driver Supply (VDR) CLK, PD, OEA, OEB VA, VD, VDR 4.2V Voltage on Any Input or Output Pin −0.05V to (VD + 0.05V) Analog Input Pins ≤ 100 mV |VA–VD| +2.4V to VD 0V to 2.6V VCM −0.3V to (VA or VD +0.3V) 0.5V to 2.0V ≤100mV |AGND–DGND| ± 25 mA ± 50 mA Input Current at Any Pin (Note 3) Package Input Current (Note 3) Package Dissipation at TA = 25˚C See (Note 4) ESD Susceptibility Human Body Model (Note 5) 2500V Machine Model (Note 5) Storage Temperature 250V −65˚C to +150˚C Soldering process must comply with National Semiconductor’s Reflow Temperature Profile specifications. Refer to www.national.com/packaging. (Note 6) Converter Electrical Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.0V, VDR = +2.5V, PD = 0V, External VREF = +1.0V, fCLK = 40 MHz, fIN = 10 MHz, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On, parallel output mode. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9) Symbol Parameter Typical (Note 10) Conditions Limits (Note 10) Units (Limits) STATIC CONVERTER CHARACTERISTICS Resolution with No Missing Codes INL Integral Non Linearity (Note 11) 12 Bits (min) ± 0.8 ± 2.6 LSB (max) LSB (max) DNL Differential Non Linearity ± 0.3 +0.96, -0.9 PGE Positive Gain Error ± 0.2 +2.5, -3.3 %FS (max) NGE Negative Gain Error ± 0.2 ± 3.6 %FS (max) TC GE Gain Error Tempco VOFF Offset Error (VIN+ = VIN−) ± 0.8 %FS (max) TC VOFF Offset Error Tempco −40˚C ≤ TA ≤ +85˚C 5 0.1 −40˚C ≤ TA ≤ +85˚C ppm/˚C 3 ppm/˚C Under Range Output Code 0 0 Over Range Output Code 4095 4095 REFERENCE AND ANALOG INPUT CHARACTERISTICS VCM Common Mode Input Voltage VRMA, VRMB Reference Output Voltage Output load = 1 mA CIN VIN Input Capacitance (each pin to GND) VIN = 2.5 Vdc + 0.7 Vrms VREF External Reference Voltage (Note 13) 1.5 2.0 V (max) V (CLK LOW) 8 pF (CLK HIGH) 7 1 5 V (min) 1.5 1.00 Reference Input Resistance 0.5 pF 0.8 V (min) 1.2 V (max) MΩ (min) www.national.com ADC12DL040 Absolute Maximum Ratings ADC12DL040 Converter Electrical Characteristics (Continued) Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.0V, VDR = +2.5V, PD = 0V, External VREF = +1.0V, fCLK = 40 MHz, fIN = 10 MHz, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On, parallel output mode. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9) Symbol Parameter Conditions Typical (Note 10) Limits (Note 10) Units (Limits) DYNAMIC CONVERTER CHARACTERISTICS FPBW SNR SINAD ENOB THD H2 H3 SFDR IMD Full Power Bandwidth Signal-to-Noise Ratio Signal-to-Noise and Distortion Effective Number of Bits Total Harmonic Distortion Second Harmonic Distortion 0 dBFS Input, Output at −3 dB 250 fIN = 1 MHz, VIN = −0.5 dBFS 69 fIN = 10 MHz, VIN = −0.5 dBFS 69 fIN = 20 MHz, VIN = −0.5 dBFS 68.5 fIN = 1 MHz, VIN = −0.5 dBFS 68.5 fIN = 10 MHz, VIN = −0.5 dBFS 68.5 fIN = 20 MHz, VIN = −0.5 dBFS 68.5 fIN = 1 MHz, VIN = −0.5 dBFS 11.1 fIN = 10 MHz, VIN = −0.5 dBFS 11.1 fIN = 20 MHz, VIN = −0.5 dBFS 11.1 fIN = 1 MHz, VIN = −0.5 dBFS −82 fIN = 10 MHz, VIN = −0.5 dBFS −83 MHz dB 67.5 dB (min) dB dB 67 dB (min) dB Bits 10.8 Bits (min) Bits dB -75 dB (min) fIN = 20 MHz, VIN = −0.5 dBFS −83 dB fIN = 1 MHz, VIN = −0.5 dBFS −88 dB fIN = 10 MHz, VIN = −0.5 dBFS −86 fIN = 20 MHz, VIN = −0.5 dBFS −86.5 dB fIN = 1 MHz, VIN = −0.5 dBFS −86 dB -76 dB (min) fIN = 10 MHz, VIN = −0.5 dBFS −87 fIN = 20 MHz, VIN = −0.5 dBFS −86.5 dB fIN = 1 MHz, VIN = −0.5 dBFS 86 dB Spurious Free Dynamic Range fIN = 10 MHz, VIN = −0.5 dBFS 85 fIN = 20 MHz, VIN = −0.5 dBFS 84 dB Intermodulation Distortion fIN = 9.6 MHz and 10.2 MHz, each = −6.0 dBFS −75 dBFS ± 0.3 ±4 %FS 10 MHz Tested Channel; 20 MHz Other Channel 80 dB (min) 20 MHz Tested Channel; 10 MHz Other Channel 80 dB (min) Third Harmonic Distortion -77 76 dB (min) dB (min) INTER-CHANNEL CHARACTERISTICS Channel — Channel Offset Match Channel — Channel Gain Match Crosstalk www.national.com 6 %FS Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.0V, VDR = +2.5V, PD = 0V, VREF = +1.0V, fCLK = 40 MHz, fIN = 10 MHz, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On, parallel output mode. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9) Symbol Parameter Conditions Typical (Note 10) Limits (Note 10) Units (Limits) 2.0 V (min) 1.0 V (max) CLK, PD, OEA, OEB DIGITAL INPUT CHARACTERISTICS VIN(1) Logical “1” Input Voltage VD = 3.6V VIN(0) Logical “0” Input Voltage VD = 3.0V IIN(1) Logical “1” Input Current VIN = 3.3V 10 µA IIN(0) Logical “0” Input Current VIN = 0V −10 µA CIN Digital Input Capacitance 5 pF DA0–DA11, DB0-DB11 DIGITAL OUTPUT CHARACTERISTICS VOUT(1) Logical “1” Output Voltage IOUT = −0.5 mA VOUT(0) Logical “0” Output Voltage IOUT = 1.6 mA, VDR = 3V VDR = 2.5V 2.3 V (min) VDR = 3V 2.7 V (min) 0.4 V (max) VOUT = 2.5V or 3.3V 100 nA VOUT = 0V −100 nA IOZ TRI-STATE ® Output Current +ISC Output Short Circuit Source Current VOUT = 0V −20 mA −ISC Output Short Circuit Sink Current VOUT = VDR 20 mA COUT Digital Output Capacitance 5 pF POWER SUPPLY CHARACTERISTICS IA Analog Supply Current PD Pin = DGND, VREF = VA PD Pin = VD 58 12 72 mA (max) mA ID Digital Supply Current PD Pin = DGND PD Pin = VD , fCLK = 0 12 0 14 mA (max) mA IDR Digital Output Supply Current PD Pin = DGND, CL = 5 pF (Note 14) PD Pin = VD, fCLK = 0 12 0 Total Power Consumption PD Pin = DGND, CL = 5 pF (Note 15) PD Pin = VD 210 36 Power Supply Rejection Ratio Rejection of Full-Scale Error with VA = 2.7V vs. 3.6V 54 PSRR1 mA mA 258 mW (max) mW dB AC Electrical Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.0V, VDR = +2.5V, PD = 0V, External VREF = +1.0V, fCLK = 40 MHz, fIN = 10 MHz, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On, parallel output mode. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9, 12) Symbol Parameter Conditions Typical (Note 10) Limits (Note 10) Units (Limits) 40 MHz (min) fCLK1 Maximum Clock Frequency fCLK2 Minimum Clock Frequency tCH Clock High Time Duty Cycle Stabilizer On 10 5 ns (min) tCL Clock Low Time Duty Cycle Stabilizer On 10 5 ns (min) tr, tf Clock Rise and Fall Times Duty Cycle Stabilizer On 2 4 ns (max) tCH Clock High Time Duty Cycle Stabilizer Off 12.5 11.25 ns (min) tCL Clock Low Time Duty Cycle Stabilizer Off 12.5 11.25 ns (min) tr, tf Clock Rise and Fall Times Duty Cycle Stabilizer Off 2 tCONV Conversion Latency Parallel mode tOD Data Output Delay after Rising Clock Edge Parallel mode 10 MHz ns (max) 7 6.0 7 Clock Cycles 3.5 ns (min) 9.6 ns (max) www.national.com ADC12DL040 DC and Logic Electrical Characteristics ADC12DL040 AC Electrical Characteristics (Continued) Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.0V, VDR = +2.5V, PD = 0V, External VREF = +1.0V, fCLK = 40 MHz, fIN = 10 MHz, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On, parallel output mode. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9, 12) Symbol Parameter Conditions Typical (Note 10) Limits (Note 10) Units (Limits) tCONV Conversion Latency Multiplex mode, Channel A 7.5 Clock Cycles tCONV Conversion Latency Multiplex mode, Channel B 8 Clock Cycles tOD Data Output Delay after Clock Edge Multiplex mode tSKEW ABb to Data Skew tAD Aperture Delay 2 ns tAJ Aperture Jitter 1.2 ps rms tDIS Data outputs into Hi-Z Mode 10 ns tEN Data Outputs Active after Hi-Z Mode 10 ns tPD Power Down Mode Exit Cycle 1 µs 6.0 3.5 ns (min) 9 ns (max) ± 0.5 1.0 µF on pins 4, 14; 0.1 µF on pins 5,6,12,13; 10 µF between pins 5, 6 and between pins 12, 13 ns (max) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified. Note 3: When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two. Note 4: The absolute maximum junction temperature (TJmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature, (TA), and can be calculated using the formula PDMAX = (TJmax - TA )/θJA. In the 64-pin TQFP, θJA is 50˚C/W, so PDMAX = 2 Watts at 25˚C and 800 mW at the maximum operating ambient temperature of 85˚C. Note that the power consumption of this device under normal operation will typically be about 250 mW (210 typical power consumption + 40 mW TTL output loading). The values for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided. Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω. Note 6: Reflow temperature profiles are different for lead-free and non-lead-free packages. Note 7: The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided current is limited per (Note 3). However, errors in the A/D conversion can occur if the input goes above VA or below GND by more than 100 mV. As an example, if VA is +3.3V, the full-scale input voltage must be ≤+3.4V to ensure accurate conversions. 20100207 Note 8: To guarantee accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin. Note 9: With the test condition for VREF = +1.0V (2VP-P differential input), the 12-bit LSB is 488 µV. Note 10: Typical figures are at TJ = 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 11: Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive and negative full-scale. Note 12: Timing specifications are tested at TTL logic levels, VIL = 0.4V for a falling edge and VIH = 2.4V for a rising edge. Note 13: Optimum performance will be obtained by keeping the reference input in the 0.8V to 1.2V range. The LM4051CIM3-ADJ (SOT-23 package) is recommended for external reference applications. Note 14: IDR is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply voltage, VDR, and the rate at which the outputs are switching (which is signal dependent). IDR=VDR(C0 x f0 + C1 x f1 +....C11 x f11) where VDR is the output driver power supply voltage, Cn is total capacitance on the output pin, and fn is the average frequency at which that pin is toggling. Note 15: Excludes IDR. See note 14. www.national.com 8 APERTURE DELAY is the time after the rising edge of the clock to when the input signal is acquired or held for conversion. OFFSET ERROR is the difference between the two input voltages [(VIN+) – (VIN−)] required to cause a transition from code 2047 to 2048. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. Aperture jitter manifests itself as noise in the output. OUTPUT DELAY is the time delay after the rising edge of the clock before the data update is presented at the output pins. CLOCK DUTY CYCLE is the ratio of the time during one cycle that a repetitive digital waveform is high to the total time of one period. The specification here refers to the ADC clock input signal. COMMON MODE VOLTAGE (VCM) is the common d.c. voltage applied to both input terminals of the ADC. OVER RANGE RECOVERY TIME is the time required after VIN goes from a specified voltage out of the normal input range to a specified voltage within the normal input range and the converter makes a conversion with its rated accuracy. PIPELINE DELAY (LATENCY) See CONVERSION LATENCY. CONVERSION LATENCY is the number of clock cycles between initiation of conversion and when that data is presented to the output driver stage. Data for any given sample is available at the output pins the Pipeline Delay plus the Output Delay after the sample is taken. New data is available at every clock cycle, but the data lags the conversion by the pipeline delay. POSITIVE FULL SCALE ERROR is the difference between the actual last code transition and its ideal value of 11⁄2 LSB below positive full scale. POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power supply voltage. For the ADC12DL040, PSRR1 is the ratio of the change in Full-Scale Error that results from a change in the d.c. power supply voltage, expressed in dB. PSRR2 is a measure of how well an a.c. signal riding upon the power supply is rejected at the output. SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or d.c. CROSSTALK is coupling of energy from one channel into the other channel. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated as: Gain Error = Positive Full Scale Error − Offset Error A gain of unity occurs when the negative and positive full scale errors are equal to each other, including having the same sign. GAIN ERROR MATCHING is the difference in gain errors between the two converters divided by the average gain of the converters. INTEGRAL NON LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from negative full scale (1⁄2 LSB below the first code transition) through positive full scale (1⁄2 LSB above the last code transition). The deviation of any given code from this straight line is measured from the center of that code value. INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in the intermodulation products to the total power in the original frequencies. IMD is usually expressed in dBFS. LSB (LEAST SIGNIFICANT BIT) is the bit that has the smallest value or weight of all bits. This value is VFS/2n, where “VFS” is the full scale input voltage and “n” is the ADC resolution in bits. MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC12DL040 is guaranteed not to have any missing codes. MSB (MOST SIGNIFICANT BIT) is the bit that has the largest value or weight. Its value is one half of full scale. SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the input signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding d.c. SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input signal and the peak spurious signal, where a spurious signal is any signal present in the output spectrum that is not present at the input. TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB, of the rms total of the first nine harmonic levels at the output to the level of the fundamental at the output. THD is calculated as where f1 is the RMS power of the fundamental (output) frequency and f2 through f10 are the RMS power of the first 9 harmonic frequencies in the output spectrum. SECOND HARMONIC DISTORTION (2ND HARM) is the difference expressed in dB, between the RMS power in the input frequency at the output and the power in its 2nd harmonic level at the output. THIRD HARMONIC DISTORTION (3RD HARM) is the difference, expressed in dB, between the RMS power in the input frequency at the output and the power in its 3rd harmonic level at the output. 9 www.national.com ADC12DL040 NEGATIVE FULL SCALE ERROR is the difference between the actual first code transition and its ideal value of 1⁄2 LSB above negative full scale. Specification Definitions ADC12DL040 Timing Diagram 20100209 Output Timing www.national.com 10 ADC12DL040 Transfer Characteristic 20100210 FIGURE 1. Transfer Characteristic 11 www.national.com ADC12DL040 Typical Performance Characteristics DNL, INL Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.0V, VDR = +2.5V, PD = 0V, VREF = +1.0V, fCLK = 40 MHz, fIN = 0, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On, parallel output mode. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C DNL INL 20100241 20100245 DNL vs. fCLK INL vs. fCLK 20100242 20100246 DNL vs. Clock Duty Cycle INL vs. Clock Duty Cycle 20100243 www.national.com 20100247 12 DNL vs. Temperature INL vs. Temperature 20100244 20100248 DNL vs. VDR, VA = VD = 3.6V INL vs. VDR, VA = VD = 3.6V 20100270 20100271 13 www.national.com ADC12DL040 Typical Performance Characteristics DNL, INL Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.0V, VDR = +2.5V, PD = 0V, VREF = +1.0V, fCLK = 40 MHz, fIN = 0, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On, parallel output mode. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Continued) ADC12DL040 Typical Performance Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.0V, VDR = +2.5V, PD = 0V, VREF = +1.0V, fCLK = 40 MHz, fIN = 20 MHz, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On, parallel output mode. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C Distortion vs. VA SNR,SINAD,SFDR vs. VA 20100249 20100256 SNR,SINAD,SFDR vs. VDR, VA = VD = 3.6V Distortion vs. VDR, VA = VD = 3.6V 20100250 20100257 SNR,SINAD,SFDR vs. VCM Distortion vs. VCM 20100251 www.national.com 20100258 14 SNR,SINAD,SFDR vs. fCLK Distortion vs. fCLK 20100252 20100259 SNR,SINAD,SFDR vs. Clock Duty Cycle Distortion vs. Clock Duty Cycle 20100253 20100236 SNR,SINAD,SFDR vs. VREF Distortion vs. VREF 20100254 20100261 15 www.national.com ADC12DL040 Typical Performance Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.0V, VDR = +2.5V, PD = 0V, VREF = +1.0V, fCLK = 40 MHz, fIN = 20 MHz, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On, parallel output mode. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Continued) ADC12DL040 Typical Performance Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.0V, VDR = +2.5V, PD = 0V, VREF = +1.0V, fCLK = 40 MHz, fIN = 20 MHz, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On, parallel output mode. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Continued) SNR,SINAD,SFDR vs. fIN Distortion vs. fIN 20100239 20100240 SNR,SINAD,SFDR vs. Temperature Distortion vs. Temperature 20100255 20100262 tOD vs. VDR, VA = VD = 3.6V Parallel Output Mode tOD vs. VDR, VA = VD = 3.6V Multiplex Output Mode 20100263 www.national.com 20100267 16 Spectral Response @ 1 MHz Input Spectral Response @ 10 MHz Input 20100237 20100268 Intermodulation Distortion, fIN1= 9.6 MHz, fIN2 = 10.2 MHz Spectral Response @ 20 MHz Input 20100269 20100238 17 www.national.com ADC12DL040 Typical Performance Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.0V, VDR = +2.5V, PD = 0V, VREF = +1.0V, fCLK = 40 MHz, fIN = 20 MHz, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On, parallel output mode. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Continued) ADC12DL040 degraded noise performance. Loading any of these pins other than VRMA and VRMB may result in performance degradation. Functional Description Operating on a single +3.0V supply, the ADC12DL040 uses a pipeline architecture and has error correction circuitry to help ensure maximum performance. The differential analog input signal is digitized to 12 bits. The user has the choice of using an internal 1.0 Volt or 0.5 Volt stable reference, or using an external reference. Any external reference is buffered on-chip to ease the task of driving that pin. The nominal voltages for the reference bypass pins are as follows: VRM = 1.5 V VRP = VRM + VREF / 2 VRN = VRM − VREF / 2 The output word rate is the same as the clock frequency, which can be between 10 MSPS and 40 MSPS (typical) with fully specified performance at 40 MSPS. The analog input for both channels is acquired at the rising edge of the clock and the digital data for a given sample is delayed by the pipeline for 7 clock cycles. Duty cycle stablization and output data format are selectable using the quad state function DF/DCS pin. The output data can be set for offset binary or two’s complement. A logic high on the power down (PD) pin reduces the converter power consumption to 36 mW. User choice of an on-chip or external reference voltage is provided. The internal 1.0 Volt reference is in use when the the VREF pin is connected to VA. When the VREF pin is connected to AGND, the internal 0.5 Volt reference is in use. If a voltage in the range of 0.8V to 1.2V is applied to the VREF pin, that is used for the voltage reference. When an external reference is used, the VREF pin should be bypassed to ground with a 0.1 µF capacitor close to the reference input pin. There is no need to bypass the VREF pin when the internal reference is used. 1.3 Signal Inputs The signal inputs are VIN A+ and VINA− for one ADC and VINB+ and VINB− for the other ADC . The input signal, VIN, is defined as VIN A = (VINA+) – (VINA−) for the "A" converter and VIN B = (VINB+) – (VINB−) Applications Information 1.0 OPERATING CONDITIONS We recommend that the following conditions be observed for operation of the ADC12DL040: 2.7V ≤ VA ≤ 3.6V VD = V A 2.4V ≤ VDR ≤ VA 10 MHz ≤ fCLK ≤ 40 MHz 0.8V ≤ VREF ≤ 1.2V (for an external reference) for the "B" converter. Figure 2 shows the expected input signal range. Note that the common mode input voltage, VCM, should be in the range of 0.5V to 2.0V. The peaks of the individual input signals should each never exceed 2.6V. 0.5V ≤ VCM ≤ 2.0V The ADC12DL040 performs best with a differential input signal with each input centered around a common mode voltage, VCM. The peak-to-peak voltage swing at each analog input pin should not exceed the value of the reference voltage or the output data will be clipped. The two input signals should be exactly 180˚ out of phase from each other and of the same amplitude. For single frequency inputs, angular errors result in a reduction of the effective full scale input. For complex waveforms, however, angular errors will result in distortion. 1.1 Analog Inputs There is one reference input pin, VREF, which is used to select an internal reference, or to supply an external reference. The ADC12DL040 has two analog signal input pairs, VIN A+ and VIN A- for one converter and VIN B+ and VIN Bfor the other converter. Each pair of pins forms a differential input pair. 1.2 Reference Pins The ADC12DL040 is designed to operate with an internal 1.0V or 0.5V reference, or an external 1.0V reference, but performs well with external reference voltages in the range of 0.8V to 1.2V. Lower reference voltages will decrease the signal-to-noise ratio (SNR) of the ADC12DL040. Increasing the reference voltage (and the input signal swing) beyond 1.2V may degrade THD for a full-scale input, especially at higher input frequencies. It is important that all grounds associated with the reference voltage and the analog input signal make connection to the ground plane at a single, quiet point to minimize the effects of noise currents in the ground path. The six Reference Bypass Pins (VRPA, VRMA, VRNA, VRPB, VRMB and VRNB) are made available for bypass purposes. All these pins should each be bypassed to ground with a 0.1 µF capacitor. A 10 µF capacitor should be placed between the VRPA and VRNA pins and between the VRPB and VRNB pins, as shown in Figure 4. This configuration is necessary to avoid reference oscillation, which could result in reduced SFDR and/or SNR. Smaller capacitor values than those specified will allow faster recovery from the power down mode, but may result in www.national.com 20100211 FIGURE 2. Expected Input Signal Range For single frequency sine waves the full scale error in LSB can be described as approximately EFS = 4096 ( 1 - sin (90˚ + dev)) 18 TABLE 2. Input to Output Relationship – Single-Ended Input (Continued) Where dev is the angular difference in degrees between the two signals having a 180˚ relative phase relationship to each other (see Figure 3). Drive the analog inputs with a source impedance less than 100Ω. 20100212 FIGURE 3. Angular Errors Between the Two Input Signals Will Reduce the Output Level or Cause Distortion VIN+ VIN− Binary Output 2’s Complement Output VCM − VREF VCM 0000 0000 0000 1000 0000 0000 VCM − VREF/2 VCM 0100 0000 0000 1100 0000 0000 VCM VCM 1000 0000 0000 0000 0000 0000 VCM + VREF/2 VCM 1100 0000 0000 0100 0000 0000 VCM + VREF VCM 1111 1111 1111 0111 1111 1111 VIN+ VIN− Binary Output 2’s Complement Output VCM − VREF/2 VCM + VREF/2 0000 0000 0000 1000 0000 0000 1.3.2 Driving the Analog Inputs The VIN+ and the VIN− inputs of the ADC12DL040 consist of an analog switch followed by a switched-capacitor amplifier. The capacitance seen at the analog input pins changes with the clock level, appearing as 8 pF when the clock is low, and 7 pF when the clock is high. As the internal sampling switch opens and closes, current pulses occur at the analog input pins, resulting in voltage spikes at the signal input pins. As a driving amplifier attempts to counteract these voltage spikes, a damped oscillation may appear at the ADC analog input. Do not attempt to filter out these pulses. Rather, use amplifiers to drive the ADC12DL040 input pins that are able to react to these pulses and settle before the switch opens and another sample is taken. The LMH6702 LMH6628, LMH6622 and the LMH6655 are good amplifiers for driving the ADC12DL040. To help isolate the pulses at the ADC input from the amplifier output, use RCs at the inputs, as can be seen in Figure 4 through Figure 6 . These components should be placed close to the ADC inputs because the input pins of the ADC is the most sensitive part of the system and this is the last opportunity to filter that input. For Nyquist applications the RC pole should be at the ADC sample rate. The ADC input capacitance in the sample mode should be considered when setting the RC pole. For wideband undersampling applications, the RC pole should be set at about 1.5 to 2 times the maximum input frequency to maintain a linear delay response. A single-ended to differential conversion circuit is shown in Figure 6. Table 3 gives resistor values for that circuit to provide input signals in a range of 1.0V ± 0.5V at each of the differential input pins of the ADC12DL040. VCM − VREF/4 VCM + VREF/4 0100 0000 0000 1100 0000 0000 TABLE 3. Resistor Values for Circuit of Figure 6 VCM VCM 1000 0000 0000 0000 0000 0000 VCM + VREF/4 VCM − VREF/4 1100 0000 0000 0100 0000 0000 VCM + VREF/2 VCM − VREF/2 For differential operation, each analog input pin of the differential pair should have a peak-to-peak voltage equal to the reference voltage, VREF, be 180 degrees out of phase with each other and be centered around VCM. 1.3.1 Single-Ended Operation Performance with differential input signals is better than with single-ended signals. For this reason, single-ended operation is not recommended. However, if single ended-operation is required and the resulting performance degradation is acceptable, one of the analog inputs should be connected to the d.c. mid point voltage of the driven input. The peak-topeak differential input signal at the driven input pin should be twice the reference voltage to maximize SNR and SINAD performance (Figure 2b). For example, set VREF to 0.5V, bias VIN− to 1.0V and drive VIN+ with a signal range of 0.5V to 1.5V. Because very large input signal swings can degrade distortion performance, better performance with a single-ended input can be obtained by reducing the reference voltage when maintaining a full-range output. Table 1 and Table 2 indicate the input to output relationship of the ADC12DL040. TABLE 1. Input to Output Relationship – Differential Input 1111 1111 1111 0111 1111 1111 SIGNAL RANGE R1 0 - 0.25V open 0Ω 124Ω 1500Ω 1000Ω 0 - 0.5V 0Ω openΩ 499Ω 1500Ω 499Ω ± 0.25V 100Ω 698Ω 100Ω 698Ω 499Ω R2 R3 R4 R5, R6 1.3.3 Input Common Mode Voltage The input common mode voltage, VCM, should be in the range of 0.5V to 2.0V and be a value such that the peak excursions of the analog signal does not go more negative than ground or more positive than 2.6V. See Section 1.2 19 www.national.com ADC12DL040 Applications Information ADC12DL040 Applications Information 2.3 PD The PD pin, when high, holds the ADC12DL040 in a powerdown mode to conserve power when the converter is not being used. The power consumption in this state is 36 mW with a 40MHz clock and 40mW if the clock is stopped when PD is high. The output data pins are undefined and the data in the pipeline is corrupted while in the power down mode. The Power Down Mode Exit Cycle time is determined by the value of the components on pins 4, 5, 6, 12, 13 and 14 and is about 500 µs with the recommended components on the VRP, VRM and VRN reference bypass pins. These capacitors loose their charge in the Power Down mode and must be recharged by on-chip circuitry before conversions can be accurate. Smaller capacitor values allow slightly faster recovery from the power down mode, but can result in a reduction in SNR, SINAD and ENOB performance. (Continued) 2.0 DIGITAL INPUTS Digital TTL/CMOS compatible inputs consist of CLK, OEA, OEB, PD, DF/DCS, and MULTIPLEX. 2.1 CLK The CLK signal controls the timing of the sampling process. Drive the clock input with a stable, low jitter clock signal in the range indicated in the Electrical Table with rise and fall times of 2 ns or less. The trace carrying the clock signal should be as short as possible and should not cross any other signal line, analog or digital, not even at 90˚. The CLK signal also drives an internal state machine. If the CLK is interrupted, or its frequency too low, the charge on internal capacitors can dissipate to the point where the accuracy of the output data will degrade. This is what limits the minimum sample rate. 2.4 DF/DCS Duty cycle stablization and output data format are selectable using this quad state function pin. When enabled, duty cycle stabilization can compensate for clock inputs with duty cycles ranging from 20% to 80% and generate a stable internal clock, improving the performance of the part. The Duty Cycle Stabilizer circuit requires a fast clock edge to produce the internal clock, which is the reason for the rise and fall time requirement listed in the specifications table. With DF/DCS = VA the output data format is offset binary and duty cycle stabilization is applied to the clock. With DF/DCS = 0 the output data format is 2’s complement and duty cycle stabilization is applied to the clock. With DF/DCS = VRMA or VRMB the output data format is 2’s complement and duty cycle stabilization is not used. If DF/DCS is floating, the output data format is offset binary and duty cycle stabilization is not used. While the sense of this pin may be changed "on the fly," doing this is not recommended as the output data could be erroneous for a few clock cycles after this change is made. The clock line should be terminated at its source in the characteristic impedance of that line. Take care to maintain a constant clock line impedance throughout the length of the line. Refer to Application Note AN-905 for information on setting characteristic impedance. It is highly desirable that the the source driving the ADC CLK pin only drive that pin. However, if that source is used to drive other things, each driven pin should be a.c. terminated with a series RC to ground, as shown in Figure 4, such that the resistor value is equal to the characteristic impedance of the clock line and the capacitor value is where tPD is the signal propagation rate down the clock line, "L" is the line length and ZO is the characteristic impedance of the clock line. This termination should be as close as possible to the ADC clock pin but beyond it as seen from the clock source. Typical tPD is about 150 ps/inch (60 ps/cm) on FR-4 board material. The units of "L" and tPD should be the same (inches or centimeters). 2.5 MULTIPLEX With the MULTIPLEX pin at a logic low, the digital output words from channels A and B are available on separate digital output buses (Parallel mode). When MULTIPLEX is high, the digital output words are multiplexed on pins DA0:DA11 (Multiplex Mode). The DB0/ABb pin changes synchronously with the multiplexed outputs, and is high when channel A data is present on the outputs, and low when channel B data is present. The duty cycle of the clock signal can affect the performance of the A/D Converter. Because achieving a precise duty cycle is difficult, the ADC12DL040 has a Duty Cycle Stabilizer which can be enabled using the DF/DCS pin. It is designed to maintain performance over a clock duty cycle range of 20% to 80% at 40 MSPS. The Duty Cycle Stabilizer circuit requires a fast clock edge to produce the internal clock, which is the reason for the rise and fall time requirement listed in the specifications table. 3.0 OUTPUTS The ADC12DL040 has 12 TTL/CMOS compatible Data Output pins for each output. Valid data is present at these outputs while the OE and PD pins are low. In the parallel mode, the data should be captured with the CLK signal. Depending on the setup and hold time requirements of the receiving circuit (ASIC), either the rising edge or the falling edge of the CLK signal can be used to latch the data. Generally, rising-edge- -capture would maximize setup time with minimal hold time; while falling-edge-capture would maximize hold time with minimal setup time. However, actual timing for the falling-edge case depends greatly on the CLK frequency and both cases also depend on the delays inside the ASIC. Refer to the Tod spec in the AC Electrical Characterisitics table. In Multiplex mode, both channel outputs are available on DA0:DA11. The ABb signal is available to de-multiplex the output bus. The ABb signal may also be used to latch the 2.2 OEA, OEB The OEA and OEB pins, when high, put the output pins of their respective converters into a high impedance state. When either of these pin is low, the corresponding outputs are in the active state. The ADC12DL040 will continue to convert whether these pins are high or low, but the output can not be read while the pin is high. Since ADC noise increases with increased output capacitance at the digital output pins, do not use the TRI-STATE outputs of the ADC12DL040 to drive a bus. Rather, each output pin should be located close to and drive a single digital input pin. To further reduce ADC noise, a 100 Ω resistor in series with each ADC digital output pin, located close to their respective pins, should be added to the circuit. www.national.com 20 bypassing, limiting output capacitance and careful attention to the ground plane will reduce this problem. Additionally, bus capacitance beyond the specified 15 pF/pin will cause tOD to increase, making it difficult to properly latch the ADC output data. The result could be an apparent reduction in dynamic performance. (Continued) data in the ASIC thus avoiding the use of the CLK signal altogether. However, since the ABb signal edges are provided in-phase with the data transitions, generally the ASIC circuitry would have to delay the ABb signal with respect to the data in order to use it as the clock for the capturing latches. It is also possible to use the CLK signal to latch the data in the multiplexed mode as well - as described in the previous paragraph. Be very careful when driving a high capacitance bus. The more capacitance the output drivers must charge for each conversion, the more instantaneous digital current flows through VDR and DR GND. These large charging current spikes can cause on-chip ground noise and couple into the analog circuitry, degrading dynamic performance. Adequate To minimize noise due to output switching, minimize the load currents at the digital outputs. This can be done by connecting buffers (74ACQ541, for example) between the ADC outputs and any other circuitry. Only one driven input should be connected to each output pin. Additionally, inserting series resistors of about 100Ω at the digital outputs, close to the ADC pins, will isolate the outputs from trace and other circuit capacitances and limit the output currents, which could otherwise result in performance degradation. See Figure 4. 20100213 FIGURE 4. Application Circuit using Transformer or Differential Op-Amp Drive Circuit, Parallel mode 21 www.national.com ADC12DL040 Applications Information ADC12DL040 Applications Information (Continued) 20100266 FIGURE 5. Application Circuit using Transformer or Differential Op-Amp Drive Circuit, Multiplex mode 20100214 FIGURE 6. Differential Drive Circuit of Figure 4 www.national.com 22 (Continued) 4.0 POWER SUPPLY CONSIDERATIONS The power supply pins should be bypassed with a 10 µF capacitor and with a 0.1 µF ceramic chip capacitor within a centimeter of each power pin. Leadless chip capacitors are preferred because they have low series inductance. Digital circuits create substantial supply and ground current transients. The logic noise thus generated could have significant impact upon system noise performance. The best logic family to use in systems with A/D converters is one which employs non-saturating transistor designs, or has low noise characteristics, such as the 74LS, 74HC(T) and 74AC(T)Q families. The worst noise generators are logic families that draw the largest supply current transients during clock or signal edges, like the 74F and the 74AC(T) families. As is the case with all high-speed converters, the ADC12DL040 is sensitive to power supply noise. Accordingly, the noise on the analog supply pin should be kept below 100 mVP-P. No pin should ever have a voltage on it that is in excess of the supply voltages, not even on a transient basis. Be especially careful of this during power turn on and turn off. The VDR pin provides power for the output drivers and may be operated from a supply in the range of 2.4V to VD. This can simplify interfacing to lower voltage devices and systems. Note, however, that tOD increases with reduced VDR. DO NOT operate the VDR pin at a voltage higher than VD. The effects of the noise generated from the ADC output switching can be minimized through the use of 100Ω resistors in series with each data output line. Locate these resistors as close to the ADC output pins as possible. Since digital switching transients are composed largely of high frequency components, total ground plane copper weight will have little effect upon the logic-generated noise. This is because of the skin effect. Total surface area is more important than is total ground plane volume. Generally, analog and digital lines should cross each other at 90˚ to avoid crosstalk. To maximize accuracy in high speed, high resolution systems, however, avoid crossing analog and digital lines altogether. It is important to keep clock lines as short as possible and isolated from ALL other lines, including other digital lines. Even the generally accepted 90˚ crossing should be avoided with the clock line as even a little coupling can cause problems at high frequencies. This is because other lines can introduce jitter into the clock line, which can lead to degradation of SNR. Also, the high speed clock can introduce noise into the analog chain. Best performance at high frequencies and at high resolution is obtained with a straight signal path. That is, the signal path through all components should form a straight line wherever possible. 5.0 LAYOUT AND GROUNDING Proper grounding and proper routing of all signals are essential to ensure accurate conversion. Maintaining separate analog and digital areas of the board, with the ADC12DL040 between these areas, is required to achieve specified performance. The ground return for the data outputs (DR GND) carries the ground current for the output drivers. The output current can exhibit high transients that could add noise to the conversion process. To prevent this from happening, the DR GND pins should NOT be connected to system ground in close proximity to any of the ADC12DL040’s other ground pins. Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor performance. The solution is to keep the analog circuitry separated from the digital circuitry, and to keep the clock line as short as possible. 23 www.national.com ADC12DL040 Applications Information ADC12DL040 Applications Information (Continued) 20100216 FIGURE 7. Example of a Suitable Layout Be especially careful with the layout of inductors. Mutual inductance can change the characteristics of the circuit in which they are used. Inductors should not be placed side by side, even with just a small part of their bodies beside each other. The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input. Any external component (e.g., a filter capacitor) connected between the converter’s input pins and ground or to the reference input pin and ground should be connected to a very clean point in the ground plane. Figure 7 gives an example of a suitable layout. All analog circuitry (input amplifiers, filters, reference components, etc.) should be placed in the analog area of the board. All digital circuitry and I/O lines should be placed in the digital area of the board. The ADC12DL040 should be between these two areas. Furthermore, all components in the reference circuitry and the input signal chain that are connected to ground should be connected together with short traces and enter the ground plane at a single, quiet point. All ground connections should have a low inductance path to ground. www.national.com 6.0 DYNAMIC PERFORMANCE To achieve the best dynamic performance, the clock source driving the CLK input must be free of jitter. Isolate the ADC clock from any digital circuitry with buffers, as with the clock tree shown in Figure 8. The gates used in the clock tree must be capable of operating at frequencies much higher than those used if added jitter is to be prevented. Best performance will be obtained with a differential input drive, compared with a single-ended drive, as discussed in Sections 1.3.1 and 1.3.2. As mentioned in Section 5.0, it is good practice to keep the ADC clock line as short as possible and to keep it well away from any other signals. Other signals can introduce jitter into the clock signal, which can lead to reduced SNR performance, and the clock can introduce noise into other lines. Even lines with 90˚ crossings have capacitive coupling, so try to avoid even these 90˚ crossings of the clock line. 24 The digital data outputs should be buffered (with 74ACQ541, for example). Dynamic performance can also be improved by adding series resistors at each digital output, close to the ADC12DL040, which reduces the energy coupled back into the converter output pins by limiting the output current. A reasonable value for these resistors is 100Ω. (Continued) Using an inadequate amplifier to drive the analog input. As explained in Section 1.3, the capacitance seen at the input alternates between 8 pF and 7 pF, depending upon the phase of the clock. This dynamic load is more difficult to drive than is a fixed capacitance. If the amplifier exhibits overshoot, ringing, or any evidence of instability, even at a very low level, it will degrade performance. A small series resistor at each amplifier output and a capacitor at the analog inputs (as shown in Figure 5 and Figure 6) will improve performance. The LMH6702 and the LMH6628 have been successfully used to drive the analog inputs of the ADC12DL040. 20100217 FIGURE 8. Isolating the ADC Clock from other Circuitry with a Clock Tree Also, it is important that the signals at the two inputs have exactly the same amplitude and be exactly 180o out of phase with each other. Board layout, especially equality of the length of the two traces to the input pins, will affect the effective phase between these two signals. Remember that an operational amplifier operated in the non-inverting configuration will exhibit more time delay than will the same device operating in the inverting configuration. Operating with the reference pins outside of the specified range. As mentioned in Section 1.2, when using an external reference, VREF should be in the range of 0.8V ≤ VREF ≤ 1.2V Operating outside of these limits could lead to performance degradation. Inadequate network on Reference Bypass pins (VRPA, VRNA, VRMA, VRPB, VRNB and VRMB). As mentioned in Section 1.2, these pins should be bypassed with 0.1 µF capacitors to ground, and 10.0 µF capacitor should be connected between pins VRPA and VRNA and between VRPB and VRNB for best performance. Using a clock source with excessive jitter, using excessively long clock signal trace, or having other signals coupled to the clock signal trace. This will cause the sampling interval to vary, causing excessive output noise and a reduction in SNR and SINAD performance. 7.0 COMMON APPLICATION PITFALLS Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, all inputs should not go more than 100 mV beyond the supply rails (more than 100 mV below the ground pins or 100 mV above the supply pins). Exceeding these limits on even a transient basis may cause faulty or erratic operation. It is not uncommon for high speed digital components (e.g., 74F and 74AC devices) to exhibit overshoot or undershoot that goes above the power supply or below ground. A resistor of about 47Ω to 100Ω in series with any offending digital input, close to the signal source, will eliminate the problem. Do not allow input voltages to exceed the supply voltage, even on a transient basis. Not even during power up or power down. Be careful not to overdrive the inputs of the ADC12DL040 with a device that is powered from supplies outside the range of the ADC12DL040 supply. Such practice may lead to conversion inaccuracies and even to device damage. Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers must charge for each conversion, the more instantaneous digital current flows through VDR and DR GND. These large charging current spikes can couple into the analog circuitry, degrading dynamic performance. Adequate bypassing and maintaining separate analog and digital areas on the pc board will reduce this problem. Additionally, bus capacitance beyond the specified 15 pF/pin will cause tOD to increase, making it difficult to properly latch the ADC output data. The result could, again, be an apparent reduction in dynamic performance. 25 www.national.com ADC12DL040 Applications Information ADC12DL040 Dual 12-Bit, 40 MSPS, 3V, 210mW A/D Converter Physical Dimensions inches (millimeters) unless otherwise noted 64-Lead TQFP Package Ordering Number ADC12DL040CIVS NS Package Number VECO64A National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. 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