A5841: BiMOS II 8-Bit Serial-Input, Latched Drivers

A5841
BiMOS II 8-Bit Serial Input Latched Driver
Discontinued Product
These parts are no longer in production The device should not be
purchased for new design applications. Samples are no longer available.
Date of status change: October 31, 2005
Recommended Substitutions:
For new customers or new applications, refer to the A6841.
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan for a
product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The information
included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor
for any infringements of patents or other rights of third parties which may result from its use.
Data Sheet
26185.14G
5841
BiMOS II 8-BIT SERIAL-INPUT,
LATCHED DRIVERS
UCN5841A
CLOCK
2
SERIAL
DATA IN
3
LOGIC
GROUND
4
LOGIC
SUPPLY
5
SERIAL
DATA OUT
6
STROBE
7
OUTPUT
ENABLE
8
VEE
9
18
OUT 1
17
OUT 2
16
OUT 3
15
OUT 4
14
OUT 5
13
OUT 6
ST
12
OUT 7
OE
11
OUT 8
10
K
SUB
CLK
VDD
LATCHES
1
SHIFT REGISTER
VEE
SUB
Dwg. PP-026-1
Note that the UCN5841A (dual in-line package) and
UCN5841LW (small-outline IC package) are electrically
identical and share a common terminal number assignment.
ABSOLUTE MAXIMUM RATINGS
at 25°C Free-Air Temperature
Output Voltage, VCE . . . . . . . . . . . . . . 50 V
Output Voltage, VCE(sus) . . . . . . . . . . 35 V†
Logic Supply Voltage Range,
VDD . . . . . . . . . . . . . . . . 4.5 V to 15 V
VDD with Reference to VEE . . . . . 25 V
Emitter Supply Voltage, VEE . . . . . . . -20 V
Input Voltage Range,
VIN . . . . . . . . . . . -0.3 V to VDD + 0.3 V
Continuous Output Current,
IOUT . . . . . . . . . . . . . . . . . . . . 500 mA
Package Power Dissipation,
PD . . . . . . . . . . . . . . . . . . . See Graph
Operating Temperature Range,
TA . . . . . . . . . . . . . . . . -20°C to +85°C
Storage Temperature Range,
TS . . . . . . . . . . . . . . . -55°C to +150°C
†For inductive load applications.
Caution: CMOS devices have input static protection
but are susceptible to damage when exposed to
extremely high static electrical charges.
The merging of low-power CMOS logic and bipolar output power
drivers permit the UCN5841A, UCN5841LW, and A5841SLW integrated circuits to be used in a wide variety of peripheral power driver
applications. Each device has an eight-bit CMOS shift register and
CMOS control circuitry, eight CMOS data latches, and eight bipolar
current-sinking Darlington output drivers. The 500 mA npn Darlington
outputs, with integral transient-suppression diodes, are suitable for use
with relays, solenoids, and other inductive loads. All drivers can be
operated with a split supply where the negative supply is up to -20 V.
BiMOS II devices have higher data-input rates than the earlier
BiMOS circuits. With a 5 V logic supply, they will typically operate at
better than 5 MHz. With a 12 V supply, significantly higher speeds are
obtained. The CMOS inputs are compatible with standard CMOS and
NMOS logic levels. TTL circuits may require the use of appropriate
pull-up resistors. By using the serial data output, drivers can be
cascaded for interface applications requiring additional drive lines.
The UCN5841A devices are furnished in a standard 18-pin plastic
DIP; the UCN5841LW devices are in an 18-lead surface-mountable
wide-body SOIC package; the A5841SLW devices are provided in a
20-lead wide-body SOIC package with improved thermal characteristics.
The A5841SLW and UCN5841LW drivers are also available for
operation to a temperature of -40°C. To order, change the suffix from
‘SLW’ to ‘ELW’, or change the prefix from ‘UCN’ to ‘UCQ’.
FEATURES
■ To 3.3 MHz Data-Input Rate
■ CMOS, NMOS, TTL Compatible Inputs
■ Internal Pull-Up/Pull-Down Resistors
■ Low-Power CMOS Logic and Latches,
■ High-Voltage Current-Sink Outputs
■ Output Transient-Protection Diodes
■ Single or Split Supply Operation
■ DIP or SOIC Packaging
■ Automotive Capable
Always order by complete part number, e.g., A5841SLW .
5841
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
FUNCTIONAL BLOCK DIAGRAM
(‘A’ Package Shown)
CLOCK
2
SERIAL
DATA IN
3
LOGIC
GROUND
4
5
LOGIC
SUPPLY
SERIAL-PARALLEL SHIFT REGISTER
6
SERIAL
DATA OUT
LATCHES
7
STROBE
8
OUTPUT ENABLE
(ACTIVE LOW)
VDD
MOS
BIPOLAR
1
18
17
16
15
14
13
12
11
OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 OUT 8
9
10
K
POWER
GROUND
SUB
Dwg. FP-013-2
2.5
POWER
GROUND
1
CLOCK
2
SERIAL
DATA IN
3
GROUND
4
LOGIC SUPPLY
5
SERIAL
DATA OUT
6
STROBE
7
OUTPUT
ENABLE
8
POWER
GROUND
9
OUT 1
19
OUT 2
18
OUT 3
17
OUT 4
16
OUT 5
15
OUT 6
ST
14
OUT 7
OE
13
OUT 8
12
K
11
NO
CONNECT.
SUB
CLK
LATCHES
VDD
SHIFT REGISTER
NO
CONNECT.
20
SUB
10
NC
NC
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
A5841SLW
2.0
18-PIN DIP, RθJA = 60°C/W
20-LEAD SOIC, RθJA = 90°C/W
18-LEAD SOIC, RθJA = 94°C/W
1.5
1.0
0.5
0
25
Dwg. PP-029-3
50
75
100
125
AMBIENT TEMPERATURE IN °C
150
Dwg. GP-022-4A
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1985, 2004 Allegro MicroSystems, Inc.
5841
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V, VEE = 0 V
(unless otherwise specified).
Limits
Characteristic
Output Leakage Current
Collector-Emitter
Collector-Emitter
Input Voltage
Symbol
Min.
Max.
Unit
VOUT = 50 V
—
50
µA
VOUT = 50 V, TA = +70°C
—
100
µA
IOUT = 100 mA
—
1.1
V
IOUT = 200 mA
—
1.3
V
IOUT = 350 mA, VDD = 7.0 V
—
1.6
V
IOUT = 350 mA, L = 2 mH
35
—
V
—
0.8
V
VDD = 12 V
10.5
—
V
VDD = 10 V
8.5
—
V
VDD = 5.0 V
3.5
—
V
VDD = 12 V
50
—
kΩ
VDD = 10 V
50
—
kΩ
VDD = 5.0 V
50
—
kΩ
All Drivers ON, VDD = 12 V
—
16
mA
All Drivers ON, VDD = 10 V
—
14
mA
All Drivers ON, VDD = 5.0 V
—
8.0
mA
All Drivers OFF, VDD = 12 V
—
2.9
mA
All Drivers OFF, VDD = 10 V
—
2.5
mA
All Drivers OFF, VDD = 5.0 V
—
1.6
mA
IR
VR = 50 V
—
50
µA
VF
IF = 350 mA
—
2.0
V
ICEX
VCE(SAT)
VCE(sus)
VIN(0)
VIN(1)
Input Resistance
Supply Current
RIN
IDD(ON)
IDD(OFF)
Clamp Diode
Test Conditions
Leakage Current
Clamp Diode
Forward Voltage
www.allegromicro.com
5841
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
CLOCK
TYPICAL INPUT CIRCUITS
D
A
B
V
DD
DATA IN
E
F
C
STROBE
STROBE
IN
OUTPUT
ENABLE
OUTPUT
ENABLE
G
OUT N
Dwg. No. A-12,627
Dwg. EP-010-3
VDD
TIMING CONDITIONS
(TA = +25°C, VDD = 5.0 V, Logic Levels are VDD and Ground)
A. Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ns
CLOCK
SERIAL
DATA IN
B. Minimum Data Active Time After Clock Pulse
(Data Hold Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ns
C. Minimum Data Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 ns
D. Minimum Clock Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 ns
E. Minimum Time Between Clock Activation and Strobe . . . . . . . . . . . . 300 ns
F. Minimum Strobe Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ns
Dwg. EP-010-4A
TYPICAL OUTPUT DRIVER
K
OUT
V
EE
SUB
Dwg. EP-021-8
G. Typical Time Between Strobe Activation and
Output Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.0 µs
Serial Data present at the input is transferred to the shift register
on the logic “0” to logic “1” transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data information towards
the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input waveform.
Information present at any register is transferred to its respective
latch when the STROBE is high (serial-to-parallel conversion). The
latches will continue to accept new data as long as the STROBE is held
high. Applications where the latches are bypassed (STROBE tied high)
will require that the ENABLE input be high during serial data entry.
When the ENABLE input is high, all of the output buffers are
disabled (OFF) without affecting the information stored in the latches or
shift register. With the ENABLE input low, the outputs are controlled by
the state of the latches.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5841
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
TRUTH TABLE
Serial
Shift Register Contents
Data Clock
Input Input I1 I2 I3 .............. I8
Serial
Data Strobe
Output Input
Latch Contents
I1
I2
I3
.............. I8
Output Contents
Output
Enable
I1 I2 I3 ..............
I8
P8
H
H
R1 R2 .............. R7
R7
L
L
R1 R2 .............. R7
R7
X
R1 R2 R3 .............. R8
R8
X
X
L
R1 R2 R3 .............. R8
P8
H
P1 P2 P3 .............. P8
L
P1 P2 P3 ..............
X
H
H H H .............. H
X
X
.............. X
P1 P2 P3 .............. P8
L = Low Logic Level
H = High Logic Level
X = Irrelevant
X
X
P = Present State
.............. X
R = Previous State
The products described here are manufactured
under one or more U.S. patents or U.S. patents
pending.
Allegro MicroSystems, Inc. reserves the right to
make, from time to time, such departures from the detail
specifications as may be required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an
order, the user is cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as
critical components in life-support devices or systems
without express written approval.
The information included herein is believed to be
accurate and reliable. However, Allegro
MicroSystems, Inc. assumes no responsibility for its
use; nor for any infringement of patents or other rights
of third parties which may result from its use.
www.allegromicro.com
5841
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
UCN5841A
Dimensions in Inches
(controlling dimensions)
18
0.014
0.008
10
0.430
MAX
0.280
0.240
0.300
BSC
1
0.070
0.045
9
0.100
0.920
0.880
BSC
0.005
MIN
0.210
MAX
0.015
0.150
0.115
MIN
0.022
0.014
Dwg. MA-001-18A in
Dimensions in Millimeters
(for reference only)
18
0.355
0.204
10
10.92
MAX
7.11
6.10
7.62
BSC
1
1.77
1.15
2.54
23.37
22.35
9
BSC
0.13
MIN
5.33
MAX
0.39
3.81
2.93
MIN
0.558
0.356
Dwg. MA-001-18A mm
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Lead thickness is measured at seating plane or below.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5841
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
UCN5841LW
Dimensions in Inches
(for reference only)
18
10
0.0125
0.0091
0.419
0.394
0.2992
0.2914
0.050
0.016
0.020
0.013
1
2
0.050
3
0° TO 8°
BSC
0.4625
0.4469
0.0926
0.1043
0.0040 MIN.
Dwg. MA-008-18A in
Dimensions in Millimeters
(controlling dimensions)
18
10
0.32
0.23
10.65
10.00
7.60
7.40
1.27
0.40
0.51
0.33
1
2
1.27
3
11.75
11.35
BSC
0° TO 8°
2.65
2.35
0.10 MIN.
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
www.allegromicro.com
Dwg. MA-008-18A mm
5841
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
A5841SLW
Dimensions in Inches
(for reference only)
20
11
0.0125
0.0091
0.419
0.394
0.2992
0.2914
0.050
0.016
0.020
0.013
1
2
0.050
3
0.5118
0.4961
0° TO 8°
BSC
0.0926
0.1043
Dwg. MA-008-20 in
0.0040 MIN.
Dimensions in Millimeters
(controlling dimensions)
20
11
0.32
0.23
10.65
10.00
7.60
7.40
1.27
0.40
0.51
0.33
1
2
1.27
3
13.00
12.60
BSC
0° TO 8°
2.65
2.35
Dwg. MA-008-20 mm
0.10 MIN.
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
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