A6275: 8-Bit Serial-Input, Constant-Current Latched LED Driver

A6275
8-Bit Serial Input Constant-Current Latched LED Driver
Last Time Buy
This part is in production but has been determined to be
LAST TIME BUY. This classification indicates that the product is
obsolete and notice has been given. Sale of this device is currently
restricted to existing customer applications. The device should not be
purchased for new design applications because of obsolescence in the
near future. Samples are no longer available.
Date of status change: November 1, 2010
Deadline for receipt of LAST TIME BUY orders: April 30, 2011
Recommended Substitutions:
For existing customer transition, and for new customers or new applications, contact Allegro Sales.
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
A6275
8-Bit Serial Input Constant-Current Latched LED Driver
Features and Benefits
Description
▪ Up to 90 mA constant-current outputs
▪ Undervoltage lockout
▪ Low-power CMOS logic and latches
▪ High data-input rate
▪ Pin-compatible with TB62705CP
The A6275 is specifically designed for LED display applications.
Each BiCMOS device includes an 8-bit CMOS shift register,
accompanying data latches, and eight NPN constant-current
sink drivers.
The CMOS shift register and latches allow direct interfacing
with microprocessor-based systems. With a 5 V logic supply,
typical serial data-input rates are up to 20 MHz. The LED drive
current is determined by the user selection of a single resistor.
A CMOS serial data output permits cascade connections in
applications requiring additional drive lines. For inter-digit
blanking, all output drivers can be disabled with an ENABLE
input high. A similar 150 mA output device is available as the
A6277; a similar 16-bit device is available as the A6276.
Packages
16-pin DIP
(A package)
Not to scale
16-pin SOICW
(LW package)
Two package styles are provided: a through-hole DIP (suffix
A) and a surface-mount SOICW (suffix LW). Under normal
applications, copper leadframes and low logic-power dissipation
allow these devices to sink maximum rated current through
all outputs continuously over the operating temperature range
(90 mA, 0.9 V drop, 85°C). Both packages are lead (Pb) free,
with 100% matte tin leadframe plating.
Functional Block Diagram
UVLO
CLOCK
SERIAL
DATA IN
SERIAL-PARALLEL SHIFT REGISTER
LATCH
ENABLE
LATCHES
VDD
LOGIC
SUPPLY
SERIAL
DATA OUT
OUTPUT ENABLE
(ACTIVE LOW)
GROUND
MOS
BIPOLAR
IO
REGULATOR
OUT 0 OUT 1 OUT 2
26185.200F
OUT N
R
EXT
Dwg. FP-013-3
Serial-Input Constant-Current Latched LED Driver
with Open LED Detection and Dot Correction
A6275
Selection Guide
Part Number
Package
Packing
A6275EA-T
A6275ELWTR-T
A6275SLWTR-T
16-pin DIP
16-pin SOICW
16-pin SOICW
25 per tube
1000 per reel
1000 per reel
Ambient Temperature
(°C)
–40 to 85
–20 to 85
Absolute Maximum Ratings*
Characteristic
Symbol
Rating
Units
VDD
7.0
V
Input Voltage Range
VI
–0.4 to VDD + 0.4
V
Output Voltage Range
VO
–0.5 to VDD + 17
V
Supply Voltage
Notes
Output Current
IO
90
mA
Ground Current
IGND
750
mA
Range E
–40 to 85
ºC
Range S
Operating Ambient Temperature
TA
–20 to 85
ºC
Maximum Junction Temperature
TJ(max)
150
ºC
Tstg
–55 to 150
ºC
Storage Temperature
*These CMOS devices have input static protection (Class 2) but are still susceptible to damage if exposed to extremely high static
electrical charges.
Thermal Characteristics may require derating at maximum conditions, see application information
Characteristic
Symbol
RθJA
Package Thermal Resistance
Test Conditions*
Value Units
Package A, 4-layer PCB based on JEDEC standard
38
ºC/W
Package LW, 4-layer PCB based on JEDEC standard
48
ºC/W
*Additional thermal information available on the Allegro website.
Power Dissipation versus Ambient Temperature
3500
3250
3000
Power Dissipation, PD (mW)
2750
2500
2250
(R
QJ
2000
1750
(R
1500
QJ
1250
1000
Pa
A
Pa
A
ck
a
= 4 ge L
8º W
C/
W
)
c
= kag
38 e
ºC A
/W
)
750
500
250
0
25
50
75
100
125
150
Temperature (°C)
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
Serial-Input Constant-Current Latched LED Driver
with Open LED Detection and Dot Correction
A6275
VDD
VDD
IN
IN
Dwg. EP-010-12
Dwg. EP-010-11
OUTPUT ENABLE (active low)
LATCH ENABLE
V
VDD
DD
OUT
IN
Dwg. EP-063-6
Dwg. EP-010-13
CLOCK and SERIAL DATA IN
SERIAL DATA OUT
TRUTH TABLE
Serial
Shift Register Contents
Data Clock
Input Input I1 I2 I3 ... IN-1 IN
Serial Latch
Data Enable
Output Input
Latch Contents
I1
I2
I3
...
IN-1 IN
Output
Enable
Input
Output Contents
I1 I2 I3 ... IN-1 IN
H
H
R1 R2 ...
RN-2 RN-1
RN-1
L
L
R1 R2 ...
RN-2 RN-1
RN-1
X
R1 R2 R3 ...
RN-1 RN
RN
X
X
X
L
R1 R2 R3 ...
RN-1 RN
PN
H
P1 P2 P3 ...
PN-1 PN
L
P1 P2 P3 ... PN-1 PN
X
X
H
H H H ... H
X
X
...
P1 P2 P3 ...
L = Low Logic (Voltage) Level
X
PN-1 PN
H = High Logic (Voltage) Level
X
X
...
X = Irrelevant
X
P = Present State
H
R = Previous State
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A6275
Serial-Input Constant-Current Latched LED Driver
with Open LED Detection and Dot Correction
ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V (unless otherwise noted).
Limits
Characteristic
Symbol
Supply Voltage Range
VDD
Undervoltage Lockout
VDD(UV)
Output Current
(any single output)
Output Current Matching
IO
∆IO
(difference between any
two outputs at same VCE)
Test Conditions
Min.
Typ.
Max.
Unit
Operating
4.5
5.0
5.5
V
VDD = 0 → 5 V
3.4
–
4.0
V
VCE = 0.7 V, REXT = 250 Ω
64.2
75.5
86.8
mA
VCE = 0.7 V, REXT = 470 Ω
34.1
40.0
45.9
mA
REXT = 250 Ω
–
±1.5
±6.0
%
REXT = 470 Ω
–
±1.5
±6.0
%
–
1.0
5.0
μA
0.4 V ≤ VCE(A) = VCE(B) ≤ 0.7 V:
Output Leakage Current
ICEX
Logic Input Voltage
VIH
0.7VDD
–
VDD
V
VIL
GND
–
0.3VDD
V
SERIAL DATA OUT
Voltage
Input Resistance
Supply Current
VOH = 15 V
VOL
IOL = 500 μA
–
–
0.4
V
VOH
IOH = -500 μA
4.6
–
–
V
ENABLE Input, Pull Up
150
300
600
kΩ
LATCH Input, Pull Down
100
200
400
kΩ
REXT = open, VOE = 5 V
–
0.8
1.4
mA
REXT = 470 Ω, VOE = 5 V
3.5
6.0
8.0
mA
REXT = 250 Ω, VOE = 5 V
6.5
11
15
mA
REXT = 470 Ω, VOE = 0 V
5.0
10
14
mA
REXT = 250 Ω, VOE = 0 V
8.0
16
24
mA
RI
IDD(OFF)
IDD(ON)
Typical Data is at VDD = 5 V and is for design information only.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A6275
Serial-Input Constant-Current Latched LED Driver
with Open LED Detection and Dot Correction
SWITCHING CHARACTERISTICS at TA = 25°C, VDD = VIH = 5 V, VCE = 0.4 V, VIL = 0 V,
REXT = 470 Ω, IO = 40 mA, VL = 3 V, RL = 65 Ω, CL = 10.5 pF.
Limits
Characteristic
Propagation Delay Time
Propagation Delay Time
Symbol
tpHL
tpLH
Test Conditions
Min.
Typ.
Max.
Unit
CLOCK-OUTn
–
350
1000
ns
LATCH-OUTn
–
350
1000
ns
ENABLE-OUTn
–
350
1000
ns
CLOCK-SERIAL DATA OUT
–
40
–
ns
CLOCK-OUTn
–
300
1000
ns
LATCH-OUTn
–
300
1000
ns
ENABLE-OUTn
–
300
1000
ns
CLOCK-SERIAL DATA OUT
–
40
–
ns
Output Fall Time
tf
90% to 10% voltage
150
350
1000
ns
Output Rise Time
tr
10% to 90% voltage
150
300
600
ns
Min.
Typ.
Max.
Unit
RECOMMENDED OPERATING CONDITIONS
Characteristic
Symbol
Supply Voltage
VDD
4.5
5.0
5.5
V
Output Voltage
VO
–
1.0
4.0
V
Output Current
IO
Continuous, any one output
–
–
90
mA
IOH
SERIAL DATA OUT
–
–
-1.0
mA
IOL
SERIAL DATA OUT
–
–
1.0
mA
VIH
0.7VDD
–
VDD + 0.3
V
VIL
-0.3
–
0.3VDD
V
–
–
10
MHz
Logic Input Voltage
Clock Frequency
fCK
Conditions
Cascade operation
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
Serial-Input Constant-Current Latched LED Driver
with Open LED Detection and Dot Correction
A6275
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
C
50%
CLOCK
A
SERIAL
DATA IN
B
DATA
50%
tp
SERIAL
DATA OUT
DATA
50%
D
E
LATCH
ENABLE
OUTPUT
ENABLE
50%
LOW = ALL OUTPUTS ENABLED
tp
HIGH = OUTPUT OFF
DATA
50%
OUT N
LOW = OUTPUT ON
Dwg. WP-029-1
HIGH = ALL OUTPUTS DISABLED (BLANKED)
OUTPUT
ENABLE
50%
t pLH
F
tf
90%
OUT N
t pHL
DATA
tr
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), tsu(D) ............................. 50 ns
B. Data Active Time After Clock Pulse
(Data Hold Time), th(D) ................................. 20 ns
C. Clock Pulse Width, tw(CK) .................................. 50 ns
D. Time Between Clock Activation
and Latch Enable, tsu(L) ............................... 100 ns
E. Latch Enable Pulse Width, tw(L) ...................... 100 ns
F. Output Enable Pulse Width, tw(OE) ................... 4.5 s
50%
10%
Dwg. WP-030-1A
Serial data present at the input is transferred to the shift
register on the logic 0-to-logic 1 transition of the CLOCK input
pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The serial data
must appear at the input prior to the rising edge of the CLOCK
input waveform.
Information present at any register is transferred to the
respective latch when the LATCH ENABLE is high (serial-toparallel conversion). The latches continue to accept new data as
NOTE: Timing is representative of a 10 MHz clock. Significantly higher speeds are attainable.
Max. Clock Transition Time, tr or tf ....................... 10 s
long as the LATCH ENABLE is held high. Applications where
the latches are bypassed (LATCH ENABLE tied high) will
require that the OUTPUT ENABLE input be high during serial
data entry.
When the OUTPUT ENABLE input is high, the output sink
drivers are disabled (OFF). The information stored in the latches
is not affected by the OUTPUT ENABLE input. With the OUTPUT ENABLE input low, the outputs are controlled by the state
of their respective latches.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
Serial-Input Constant-Current Latched LED Driver
with Open LED Detection and Dot Correction
A6275
ALLOWABLE OUTPUT CURRENT AS A FUNCTION OF DUTY CYCLE
A Package
LW Package
100
100
V CE = 2 V
V CE = 2 V
V CE = 3 V
80
V CE = 1 V
80
V CE = 3 V
V CE = 4 V
60
60
V CE = 4 V
40
40
T A = +25°C
V DD = 5 V
R θJA = 60°C/W
20
0
0
20
T A = +25°C
V DD = 5 V
R θJA = 94°C/W
20
40
60
80
100
0
0
20
DUTY CYCLE IN PER CENT
40
60
80
100
DUTY CYCLE IN PER CENT
Dwg. GP-062-5
Dwg. GP-062-4A
100
100
V CE = 1 V
V CE = 2 V
80
V CE = 2 V
80
V CE = 3 V
V CE = 3 V
V CE = 4 V
60
60
V CE = 4 V
40
40
T A = +50°C
V DD = 5 V
R θJA = 60°C/W
20
T A = +50°C
V DD = 5 V
R θJA = 94°C/W
20
0
0
0
20
40
60
80
100
DUTY CYCLE IN PER CENT
0
20
40
60
80
100
DUTY CYCLE IN PER CENT
Dwg. GP-062-3
Dwg. GP-062-2A
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
Serial-Input Constant-Current Latched LED Driver
with Open LED Detection and Dot Correction
A6275
ALLOWABLE OUTPUT CURRENT AS A FUNCTION OF DUTY CYCLE (cont.)
A Package
LW Package
100
100
V CE = 0.7 V
V CE = 1 V
V CE = 1 V
80
80
V CE = 2 V
V CE = 2 V
V CE = 3 V
60
60
V CE = 3 V
V CE = 4 V
V CE = 4 V
40
40
T A = +85°C
V DD = 5 V
R θJA = 60°C/W
20
0
0
20
T A = +85°C
V DD = 5 V
R θJA = 94°C/W
20
40
60
80
0
100
0
20
DUTY CYCLE IN PER CENT
40
60
80
100
DUTY CYCLE IN PER CENT
Dwg. GP-062-1
Dwg. GP-062A
TYPICAL CHARACTERISTICS
60
40
T A = +25°C
R EXT = 500 Ω
20
0
0
0.5
1.0
1.5
2.0
V CE IN VOLTS
Dwg. GP-063
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
Serial-Input Constant-Current Latched LED Driver
with Open LED Detection and Dot Correction
A6275
Pin-out Diagrams
Package A
GROUND
SERIAL
DATA IN
Package LW
V DD
1
IO
REGULATOR
2
CLOCK
3
CK
LATCH
ENABLE
4
L
OE
16
LOGIC
SUPPLY
15
R EXT
14
SERIAL
DATA OUT
13
OUTPUT
ENABLE
REGISTER
GROUND
V DD
1
IO
REGULATOR
SERIAL
DATA IN
2
CLOCK
3
CK
LATCH
ENABLE
4
L
OE
16
LOGIC
SUPPLY
15
R EXT
14
SERIAL
DATA OUT
13
OUTPUT
ENABLE
12
OUT 7
REGISTER
12
OUT 7
OUT 0
5
6
11
OUT 6
OUT 1
6
11
OUT 6
OUT 2
7
10
OUT 5
OUT 2
7
10
OUT 5
OUT 3
8
9
OUT 4
OUT 3
8
9
OUT 4
OUT 0
5
OUT 1
LATCHES
LATCHES
TERMINAL DESCRIPTION
Terminal No.
1
2
Terminal Name
GND
Function
Reference terminal for control logic.
SERIAL DATA IN
Serial-data input to the shift-register.
3
CLOCK
4
LATCH ENABLE
5-12
OUT0-7
13
OUTPUT ENABLE
When (active) low, the output drivers are enabled; when high, all output drivers are turned OFF (blanked).
14
SERIAL DATA OUT
CMOS serial-data output to the following shift-register.
15
REXT
16
SUPPLY
Clock input terminal for data shift on rising edge.
Data strobe input terminal; serial data is latched with high-level input.
The eight current-sinking output terminals.
An external resistor at this terminal establishes the output current for all sink
drivers.
(VDD) The logic supply voltage (typically 5 V).
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
Serial-Input Constant-Current Latched LED Driver
with Open LED Detection and Dot Correction
A6275
Applications Information
The load current per bit (IO) is set by the external resistor
(REXT) as shown in the figure below.
100
V CE = 0.7 V
80
0.7 V per diode) for a group of drivers. If the available
voltage source will cause unacceptable dissipation and
series resistors or diode(s) are undesirable, a regulator
such as the Sanken Series SAI or Series SI can be used to
provide supply voltages as low as 3.3 V.
For reference, typical LED forward voltages are:
White
3.5 – 4.0 V
Blue
3.0 – 4.0 V
Green
1.8 – 2.2 V
Yellow
2.0 – 2.1 V
Amber
1.9 – 2.65 V
Red
1.6 – 2.25 V
Infrared
1.2 – 1.5 V
60
40
20
0
100
200
300
500
700
CURRENT-CONTROL RESISTANCE, R
2k
1k
EXT
3k
5k
IN OHMS
Dwg. GP-061
Package Power Dissipation (PD). The maximum allowable package power dissipation is determined as
PD(max) = (150 - TA)/RθJA.
The actual package power dissipation is
PD(act) = dc(VCE × IO × 8) + (VDD × IDD).
When the load supply voltage is greater than 3 V to 5 V,
considering the package power dissipating limits of these
devices, or if PD(act) > PD(max), an external voltage reducer (VDROP) should be used.
Load Supply Voltage (VLED). These devices are designed to operate with driver voltage drops (VCE) of
0.4 V to 0.7 V with LED forward voltages (VF) of 1.2 V to
4.0 V. If higher voltages are dropped across the driver,
package power dissipation will be increased significantly.
To minimize package power dissipation, it is recommended to use the lowest possible load supply voltage or
to set any series dropping voltage (VDROP) as
VDROP = VLED - VF - VCE
with VDROP = Io × RDROP for a single driver, or a Zener
diode (VZ), or a series string of diodes (approximately
Pattern Layout. This device has a common logic-ground
and power-ground terminal. If ground pattern layout
contains large common-mode resistance, and the voltage
between the system ground and the LATCH ENABLE or
CLOCK terminals exceeds 2.5 V (because of switching
noise), these devices may not operate correctly.
V
LED
V DROP
VF
V CE
Dwg. EP-064
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
10
Serial-Input Constant-Current Latched LED Driver
with Open LED Detection and Dot Correction
A6275
Package A 16-Pin DIP
19.05±0.25
16
+0.10
0.38 –0.05
+0.38
10.92 –0.25
+0.76
6.35 –0.25
7.62
A
1
2
For Reference Only
(reference JEDEC MS-001 BB)
Dimensions in inches, metric dimensions (mm) in brackets, for reference only
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
5.33 MAX
+0.51
3.30 –0.38
1.27 MIN
2.54
+0.25
1.52 –0.38
0.46 ±0.12
Package LW 16-Pin SOICW
10.30±0.20
4° ±4
16
1.27
0.65
16
+0.07
0.27 –0.06
10.30±0.33
7.50±0.10
9.50
A
+0.44
0.84 –0.43
2.25
1
2
1
2
0.25
B
16X
SEATING
PLANE
0.10 C
0.41 ±0.10
1.27
C
PCB Layout Reference View
SEATING PLANE
GAUGE PLANE
2.65 MAX
0.20 ±0.10
For Reference Only
Dimensions in millimeters
(reference JEDEC MS-013 AA)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B
Reference pad layout (reference IPC SOIC127P1030X265-16M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
Copyright ©2000-2008, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11
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