A6279: Serial-Input Constant-Current Latched LED Drivers with Open LED Detection

A6279
Serial-Input Constant-Current Latched
LED Drivers with Open LED Detection
Discontinued Product
This device is no longer in production. The device should not be
purchased for new design applications. Samples are no longer available.
Date of status change: October 31, 2011
Recommended Substitutions:
For existing customer transition, and for new customers or new applications, contact Allegro Sales.
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
A6279
Serial-Input Constant-Current Latched
LED Drivers with Open LED Detection
Features and Benefits
Description
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The A6279 device is specifically designed for LED display
applications. This BiCMOS device includes a CMOS shift
register, accompanying data latches, and NPN constant-current
sink drivers. The A6279 contains 16 sink drivers.
3.0 to 5.5 V logic supply range

Schmitt trigger inputs for improved noise immunity
Power-On Reset (POR)
Up to 90 mA constant-current sinking outputs
LED open circuit detection
Low-power CMOS logic and latches
High data input rate
20 ns typical staggering delay on the outputs
Internal UVLO and thermal shutdown (TSD) circuitry
The CMOS shift register and latches allow direct interfacing
with microprocessor-based systems. With a 3.3 or 5 V logic
supply, typical serial data-input rates can reach up to 25 MHz.
The LED drive current is determined by the user’s selection of
a single resistor. A CMOS serial data output permits cascading
between multiple devices in applications requiring additional
drive lines. Open LED connections can be detected and signaled
back to the host microprocessor through the SERIAL DATA
OUT pin.
Two package styles are provided: a QFN surface mount,
0.90 mm overall height nominal, and for leaded surface-mount,
a TSSOP with exposed thermal pad (type LP). The packages
are electrically identical to each other. Both packages are lead
(Pb) free, with 100% matte tin plated leadframes.
Packages:
28-pin QFN (suffix ET)
24-pin TSSOP (suffix LP)
Not to scale
Functional Block Diagram
LOGIC
SUPPLY
UVLO
SERIAL
DATA IN
VDD
CLOCK
VDD
OUTPUT
ENABLE
LATCH
ENABLE
SERIAL
DATA OUT
Serial - Parallel Shift Register
Latches
Control Logic
Block
Output Control Drivers and Open Circuit Detector
REXT
IO
Regulator
Exposed Pad
(ET and LP packages)
GND
OUT0 OUT1
OUT15 (A6279)
VLED
6278-DS, Rev. 11
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
A6279
Selection Guide
Part Number
Packing
A6279ELPTR-T*
4000 pieces per 13-in. reel
A6279EETTR-T*
1500 pieces per 7-in. reel
Package Type
Terminals
LED Drive Lines
TSSOP with exposed thermal pad
24
16
MLP surface mount
28
16
*Variant is in production but has been determined to be LAST TIME BUY. This classification indicates that the variant is obsolete and notice
has been given. Sale of the variant is currently restricted to existing customer applications. The variant should not be purchased for new design
applications because of obsolescence in the near future. Samples are no longer available. Status date change May 2, 2011. Deadline for receipt
of LAST TIME BUY orders is October 31, 2011.
Absolute Maximum Ratings
Min.
Typ.
LOGIC SUPPLY Voltage Range
Parameter
VDD
–
–
7.0
Load Supply Voltage Range
VLED
–0.5
–
17
V
IO
–
–
90
mA
IGND
–
–
1475
mA
Logic Input Voltage Range
VI
–0.4
–
VDD
+ 0.4
V
Operating Temperature Range (E)
TA
–40
–
85
°C
OUTx Current (any single output)
Ground Current
Symbol
Conditions
Max. Units
V
Junction Temperature
TJ
–
–
150
°C
Storage Temperature Range
TS
–55
–
150
°C
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
A6279
15 OUT5
1
24
LOGIC SUPPLY
2
23
REXT
CLOCK
3
22
SERIAL DATA OUT
LATCH ENABLE
4
21
OUTPUT ENABLE
OUT0
5
20
OUT15
OUT1
6
19
OUT14
OUT2
7
18
OUT13
OUT3
8
17
OUT12
OUT4
9
16
OUT11
OUT5
10
15
OUT10
7
16 OUT6
GND
SERIAL DATA IN
OUT6
11
14
OUT9
CLOCK
17 OUT7
18 NC
19 OUT8
20 OUT9
21 OUT10
Pin-out Diagrams
OUT7
12
13
OUT8
OUT11 22
14 OUT4
OUT12 23
13 OUT3
OUT13 24
12 OUT2
EP
OUT14 25
11 OUT1
10 OUT0
OUT15 26
SERIAL DATA IN
GND
NC
LOGIC SUPPLY
REXT
SERIAL DATA OUT
6
NC
5
8
4
NC 28
3
LATCH ENABLE
2
9
1
OUTPUT ENABLE 27
Package ET
EP
Package LP
Terminal List Table
Number
Name
Function
LP
ET
1
5
GND
2
6
SERIAL DATA IN
3
7
CLOCK
4
9
LATCH ENABLE
5 TO 20
10 to 26
OUTx
21
27
OUTPUT ENABLE
(Active low) Set low to enable output drivers; set high to turn OFF
(blank) all output drivers
22
1
SERIAL DATA OUT
CMOS serial-data output; for cascading to the next device (to that
device SERIAL DATA IN pin); for reading OCD bits.
23
2
REXT
24
3
LOGIC SUPPLY
–
4, 8, 18, 28
NC
No connection
–
–
EP
Exposed thermal pad for heat dissipation
Reference terminal for logic ground and power ground
Serial-data input to the shift-register
Clock input terminal; data is shifted on the rising edge of the clock.
Data strobe input terminal; serial data is latched with a high-level input
Current-sinking output terminals
An external resistor at this terminal establishes the output current for all
of the sink drivers.
(VDD) Logic supply voltage (typically 3.3 or 5.0 V)
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A6279
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
OPERATING CHARACTERISTICS
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max
Unit
ELECTRICAL CHARACTERISTICS valid at TA = 25°C, VDD = 3.0 to 5.5 V, unless otherwise noted
Operating
3.0
5.0
5.5
V
LOGIC SUPPLY Voltage Range
VDD
VDD = 0.0 → 5.0 V
2.4
–
2.85
V
Undervoltage Lockout
VDD(UV)
VDD = 5.0 → 0.0 V
2.15
–
2.55
V
VCE = 0.7 V, REXT = 225 Ω
64.2
75.5
86.8
mA
Output Current (any single output)
IO
34.1
40.0
45.9
mA
VCE = 0.7 V, REXT = 470 Ω
VCE = 0.6 V, REXT = 3900 Ω
4.25
5.0
5.75
mA
VCE(A) = VCE(B) = 0.7 V, REXT = 225 Ω
–
+1.0
+6.0
%
Output Current Matching (difference between any two
VCE(A) = VCE(B) = 0.7 V, REXT = 470 Ω
ΔIO
–
+1.0
+6.0
%
outputs at the same VCE )
VCE(A) = VCE(B) = 0.6 V, REXT = 3900 Ω
–
+1.0
+6.0
%
Output Leakage Current
ICEX
VOH = 15 V
–
1.0
5.0
μA
0.7VDD
–
VDD
V
VIH
Logic Input Voltage
VIL
GND
–
0.3VDD
V
Logic Input Voltage Hysteresis
VIhys
All digital inputs
200
–
400
mV
VOL
IOL = 500 μA
–
–
0.4
V
SERIAL DATA OUT Voltage
IOH = –500 μA
VDD– 0.4
–
–
V
VOH
OUTPUT ENABLE input, Pull Up
150
300
600
kΩ
Input Resistance
RI
LATCH ENABLE input, Pull Down
100
200
400
kΩ
REXT = open, VOE = 5 V
–
–
1.4
mA
IDD(OFF) REXT = 470 Ω, VOE = 5 V
–
–
5.0
mA
REXT = 225 Ω, VOE = 5 V
–
–
8.0
mA
LOGIC SUPPLY Current
REXT = 3900 Ω, VOE = 0 V
–
–
3.0
mA
REXT = 470 Ω, VOE = 0 V
IDD(ON)
–
–
18.0
mA
REXT = 225 Ω, VOE = 0 V
–
–
32.0
mA
Thermal Shutdown Temperature
TJTSD
Temperature increasing
–
165
–
°C
Thermal Shutdown Hysteresis
TJTSDhys
–
15
–
°C
Open LED Detection Threshold
VCE(ODC) IO > 5 mA, VCE ≥ 0.6 V
–
0.30
–
V
SWITCHING CHARACTERISTICS valid at TA = 25°C, VDD = VIH = 3.0 to 5.5 V, VCE = 0.7 V, VIL = 0 V, REXT = 470 Ω, IO = 40 mA, VLED = 3 V, RLED =
58 Ω, CLED = 10 pF, unless otherwise noted
CLOCK Pulse Width
thigh, tlow
20
–
–
ns
10
–
–
ns
SERIAL DATA IN Setup Time
tSU(D)
SERIAL DATA IN Hold Time
tH(D)
10
–
–
ns
LATCH ENABLE Setup Time
tSU(LE)
20
–
–
ns
LATCH ENABLE Hold Time
tH(LE)
20
–
–
ns
OUTPUT ENABLE Set Up Time
tSU(OE)
40
–
–
ns
Normal Mode
OUTPUT ENABLE Hold Time
tH(OE)
20
–
–
ns
OUTPUT ENABLE Pulse Width
tW(OE)
1200
–
–
ns
CLOCK to SERIAL DATA OUT Propagation Delay Time
tP(DO)
30
–
–
ns
–
75
–
ns
OUTPUT ENABLE to OUT0 Propagation Delay Time
tP(OE)
Staggering Delay (between consecutive outputs)
tD
10
20
40
ns
Total Delay Time (15 × tD)
tDtotal
–
300
–
ns
CLOCK Pulse Width
thigh, tlow
20
–
–
ns
20
–
–
ns
SERIAL DATA IN Setup Time
tSU(D)
SERIAL DATA IN Hold Time
tH(D)
20
–
–
ns
LATCH ENABLE Setup Time
tSU(LE)
40
–
–
ns
LATCH ENABLE Hold Time
tH(LE)
20
–
–
ns
OUTPUT ENABLE Set Up Time
tSU(OE)
40
–
–
ns
Test Mode, VDD = 4.5 to 5.5 V
20
–
–
ns
OUTPUT ENABLE Hold Time
tH(OE)
OUTPUT ENABLE Pulse Width*
tW(OE)
2.0
–
–
us
CLOCK to SERIAL DATA OUT Propagation Delay Time
tP(DO)
30
–
–
ns
OUTPUT ENABLE to OUT0 Propagation Delay Time
tP(OE)
–
75
–
ns
Staggering Delay (between consecutive outputs)
tD
10
20
40
ns
Total Delay Time (15 × tD)
tDtotal
–
300
–
ns
Output Fall Time
tf
90% to 10% voltage
–
75
150
ns
Output Rise Time
tr
10% to 90% voltage
–
75
150
ns
*See LED Open Circuit Detection (Test) mode timing diagram.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
A6279
Truth Table
Serial
Data
Input
Clock
Input
Shift Register Contents
I0
I1
I2
…
In-1 In
Serial
Data
Out
H
H R0 R1 …
Rn-2 Rn-1
Rn-1
L
L R0 R1 …
Rn-2 Rn-1
Rn-1
X
R0 R1 R2 …
Rn-1 Rn
Rn
X
X
X X
…
P0 P1 P2 …
X
Pn-1 Pn
Latch
Enable
Input
Latch Contents
I0
I1
I2
…
Output
Enable
Input
In-1 In
Output Contents
I0
I1
I2
…
In-1 In
X
L
R0 R1 R2 …
Rn-1 Rn
Pn
H
P0 P1 P2 …
Pn-1 Pn
L
P0 P1 P2 …
Pn-1 Pn
X
X
H
H
H
X X
…
X
H H
…
H
L = Low logic (voltage) level
H = High logic (voltage) level
X = Don’t care
P = Present state
R = Previous state
n = 15
Inputs and Outputs Equivalent Circuits
VDD
IN
VDD
IN
OUTPUT ENABLE
(active low)
VDD
VDD
IN
LE
CLOCK and
SERIAL DATA IN
OUT
LATCH ENABLE
SERIAL DATA OUT
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
A6279
Normal Mode Timing Requirements
CLOCK
0
1
n
thigh tlow
SERIAL
DATA IN
SERIAL
DATA OUT
SDI n
SDI n-1
SDI 0
tSU(D) tH(D)
SDO n
Don't Care
tp(DO)
LATCH
ENABLE
tSU(LE) tH(LE)
tW(OE)
OUTPUT
ENABLE
tW(OE)
tSU(OE)
OUT0
Don't Care
tP(OE)
OUT1
tP(OE)
Don't Care
Logic Levels: VDD and GND
tD
tD
Don't Care
OUTn
n = 15
tD(Total)
tD(Total)
LED Open Circuit Detection (Test) Mode Timing Requirements
(A) To enter LED OCD mode, a minimum of one CLOCK pulse is required after LATCH ENABLE is brought back low.
CLOCK
1
thigh t low
OUTPUT
ENABLE
tSU(OE1)
tH(OE1)
LATCH
ENABLE
tSU(LE1)
tH(LE1)
(B) To output the latched error code, OUTPUT ENABLE must be held low a minimum of 3 CLOCK cycles.
CLOCK
tW(OE1)
OUTPUT
ENABLE
Logic Levels: VDD and GND
3
2
1
SERIAL
DATA OUT
SDO n
Don't Care
SDO n-1
SDO n-2
SDO 0
(C) When returning to Normal mode, a minimum of three CLOCK pulses is required after OUTPUT ENABLE is brought back high.
CLOCK
OUTPUT
ENABLE
thigh tlow
tSU(OE1)
1
2
3
tH(OE1)
LATCH
ENABLE
n = 15
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
A6279
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
Functional Description
Normal Mode
Serial data present at the SERIAL DATA IN input is transferred
to the shift register on the logic 0-to-logic 1 transition of the
CLOCK input pulse. On succeeding CLOCK pulses, the register
shifts data towards the SERIAL DATA OUT pin. The serial data
must appear at the input prior to the rising edge of the CLOCK
input waveform.
Data present in any register is transferred to the respective latch
when the LATCH ENABLE input is high (serial-to-parallel conversion). The latches continue to accept new data as long as the
LATCH ENABLE input is held high.
Applications where the latches are bypassed (LATCH ENABLE
tied high) will require that the OUTPUT ENABLE input be high
during serial data entry. When the OUTPUT ENABLE input is
high, the output sink drivers are disabled (OFF).
The data stored in the latches is not affected by the OUTPUT
ENABLE input. With the OUTPUT ENABLE input active (low),
the outputs are controlled by the state of their respective latches.
Open circuit detection does not take place until the sequence in
Panel B on page 7 is performed. During this sequence, the OE
pin must be held low for a minimum of 2 μs (tW(OE1)) to ensure
proper settling of the output currents and be given a minimum of
three CLOCK pulses. During the period that the OE pin is low
(active), OCD testing begins. The VCE voltage on each of the
output pins is compared to the Open LED Detection Theshold,
VCE(OCD). If the VCE of an enabled output is lower than VCE(OCD),
an error bit value of 0 is set in the corresponding shift register. A
value of 1 will be set if no error is detected. If a particular output
is not enabled, a 0 will be set. The error codes are summarized in
the following table:
Output State Test Condition Error Code Meaning
Output State
Test Condition
Error Code
Meaning
OFF
N/A
0
N/A
VCE < VCE(OCD)
0
Open/TSD
VCE ≥ VCE(OCD)
1
Normal
ON
LED Open Circuit Detection (Test) Mode
The LED Open Circuit Detection (OCD) mode, or Test mode,
is entered by clocking in the LED OCD mode initialization
sequence on the OUTPUT ENABLE (OE) and LATCH ENABLE
(LE) pins. In Normal mode, the OE and LE pins do not change
states while the CLOCK signal is cycling. The initialization
sequence is shown in panel A of the LED OCD timing requirements diagram on page 7.
Note: Each step event during mode sequencing happens on the
leading edge of the CLOCK signal. Five step events (CLOCK
pulses) are required to enter OCD mode and five step events are
required to return to Normal mode.
A pattern, such as all highs, should first be loaded into the registers and latched leaving LE low. The device is then sequenced
into LED OCD mode. It should be noted that data is still being
sent through the shift registers while entering the LED OCD
mode. However, this data is not latched when the LE pin goes
high and sees a CLOCK pulse during the initialization sequence.
After the testing process, setting the OE pin high causes the shift
registers to latch the error code data where it can then be clocked
out of the SERIAL DATA OUT pin. The OCD latching sequence
(OE low, 3 CLOCK pulses, OE high as shown in panel B of the
LED OCD timing diagram) can then be repeated if necessary to
look for intermittent contact problems.
The state of the outputs can be programmed with new data at any
time while in LED OCD mode (the same as in Normal mode).
This allows specific patterns to be tested for open circuits. The
pattern that is latched will then be tested during the OCD latching
sequence and the resulting bit values can be clocked out of the
SERIAL DATA OUT pin.
Note: LED Open Circuit Detection will not work properly if the
current is being externally limited by resistors to within the set
current limit for the device.
To return to Normal mode, perform the clocking sequence shown
in panel C of the timing diagram on the OE and LE pins.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
A6279
LED current. The output current is determined by the value of
an external current-control resistor (REXT). The relationship of
these parameters is shown in figure 1. Typical characteristics for
output current and VCE are shown in figure 2 for common values
of REXT.
Constant Current (REXT)
The A6279 allows the user to set the magnitude of the constant
current to the LEDs. Once set, the current remains constant
regardless of the LED voltage variation, the supply voltage
variation, or other circuit parameters that could otherwise affect
Figure 1. Output Current versus Current Control Resistance
TA= 25°C, VCE = 0.7 V
90
80
IO (mA/Bit)
70
60
50
40
30
20
10
0
100
100
200
300
300
500
500
700
1k
1K
2k2K
3k
3K
5k
5K
REXT (Ω)
Figure 2. Output Current versus Device Voltage Drop
TA= 25°C
90
80
REXT = 225 Ω
IO (mA/Bit)
70
60
50
REXT = 470 Ω
40
30
20
REXT = 3900 Ω
10
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
VCE (V)
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
A6279
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
Undervoltage Lockout
The 20 ns delays are cumulative across all the outputs. Under any
The A6279 includes an internal under-voltage lockout (UVLO)
of the above conditions, the state of OUT0 gets set after a typical
circuit that disables the outputs in the event that the logic supply
propagation delay, tP(OE). OUT1 will get set 20 ns after OUT0,
voltage drops below a minimum acceptable level. This feature
and so forth. OUT15 will get set after 300 ns (15 × 20 ns) plus
prevents the display of erroneous information, a necessary func-
tP(OE).
tion for some critical applications.
Note: The maximum CLOCK frequency is reduced in applica-
Upon recovery of the logic supply voltage after a UVLO event,
tions where both the OUTPUT ENABLE pin is held low and the
and on power-up, all internal shift registers and latches are set
LATCH ENABLE pin is held high continuously, and the outputs
to 0. The A6279 is then in Normal mode.
change state on the CLOCK edges. The staggering delay could
Output Staggering Delay
The A6279 has a 20 ns delay between each output. The stagger-
cause spurious output responses at CLOCK speeds greater than
1 MHz.
ing of the outputs reduces the in-rush of currents onto the power
Thermal Shutdown
and ground planes. This aids in power supply decoupling and
When the junction temperature of the A6279 reaches the thermal
EMI/EMC reduction.
shutdown temperature threshold, TJTSD (165°C typical), the out-
The output staggering delay occurs under the following conditions:
puts are shut off until the junction temperature cools down below
the recovery threshold, TJTSD– TJTSDhys (15°C typical). The shift
register and output latches will remain active during a TSD event.
• OUTPUT ENABLE is pulled low
Therefore, there is no need to reset the data in the output latches.
• OUTPUT ENABLE is held low and LATCH ENABLE is
In LED OCD mode, if the junction temperature reaches the Ther-
pulled high
• OUTPUT ENABLE is held low, LATCH ENABLE is held high,
and CLOCK is pulled high
mal Shut Down threshold, the outputs will turn off, as in Normal
mode operation. However, all of the shift registers will be set
with 0, the error bit value.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
A6279
Application Information
Load Supply Voltage (VLED)
These devices are designed to operate with driver voltage
drops (VCE) of 0.7 to 3V, with an LED forward voltage, VF , of
1.2 to 4.0 V. If higher voltages are dropped across the driver,
package power dissipation will increase significantly. To minimize package power dissipation, it is recommended to use the
lowest possible load supply voltage, VLED, or to set any series
voltage dropping, VDROP , according to the following formula:
VDROP = VLED – VF – VCE ,
with VDROP = IO× RDROP for a single driver or for a Zener diode
(VZ), or for a series string of diodes (approximately 0.7 V per
diode) for a group of drivers (see figure 3). If the available voltage source, VLED, will cause unacceptable power dissipation and
series resistors or diodes are undesirable, a voltage regulator can
be used to provide supply voltages.
For reference, typical LED forward voltages are:
LED Type
VF (V)
White
3.5 to 4.0
Blue
3.0 to 4.0
Green
1.8 to 2.2
Yellow
2.0 to 2.1
Amber
1.9 to 2.65
Red
1.6 to 2.25
Infrared
1.2 to 1.5
Pattern Layout
This device has a common logic ground and power ground
terminal, GND. For the LP package, the GND pin should be tied
to the exposed metal pad, EP, allowing the ground plane copper
to be used to dissipate heat. If the ground pattern layout contains
large common mode resistance, and the voltage between the
system ground and the LATCH ENABLE, OUTPUT ENABLE,
or CLOCK terminals exceeds 2.5 V (because of switching noise),
these devices may not work properly.
Package Power Dissipation (PD)
The maximum allowable package power dissipation based on
package type is determined by:
PD(max) = (150 – TA) / RJA ,
where RJA is the thermal resistance of the package, determined
experimentally. Power dissipation levels based on the package
are shown in the Package Thermal Characteristics section (see
page 14).
The actual package power dissipation is determined by:
PD(act) = DC × (VCE × IO× 16) + (VDD× IDD) ,
where DC is the duty cycle. The value 16 represents the maximum number of available device outputs for the A6279, used for
the worst-case scenario (displaying all 16 LEDs).
When the load suppy voltage, VLED, is greater than 3 to 5 V, and
PD(act) > PD(max), an external voltage reducer (VDROP) must be
used (see figure 3).
Reducing the percent duty cycle, DC, will also reduce power dissipation. Typical results are shown on the following pages.
VLED
VLED
VLED
VDROP
VDROP
VDROP
VF
VF
VF
VCE
VCE
VCE
Figure 3. Typical appplications for voltage drops
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
10
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
A6279
Allowable Output Current versus Duty Cycle, A6279
VDD = 5 V
A Package, TA = 25°C
A Package, TA = 50°C
90
90
IO (mA/Bit)
90
A Package, TA = 85°C
0
0
0
0
100
0
DC (%)
100
0
100
DC (%)
LP Package, TA = 25°C
DC (%)
LP Package, TA = 50°C
90
90
IO (mA/Bit)
90
LP Package, TA = 85°C
0
0
0
100
0
0
DC (%)
100
0
100
DC (%)
LW Package, TA = 25°C
DC (%)
LW Package, TA = 50°C
LW Package, TA = 85°C
90
90
IO (mA/Bit)
90
0
0
0
100
DC (%)
0
0
100
DC (%)
0
100
DC (%)
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
A6279
Package Thermal Characteristics
Characteristic
Package Thermal Resistance
Symbol
RθJA
Test Conditions*
Value
Unit
LP package, 24-pin, measured on 4-layer board based on JEDEC standard
28
°C/W
ET package, 24-pin, measured on 4-layer board based on JEDEC standard
32
°C/W
*Additional thermal information is available on the Allegro Web site.
Allowable Package Power Dissipation (W)
5.0
4.0
LP
,R
ET
, R QJA 2
8°
QJ
C/
A 3
W
2°
C/
W
3.0
2.0
1.0
0
25
50
75
100
125
Ambient Temperature, TA (°C)
150
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
12
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
A6279
Package LP, 24-pin TSSOP with Exposed Thermal Pad
7.80 ±0.10
24
0.65
0.45
4° ±4
+0.05
0.15 –0.06
B
3.00
4.40 ±0.10
6.40 ±0.20
A
1
6.10
(1.00)
2
4.32
0.25
24X
SEATING
PLANE
0.10 C
+0.05
0.25 –0.06
3.00
0.60 ±0.15
0.65
1.20 MAX
0.15 MAX
C
SEATING PLANE
GAUGE PLANE
1.65
4.32
C
PCB Layout Reference View
For Reference Only
(reference JEDEC MO-153 ADT)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Exposed thermal pad (bottom surface)
C Reference land pattern layout (reference IPC7351
TSOP65P640X120-25M); all pads a minimum of 0.20 mm from all
adjacent pads; adjust as necessary to meet application process
requirements and PCB layout tolerances; when mounting on a multilayer
PCB, thermal vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
13
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
A6279
Package ET, 28-pin QFN
0.30
5.00 ±0.15
1.15
28
1
2
0.50
28
1
A
5.00 ±0.15
3.15
4.80
3.15
29X
D
SEATING
PLANE
0.08 C
C
4.80
C
+0.05
0.25 –0.07
PCB Layout Reference View
0.90 ±0.10
0.50
For Reference Only
(reference JEDEC MO-220VHHD-1)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
+0.20
0.55 –0.10
A Terminal #1 mark area
B
3.15
2
1
28
3.15
B Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
C Reference land pattern layout (reference IPC7351
QFN50P500X500X100-29V1M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
D Coplanarity includes exposed thermal pad and terminals
Copyright ©2005-2011, Allegro MicroSystems, Inc.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
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Allegro MicroSystems, Inc.
115 Northeast Cutoff
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1.508.853.5000; www.allegromicro.com
14
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