A6810: DABiC-IV 10-Bit Serial-Input Latched Source Drivers with Active Pull-Downs

A6810
10-Bit Serial Input Latched Source Driver
Discontinued Product
This device is no longer in production. The device should not be
purchased for new design applications. Samples are no longer available.
Date of status change: November 1, 2010
Recommended Substitutions:
For existing customer transition, and for new customers or new applications, contact Allegro Sales.
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
A6810
10-Bit Serial Input Latched Source Driver
Features and Benefits
Description
▪ Controlled output slew rate
▪ High-speed data storage
▪ 60 V minimum output breakdown
▪ High data-input rate
▪ PNP active pull-downs
▪ Low output-saturation voltages
▪ Low-power CMOS logic and latches
▪ Improved replacements for TL4810x, UCN5810x, and
UCQ5810x
The A6810 combines 10-bit CMOS shift registers,
accompanying data latches, and control circuitry with bipolar
sourcing outputs and PNP active pull-downs. Designed
primarily to drive vacuum-fluorescent (VF) displays, the 60 V
and –40 mA output ratings also allow this device to be used in
many other peripheral power driver applications. The A6810
features an increased data input rate (compared with the older
UCN/UCQ5810-F) and a controlled output slew rate.
Packages:
The CMOS shift register and latches allow direct interfacing
with microprocessor-based systems. With a 3.3 or 5 V logic
supply, serial data-input rates of at least 10 MHz can be
attained
A CMOS serial data output permits cascaded connections in
applications requiring additional drive lines. Similar devices
are available as the A6812 (20-bit) and A6818 (32-bit).
18-pin DIP
(A package)
Not to scale
20-pin SOICW
(LW package)
The A6810 output source drivers are NPN Darlingtons, capable
of sourcing up to 40 mA. The controlled output slew rate reduces
electromagnetic noise, which is an important consideration in
systems that include telecommunications and microprocessors,
and to meet government emissions regulations. For inter-digit
Continued on the next page…
Functional Block Diagram
26182.124I
10-Bit Serial Input Latched Source Driver
A6810
Description (continued)
blanking, all output drivers can be disabled and all sink drivers
turned on with a BLANKING input high. The PNP active pulldowns can sink at least 2.5 mA.
The A6810 is available in three temperature ranges for optimum
performance in commercial (S), industrial (E), and automotive (K)
applications. It is provided in two package styles, through-hole
DIP (package A) and surface-mount SOIC (package LW). Copper
leadframes, low logic-power dissipation, and low output-saturation
voltages allow all devices to source 25 mA from all outputs
continuously over the full operating temperature range.
The lead (Pb) free versions have 100% matte tin leadframe
plating.
Selection Guide
Pb-free
Packing
Ambient Temperature, TA (°C)
A6810EA-T
Part Number
Yes
21 pieces/tube
–40 to 85
A6810SA-T
Yes
21 pieces/tube
–20 to 85
A6810ELWTR-T
Yes
1000 pieces/13-in. reel
–40 to 85
A6810KLWTR-T
Yes
1000 pieces/13-in. reel
–40 to 125
Package
18-pin DIP
20-pin SOIC-W
A6810SLWTR-T
Yes
1000 pieces/13-in. reel
–20 to 85
*Variant is in production but has been determined to be LAST TIME BUY. This classification indicates that the variant is obsolete and
notice has been given. Sale of the variant is currently restricted to existing customer applications. The variant should not be purchased
for new design applications because of obsolescence in the near future. Samples are no longer available. Status date change May 3,
2010. Deadline for receipt of LAST TIME BUY orders is October 29, 2010.
Absolute Maximum Ratings*
Characteristic
Symbol
Notes
Rating
Units
Logic Supply Voltage
VDD
7.0
V
Driver Supply Voltage
VBB
60
V
Input Voltage Range
VIN
–0.3 to VDD + 0.3
V
Continuous Output Current Range
IOUT
–40 to 15
mA
Operating Ambient Temperature
Maximum Junction Temperature
Storage Temperature
Range E
–40 to 85
ºC
Range K
–40 to 125
ºC
Range S
–20 to 85
ºC
TJ(max)
150
ºC
Tstg
–55 to 125
ºC
TA
*Caution: These CMOS devices have input static protection (Class 2) but are still susceptible to damage if exposed to extremely high
static electrical charges.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A6810
10-Bit Serial Input Latched Source Driver
Pin-out Diagrams
Thermal Characteristics
Characteristic
Package Thermal Resistance
Symbol
RθJA
Test Conditions*
Value Units
Package A, 1-layer PCB with copper limited to solder pads
65
ºC/W
Package LW, 1-layer PCB with copper limited to solder pads
90
ºC/W
*Additional thermal information available on the Allegro website.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A6810
10-Bit Serial Input Latched Source Driver
ELECTRICAL CHARACTERISTICS at TA = +25°C (A6810S-) or over operating temperature range (A6810E-),
VBB = 60 V, logic supply operating voltage VDD = 3.0 to 5.5 V; unless otherwise noted
Characteristic
Output Leakage Current
Output Voltage
Symbol
ICEX
Test Conditions
VOUT = 0 V
Limits @ VDD = 3.3 V
Limits @ VDD = 5 V
Mln.
Typ.
Max.
Min.
Typ.
Max.
Units
—
<-0.1
-15
—
<-0.1
-15
μA
57.5
58.3
—
57.5
58.3
—
V
VOUT(1)
IOUT = -25 mA
VOUT(0)
IOUT = 1 mA
—
1.0
1.5
—
1.0
1.5
V
Output Pull-Down Current
IOUT(0)
VOUT = 5 V to VBB
2.5
5.0
—
2.5
5.0
—
mA
Input Voltage
VIN(1)
2.2
—
—
3.3
—
—
V
VIN(0)
—
—
1.1
—
—
1.7
V
Input Current
Input Clamp Voltage
Serial Data Output Voltage
Maximum Clock Frequency
Logic Supply Current
IIN(1)
VIN = VDD
—
<0.01
1.0
—
<0.01
1.0
μA
IIN(0)
VIN = 0 V
—
<-0.01
-1.0
—
<-0.01
-1.0
μA
IIN = -200 μA
—
-0.8
-1.5
—
-0.8
-1.5
V
VOUT(1)
IOUT = -200 μA
2.8
3.05
—
4.5
4.75
—
V
VOUT(0)
IOUT = 200 μA
—
0.15
0.3
—
0.15
0.3
V
10*
—
—
10*
—
—
MHz
VIK
fc
IDD(1)
All Outputs High
—
0.25
0.75
—
0.3
1.0
mA
IDD(0)
All Outputs Low
—
0.25
0.75
—
0.3
1.0
mA
IBB(1)
All Outputs High, No Load
—
1.5
3.0
—
1.5
3.0
mA
IBB(0)
All Outputs Low
—
0.2
20
—
0.2
20
μA
tdis(BQ)
CL = 30 pF, 50% to 50%
—
0.7
2.0
—
0.7
2.0
μs
ten(BQ)
CL = 30 pF, 50% to 50%
—
1.8
3.0
—
1.8
3.0
μs
tp(STH-QL)
RL = 2.3 kΩ, CL ≤ 30 pF
—
0.7
2.0
—
0.7
2.0
μs
tp(STH-QH)
RL = 2.3 kΩ, CL ≤ 30 pF
—
1.8
3.0
—
1.8
3.0
μs
Output Fall Time
tf
RL = 2.3 kΩ, CL ≤ 30 pF
2.4
—
12
2.4
—
12
μs
Output Rise Time
tr
RL = 2.3 kΩ, CL ≤ 30 pF
2.4
—
12
2.4
—
12
μs
Output Slew Rate
dV/dt
RL = 2.3 kΩ, CL ≤ 30 pF
4.0
—
20
4.0
—
20
V/μs
IOUT = ±200 μA
—
50
—
—
50
—
ns
Load Supply Current
Blanking-to-Output Delay
Strobe-to-Output Delay
Clock-to-Serial Data Out Delay tp(CH-SQX)
Negative current is defined as coming out of (sourcing) the specified device terminal.
Typical data is is for design information only and is at TA = +25°C.
*Operation at a clock frequency greater than the specified minimum value is possible but not warranteed.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A6810
10-Bit Serial Input Latched Source Driver
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
C
50%
CLOCK
A
SERIAL
DATA IN
B
DATA
50%
t p(CH-SQX)
SERIAL
DATA OUT
DATA
50%
D
50%
STROBE
BLANKING
E
LOW = ALL OUTPUTS ENABLED
tp(STH-QH)
tp(STH-QL)
90%
DATA
OUT N
10%
Dwg. WP-029
HIGH = ALL OUTPUTS BLANKED (DISABLED)
BLANKING
50%
t dis(BQ)
tr
t en(BQ)
OUT N
tf
90%
10%
DATA
50%
Dwg. WP-030A
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), tsu(D) ........................................... 25 ns
B. Data Active Time After Clock Pulse
(Data Hold Time), th(D) ................................................ 25 ns
C. Clock Pulse Width, tw(CH) ................................................. 50 ns
D. Time Between Clock Activation and Strobe, tsu(C) ......... 100 ns
E. Strobe Pulse Width, tw(STH) .............................................. 50 ns
NOTE – Timing is representative of a 10 MHz clock. Higher
speeds may be attainable; operation at high temperatures will
reduce the specified maximum clock frequency.
Serial Data present at the input is transferred to the shift
register on the logic “0” to logic “1” transition of the CLOCK
input pulse. On succeeding CLOCK pulses, the registers shift
data information towards the SERIAL DATA OUTPUT. The
SERIAL DATA must appear at the input prior to the rising edge
of the CLOCK input waveform.
Information present at any register is transferred to the
respective latch when the STROBE is high (serial-to-parallel
conversion). The latches will continue to accept new data as
long as the STROBE is held high. Applications where the
latches are bypassed (STROBE tied high) will require that the
BLANKING input be high during serial data entry.
When the BLANKING input is high, the output source
drivers are disabled (OFF); the PNP active pull-down sink
drivers are ON. The information stored in the latches is not
affected by the BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of their respective
latches.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
10-Bit Serial Input Latched Source Driver
A6810
TRUTH TABLE
Serial
Shift Register Contents
Data Clock
Input Input I1 I2 I3 ... IN-1 IN
Serial
Data Strobe
Output Input
Latch Contents
I1
I2
I3
...
IN-1
Output Contents
IN Blanklng
I1 I2 I3 ... IN-1 IN
H
H
R1 R2 ...
RN-2 RN-1
RN-1
L
L
R1 R2 ...
RN-2 RN-1
RN-1
X
R1 R2 R3 ...
RN-1 RN
RN
X
X
X
L
R1 R2 R3 ...
RN-1 RN
PN
H
P1 P2 P3 ...
PN-1 PN
L
P1 P2 P3 ... PN-1 PN
X
X
H
L
X
X
...
P1 P2 P3 ...
X
PN-1 PN
X
X
...
X
L
L
... L
L
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
10-Bit Serial Input Latched Source Driver
A6810
Package A 18-Pin DIP
22.86 ±0.51
18
+0.10
0.25 –0.05
+0.76
6.35 –0.25
+0.38
10.92 –0.25
7.62
A
1
2
5.33 MAX
+0.51
3.30 –0.38
2.54
+0.25
1.52 –0.38
0.46 ±0.12
SEATING
PLANE
C
All dimensions nominal, not for tooling use
(reference JEDEC MS-001 AC)
Dimensions in inches
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
Package LW 20-Pin SOICW
12.80±0.20
4° ±4
20
20
+0.07
0.27 –0.06
7.50±0.10
10.30±0.33
A
1
2.25
9.50
+0.44
0.84 –0.43
2
1
2
0.65
0.25
20X
SEATING
PLANE
0.10 C
0.41 ±0.10
1.27
C
SEATING PLANE
GAUGE PLANE
1.27
B PCB Layout Reference View
2.65 MAX
0.20 ±0.10
For Reference Only
Dimensions in millimeters
(Reference JEDEC MS-013 AC)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Reference pad layout (reference IPC SOIC127P1030X265-20M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
A6810
10-Bit Serial Input Latched Source Driver
Copyright ©1998-2010, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
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